From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ADD9AC3271E for ; Mon, 8 Jul 2024 16:28:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:Message-ID:In-Reply-To:Subject:cc:To:Date:From:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=D5Xf4RK3Ne0hU64SbypIIK+/YKh18QvebRWcWPeLUHs=; b=g8WUeZ2WxWGpXOA+g8VgqCr5HD GHbJsRsO87BYXirmES5eonOWRSOXT4X8Wzganbz+3wHrQ/6SfrHC3s8tDyxlU2WY3qfqXC3e/8r1t 8BIhr4O6vfG5Dq+qrU0CjOVLUDE6TFWhOPSfMaaC1BE0LUA9/R/ygc/vcGdkhbi2vlTXlPiK19674 ZNpb5/xI2c+Kq2mkLhrgXOTl088RiSr6Pn0SRZg/ay+xegqZ7OiWF1L8Jk/8OW60z9CVjCgqD2SJZ DxtFBVBjIACjUPuAwv7SYL2my6x+2GGmWjSm63CWNWycZoCE9n5FhXtTxha4YAsHfJSxcfmvAX7ol 5leT7VQg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sQrDs-00000004R8Q-0iVE; Mon, 08 Jul 2024 16:28:16 +0000 Received: from mgamail.intel.com ([192.198.163.13]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sQrDc-00000004R76-2rol for linux-arm-kernel@lists.infradead.org; Mon, 08 Jul 2024 16:28:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720456081; x=1751992081; h=from:date:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=24iMxEki4F/1ZL4b6Dk55X86isgnP+CUn/+e4BSziiU=; b=UyAdr8Y6NeI2dwoirYPGBt5BIVsMhL+V9mwk9dv+RKFEIaoEjGMl22iI 8IZfxJu1q+zplJw1+bxkTnXi4xbSz7qtquBr4wkNcw/asRJcgG/D/QvQg pbj2scQ0v0IWNNXftBUN0GDFasiiqQaUUqBH+CJ5B3EajdHxOpZer6P2z 6zEDXoCVZjQOp2uIU1b9E/lfdR83fok3ME8CbYvY9yvSHyYK7CwE5mas8 jwTNxCsCNQxXBSNY1cB+rCMHtsUFJo16Z/rhTG8zstAIkoJzS6jymFMuD eWJ2l85v4hXciOHGwQK/udH0S86t1BG/v1/pfxOSPWUqNZNdUtnUxxaM6 A==; X-CSE-ConnectionGUID: aVFna+/DQiOaw9A5zKKfxA== X-CSE-MsgGUID: 66bK8ws7SO68T1LjgpaUvg== X-IronPort-AV: E=McAfee;i="6700,10204,11127"; a="20570720" X-IronPort-AV: E=Sophos;i="6.09,192,1716274800"; d="scan'208";a="20570720" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2024 09:27:59 -0700 X-CSE-ConnectionGUID: mIW8md8iS6CS6SuawiViAQ== X-CSE-MsgGUID: QSluXyhRTTui3feMawuu9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,192,1716274800"; d="scan'208";a="47635843" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.115]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2024 09:27:56 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Mon, 8 Jul 2024 19:27:52 +0300 (EEST) To: =?ISO-8859-15?Q?Marek_Beh=FAn?= cc: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede Subject: Re: [PATCH v3 04/10] irqchip/armada-370-xp: Use BIT() and GENMASK() macros In-Reply-To: <20240708151801.11592-5-kabel@kernel.org> Message-ID: <3ee4c786-6452-95cf-70ec-06359f1c7668@linux.intel.com> References: <20240708151801.11592-1-kabel@kernel.org> <20240708151801.11592-5-kabel@kernel.org> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323328-1541924660-1720456072=:1343" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240708_092800_757138_B514476C X-CRM114-Status: GOOD ( 16.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-1541924660-1720456072=:1343 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE On Mon, 8 Jul 2024, Marek Beh=C3=BAn wrote: > Use the BIT() and GENMASK() macros where appropriate. >=20 > Signed-off-by: Marek Beh=C3=BAn > Reviewed-by: Andrew Lunn Are #includes missing for GENMASK() and BIT()? (Or is this based on some=20 tree which already has them?) --=20 i. > --- > drivers/irqchip/irq-armada-370-xp.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-ar= mada-370-xp.c > index 427ba5fd6adc..18aca9b5d3b3 100644 > --- a/drivers/irqchip/irq-armada-370-xp.c > +++ b/drivers/irqchip/irq-armada-370-xp.c > @@ -121,7 +121,7 @@ > #define ARMADA_370_XP_INT_SET_ENABLE=09=09(0x30) > #define ARMADA_370_XP_INT_CLEAR_ENABLE=09=09(0x34) > #define ARMADA_370_XP_INT_SOURCE_CTL(irq)=09(0x100 + irq*4) > -#define ARMADA_370_XP_INT_SOURCE_CPU_MASK=090xF > +#define ARMADA_370_XP_INT_SOURCE_CPU_MASK=09GENMASK(3, 0) > #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)=09((BIT(0) | BIT(8)) << cp= uid) > =20 > /* Registers relative to per_cpu_int_base */ > @@ -132,18 +132,18 @@ > #define ARMADA_370_XP_INT_SET_MASK=09=09(0x48) > #define ARMADA_370_XP_INT_CLEAR_MASK=09=09(0x4C) > #define ARMADA_370_XP_INT_FABRIC_MASK=09=09(0x54) > -#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)=09(1 << cpu) > +#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)=09BIT(cpu) > =20 > #define ARMADA_370_XP_MAX_PER_CPU_IRQS=09=09(28) > =20 > /* IPI and MSI interrupt definitions for IPI platforms */ > #define IPI_DOORBELL_START=09=09=09(0) > #define IPI_DOORBELL_END=09=09=09(8) > -#define IPI_DOORBELL_MASK=09=09=090xFF > +#define IPI_DOORBELL_MASK=09=09=09GENMASK(7, 0) > #define PCI_MSI_DOORBELL_START=09=09=09(16) > #define PCI_MSI_DOORBELL_NR=09=09=09(16) > #define PCI_MSI_DOORBELL_END=09=09=09(32) > -#define PCI_MSI_DOORBELL_MASK=09=09=090xFFFF0000 > +#define PCI_MSI_DOORBELL_MASK=09=09=09GENMASK(31, 16) > =20 > /* MSI interrupt definitions for non-IPI platforms */ > #define PCI_MSI_FULL_DOORBELL_START=09=090 > @@ -415,7 +415,7 @@ static void armada_370_xp_ipi_send_mask(struct irq_da= ta *d, > =20 > =09/* Convert our logical CPU mask into a physical one. */ > =09for_each_cpu(cpu, mask) > -=09=09map |=3D 1 << cpu_logical_map(cpu); > +=09=09map |=3D BIT(cpu_logical_map(cpu)); > =20 > =09/* > =09 * Ensure that stores to Normal memory are visible to the >=20 --8323328-1541924660-1720456072=:1343--