From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCAE8C2BD09 for ; Fri, 12 Jul 2024 08:32:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=StK0WzdyVIERPUHoNMWReNnM7zz4/NSCx1eLD/3cM7A=; b=O+ptyzKnRKgUowsYb9uNN4ndz9 zOXOVnLnONFaAZvN617M8Qu0tCHETV7iR7j0GkLjQRB6PqIX3kYYAEjxJ06v/MaxXCI90sOm55g1N NEVp7GP4azxufzmc5M35mEXOqJ4/FbIzqpVG487y3hdW5HW8Gkjkz4/tUMpHnKSXC88GEoYZlJOyT ZqeOOf/isuVc4Rz7ojLBEmiGuXTJUhPZfQbBzjAr5vkytJt6+cgt1mRdpF4Zt9Nr9KQqJ6QEjC8O/ ioaOMYQAOqcQb9L/HLA4843CGNKDfZg7BuE97hnkwGnK3G/BSjMhrVHskVDvsruT6AY/PCMBGQDed HgO/8vTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sSBhl-0000000GuOX-211R; Fri, 12 Jul 2024 08:32:37 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sSBhS-0000000GuLY-3mGf for linux-arm-kernel@lists.infradead.org; Fri, 12 Jul 2024 08:32:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA7D81007; Fri, 12 Jul 2024 01:32:42 -0700 (PDT) Received: from [10.162.16.42] (a077893.blr.arm.com [10.162.16.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F021B3F762; Fri, 12 Jul 2024 01:32:14 -0700 (PDT) Message-ID: <3fc8eccd-21a7-40d8-9851-24941c8414da@arm.com> Date: Fri, 12 Jul 2024 14:02:12 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/12] arm64: Add missing APTable and TCR_ELx.HPD masks To: Marc Zyngier , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly References: <20240625133508.259829-1-maz@kernel.org> <20240625133508.259829-2-maz@kernel.org> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20240625133508.259829-2-maz@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240712_013219_019208_DEEB8D12 X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/25/24 19:05, Marc Zyngier wrote: > Although Linux doesn't make use of hierarchical permissions (TFFT!), > KVM needs to know where the various bits related to this feature > live in the TCR_ELx registers as well as in the page tables. > > Add the missing bits. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/include/asm/kvm_arm.h | 1 + > arch/arm64/include/asm/pgtable-hwdef.h | 7 +++++++ > 2 files changed, 8 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index b2adc2c6c82a5..c93ee1036cb09 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -108,6 +108,7 @@ > /* TCR_EL2 Registers bits */ > #define TCR_EL2_DS (1UL << 32) > #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) > +#define TCR_EL2_HPD (1 << 24) > #define TCR_EL2_TBI (1 << 20) > #define TCR_EL2_PS_SHIFT 16 > #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h > index 9943ff0af4c96..f75c9a7e6bd68 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -146,6 +146,7 @@ > #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) > #define PMD_TABLE_PXN (_AT(pmdval_t, 1) << 59) > #define PMD_TABLE_UXN (_AT(pmdval_t, 1) << 60) > +#define PMD_TABLE_AP (_AT(pmdval_t, 3) << 61) APTable bits are also present in all table descriptors at each non-L3 level. Should not corresponding corresponding macros i.e PUD_TABLE_AP, P4D_TABLE_AP, and PGD_TABLE_AP be added as well ? > > /* > * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). > @@ -307,6 +308,12 @@ > #define TCR_TCMA1 (UL(1) << 58) > #define TCR_DS (UL(1) << 59) > > +#define TCR_HPD0_SHIFT 41 > +#define TCR_HPD0 BIT(TCR_HPD0_SHIFT) > + > +#define TCR_HPD1_SHIFT 42 > +#define TCR_HPD1 BIT(TCR_HPD1_SHIFT) Should not these new register fields follow the current ascending bit order in the listing i.e get added after TCR_HD (bit 40). > + > /* > * TTBR. > */