From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA930CD11C2 for ; Wed, 10 Apr 2024 07:55:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NG9vlVCdYpgF8f9KU1LCidE92+a/Nol8ftxVF9LrW6k=; b=RV4pbaekdMoPdm IZQKXduVEs61nGTSQpa4uSyaFdCDg9er1KEw8zKY8Fnj6H0VlPhYT008RirdOhbdcfM8osLvJBxht gIRZVuW5eOSNoLwNh6pv0shTw7Oc09Zqd5sZZDNKUXkCbYEDx2O+HdTHtZttwcKdWKxWrR55pSNk6 vu0YJvcOk+eJsE9k0+SVXcpsOVSnnfllfKIfGcQH24uZx2bLX1WHbZgtgG6zTcCWSC4TY9K0jQy19 xFWFnhrPNWfS0bgwXDwS+sodvQgf0+iVj90lXeLQvKQcNvdmxJCWgO1Sov89A10gys3iI0z1fiLDm S5wCqosV01ikQ2kDVY2g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruSnu-00000005j6s-3veX; Wed, 10 Apr 2024 07:55:34 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruSnr-00000005j4M-16SX for linux-arm-kernel@lists.infradead.org; Wed, 10 Apr 2024 07:55:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6BB0139F; Wed, 10 Apr 2024 00:55:55 -0700 (PDT) Received: from [10.162.43.6] (a077893.blr.arm.com [10.162.43.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 619903F64C; Wed, 10 Apr 2024 00:55:20 -0700 (PDT) Message-ID: <410c7fe2-5790-49d6-9732-d2f3c5e351e6@arm.com> Date: Wed, 10 Apr 2024 13:25:17 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] arm64: tlb: Fix TLBI RANGE operand Content-Language: en-US To: Gavin Shan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: catalin.marinas@arm.com, will@kernel.org, akpm@linux-foundation.org, maz@kernel.org, oliver.upton@linux.dev, ryan.roberts@arm.com, apopple@nvidia.com, rananta@google.com, mark.rutland@arm.com, v-songbaohua@oppo.com, yangyicong@hisilicon.com, shahuang@redhat.com, yihyu@redhat.com, shan.gavin@gmail.com References: <20240405035852.1532010-1-gshan@redhat.com> <20240405035852.1532010-2-gshan@redhat.com> From: Anshuman Khandual In-Reply-To: <20240405035852.1532010-2-gshan@redhat.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240410_005531_424804_CC9EFEA6 X-CRM114-Status: GOOD ( 25.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 4/5/24 09:28, Gavin Shan wrote: > KVM/arm64 relies on TLBI RANGE feature to flush TLBs when the dirty > pages are collected by VMM and the page table entries become write > protected during live migration. Unfortunately, the operand passed > to the TLBI RANGE instruction isn't correctly sorted out due to the > commit 117940aa6e5f ("KVM: arm64: Define kvm_tlb_flush_vmid_range()"). > It leads to crash on the destination VM after live migration because > TLBs aren't flushed completely and some of the dirty pages are missed. > > For example, I have a VM where 8GB memory is assigned, starting from > 0x40000000 (1GB). Note that the host has 4KB as the base page size. > In the middile of migration, kvm_tlb_flush_vmid_range() is executed > to flush TLBs. It passes MAX_TLBI_RANGE_PAGES as the argument to > __kvm_tlb_flush_vmid_range() and __flush_s2_tlb_range_op(). SCALE#3 > and NUM#31, corresponding to MAX_TLBI_RANGE_PAGES, isn't supported > by __TLBI_RANGE_NUM(). In this specific case, -1 has been returned > from __TLBI_RANGE_NUM() for SCALE#3/2/1/0 and rejected by the loop > in the __flush_tlb_range_op() until the variable @scale underflows > and becomes -9, 0xffff708000040000 is set as the operand. The operand > is wrong since it's sorted out by __TLBI_VADDR_RANGE() according to > invalid @scale and @num. > > Fix it by extending __TLBI_RANGE_NUM() to support the combination of > SCALE#3 and NUM#31. With the changes, [-1 31] instead of [-1 30] can > be returned from the macro, meaning the TLBs for 0x200000 pages in the > above example can be flushed in one shoot with SCALE#3 and NUM#31. The > macro TLBI_RANGE_MASK is dropped since no one uses it any more. The > comments are also adjusted accordingly. > > Fixes: 117940aa6e5f ("KVM: arm64: Define kvm_tlb_flush_vmid_range()") > Cc: stable@kernel.org # v6.6+ > Reported-by: Yihuang Yu > Suggested-by: Marc Zyngier > Signed-off-by: Gavin Shan Reviewed-by: Anshuman Khandual > --- > arch/arm64/include/asm/tlbflush.h | 20 +++++++++++--------- > 1 file changed, 11 insertions(+), 9 deletions(-) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index 3b0e8248e1a4..a75de2665d84 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -161,12 +161,18 @@ static inline unsigned long get_trans_granule(void) > #define MAX_TLBI_RANGE_PAGES __TLBI_RANGE_PAGES(31, 3) > > /* > - * Generate 'num' values from -1 to 30 with -1 rejected by the > - * __flush_tlb_range() loop below. > + * Generate 'num' values from -1 to 31 with -1 rejected by the > + * __flush_tlb_range() loop below. Its return value is only > + * significant for a maximum of MAX_TLBI_RANGE_PAGES pages. If > + * 'pages' is more than that, you must iterate over the overall > + * range. > */ > -#define TLBI_RANGE_MASK GENMASK_ULL(4, 0) > -#define __TLBI_RANGE_NUM(pages, scale) \ > - ((((pages) >> (5 * (scale) + 1)) & TLBI_RANGE_MASK) - 1) > +#define __TLBI_RANGE_NUM(pages, scale) \ > + ({ \ > + int __pages = min((pages), \ > + __TLBI_RANGE_PAGES(31, (scale))); \ > + (__pages >> (5 * (scale) + 1)) - 1; \ > + }) > > /* > * TLB Invalidation > @@ -379,10 +385,6 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) > * 3. If there is 1 page remaining, flush it through non-range operations. Range > * operations can only span an even number of pages. We save this for last to > * ensure 64KB start alignment is maintained for the LPA2 case. > - * > - * Note that certain ranges can be represented by either num = 31 and > - * scale or num = 0 and scale + 1. The loop below favours the latter > - * since num is limited to 30 by the __TLBI_RANGE_NUM() macro. > */ > #define __flush_tlb_range_op(op, start, pages, stride, \ > asid, tlb_level, tlbi_user, lpa2) \ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel