From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3E1ACDB47E for ; Mon, 16 Oct 2023 03:00:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=W/7LM+VVVcqX2Sl/heZxC5JmWdSjq198QWW3yB4T1FA=; b=aT1iWrbettR3XJ 0GAJC9bhyobQRk8APwySd22v44OlHmWNjAq7ZOoumKYur+LiOUksmEh7/5HwVhxqc3XDaE+6CUH1D x4uf1NDui8gHiUpKlbUUc9E2VUhbfMHJJ7NO3FsP9mfyqQMTQKIToo5vbs1+a6pF/7gW+cn1hyiBo rZw61ELD2usvZCfOzj4BfrzZO7R+lwLnxmke/j7I6Vy2W3M3NzC3rPKrskd6Q0WgnnZ+nyAzVLWMU zlFEU3ns28oaJ7ZgFN7+cdxPEK6dRNJzuVa8e7b9Ry8k9Wf1S/yUDaVH2wwKi5+Lf2tC6J5uiLMWm 2JQuIz1HhfL9dmGodZlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qsDqK-0087Xt-32; Mon, 16 Oct 2023 03:00:32 +0000 Received: from out30-118.freemail.mail.aliyun.com ([115.124.30.118]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qsDqG-0087WR-0k for linux-arm-kernel@lists.infradead.org; Mon, 16 Oct 2023 03:00:30 +0000 X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R611e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045176;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=15;SR=0;TI=SMTPD_---0Vu9JM3x_1697425214; Received: from 30.240.113.74(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0Vu9JM3x_1697425214) by smtp.aliyun-inc.com; Mon, 16 Oct 2023 11:00:15 +0800 Message-ID: <4147832a-1f24-5993-dfb6-59f420a17481@linux.alibaba.com> Date: Mon, 16 Oct 2023 11:00:13 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v7 3/4] drivers/perf: add DesignWare PCIe PMU driver Content-Language: en-US To: Bjorn Helgaas Cc: chengyou@linux.alibaba.com, kaishen@linux.alibaba.com, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, renyu.zj@linux.alibaba.com References: <20231013163025.GA1116248@bhelgaas> From: Shuai Xue In-Reply-To: <20231013163025.GA1116248@bhelgaas> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231015_200028_520237_7B57A27D X-CRM114-Status: GOOD ( 32.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2023/10/14 00:30, Bjorn Helgaas wrote: > On Fri, Oct 13, 2023 at 11:46:44AM +0800, Shuai Xue wrote: >> >> >> On 2023/10/13 00:25, Bjorn Helgaas wrote: >>> On Thu, Oct 12, 2023 at 11:28:55AM +0800, Shuai Xue wrote: >>>> This commit adds the PCIe Performance Monitoring Unit (PMU) driver support >>>> for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express >>>> Core controller IP which provides statistics feature. The PMU is not a PCIe >>>> Root Complex integrated End Point(RCiEP) device but only register counters >>>> provided by each PCIe Root Port. > > IIUC, the PMU is directly integrated into the Root Port: it's > discovered and operated via the Root Port config space. If so, I > wouldn't bother mentioning RCiEP because there's no need to list all > the things it's *not*. I see, will not mention RCiEP next version. > >>>> To facilitate collection of statistics the controller provides the >>>> following two features for each Root Port: >>>> >>>> - Time Based Analysis (RX/TX data throughput and time spent in each >>>> low-power LTSSM state) >>>> - Event counters (Error and Non-Error for lanes) >>>> >>>> Note, only one counter for each type and does not overflow interrupt. >>> >>> Not sure what "does not overflow interrupt" means. Does it mean >>> there's no interrupt generated when the counter overflows? >> >> Yes, exactly. The rootport does NOT generate interrupt when the >> couter overflows. I think the assumption hidden in this design is >> 64-bit counter will not overflow within observable time. >> >> PCIe 5.0 slots can now reach anywhere between ~4GB/sec for a x1 slot >> up to ~64GB/sec for a x16 slot. The unit of counter is 16 byte. >> >> 2^64/(64/16*10^9)/60/60/24/365=146 years >> >> so, the counter will not overflow within 146 years. > > Certainly a reasonable assumption :) > > But I'm confused about how many counters there are. Clearly there are > two features ((1) time-based analysis and (2) event counters). > > "One counter for each type" suggests there's one counter for > time-based analysis and a second counter for event counting, You are right, two counters, TIME_BASED_ANAL_DATA_REG for time-based analysis and EVENT_COUNTER_DATA_REG for event counting. And both of them do not support generate interrupt when the counter overflows. > but from > dwc_pcie_pmu_event_add(), it looks like each Root Port might have a > single counter, and you can decide whether that counter is used for > time-based analysis or event counting, but you can't do both at the > same time? dwc_pcie_pmu_event_add() now limit the PMU usage to stat event for either time-based analysis or event counting. I will extend to support stat them at the same time. @@ -447,10 +447,10 @@ static int dwc_pcie_pmu_event_add(struct perf_event *event, int flags) u32 ctrl; /* Only one counter and it is in use */ - if (pcie_pmu->event) + if (pcie_pmu->event[type]) return -ENOSPC; - pcie_pmu->event = event; + pcie_pmu->event[type] = event; hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; if (type == DWC_PCIE_LANE_EVENT) { @@ -486,10 +486,11 @@ static int dwc_pcie_pmu_event_add(struct perf_event *event, int flags) static void dwc_pcie_pmu_event_del(struct perf_event *event, int flags) { struct dwc_pcie_pmu *pcie_pmu = to_dwc_pcie_pmu(event->pmu); + enum dwc_pcie_event_type type = DWC_PCIE_EVENT_TYPE(event); dwc_pcie_pmu_event_stop(event, flags | PERF_EF_UPDATE); perf_event_update_userpage(event); - pcie_pmu->event = NULL; + pcie_pmu->event[type] = NULL; } > And the event counting is for a single lane, not for the > link as a whole? Yes. > > If so, I might word this as: > > Each Root Port contains one counter that can be used for either: > > - Time-Based Analysis (RX/TX data throughput and time spent in > each low-power LTSSM state) or > > - Event counting (error and non-error events for a specified lane) > > There is no interrupt for counter overflow. Based on above, I change the word to: To facilitate collection of statistics the controller provides the following two features for each Root Port: - one 64-bit counter for Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) and - one 32-bit counter for Event counting (error and non-error events for a specified lane) Note: There is no interrupt for counter overflow. > >>>> + Enable perf support for Synopsys DesignWare PCIe PMU Performance >>>> + monitoring event on platform including the Yitian 710. >>> >>> Should this mention Alibaba or T-Head? I don't know how >>> Alibaba/T-Head/Yitian are all related. >> >> The server chips, named Yitian 710, are custom-built by Alibaba Group's chip >> development business, T-Head. >> >> Enable perf support for Synopsys DesignWare PCIe PMU Performance >> monitoring event on platform including the Alibaba Yitian 710. >> >> Is this okay? > > Perfect :) Thank you for valuable comments. Best Regards, Shuai _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel