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Fri, 08 May 2020 18:12:26 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id A759AC433BA; Fri, 8 May 2020 18:12:25 +0000 (UTC) Received: from [192.168.8.176] (cpe-70-95-149-85.san.res.rr.com [70.95.149.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: asutoshd) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0B44CC433D2; Fri, 8 May 2020 18:12:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0B44CC433D2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=asutoshd@codeaurora.org Subject: Re: [PATCH v1 3/5] scsi: ufs: customize flush threshold for WriteBooster To: Stanley Chu , linux-scsi@vger.kernel.org, martin.petersen@oracle.com, avri.altman@wdc.com, alim.akhtar@samsung.com, jejb@linux.ibm.com References: <20200508171513.14665-1-stanley.chu@mediatek.com> <20200508171513.14665-4-stanley.chu@mediatek.com> From: "Asutosh Das (asd)" Message-ID: <4196ff98-093e-3708-d166-a7a7c6046c57@codeaurora.org> Date: Fri, 8 May 2020 11:12:23 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200508171513.14665-4-stanley.chu@mediatek.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200508_111234_789703_78F4784E X-CRM114-Status: GOOD ( 21.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bvanassche@acm.org, andy.teng@mediatek.com, chun-hung.wu@mediatek.com, kuohong.wang@mediatek.com, linux-kernel@vger.kernel.org, cang@codeaurora.org, linux-mediatek@lists.infradead.org, peter.wang@mediatek.com, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org, beanhuo@micron.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 5/8/2020 10:15 AM, Stanley Chu wrote: > Allow flush threshold for WriteBooster to be customizable by > vendors. To achieve this, make the value as a variable in struct > ufs_hba first. > > Signed-off-by: Stanley Chu > --- > drivers/scsi/ufs/ufshcd.c | 6 ++++-- > drivers/scsi/ufs/ufshcd.h | 1 + > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c > index cdacbe6378a1..9a0ce6550c2f 100644 > --- a/drivers/scsi/ufs/ufshcd.c > +++ b/drivers/scsi/ufs/ufshcd.c > @@ -5301,8 +5301,8 @@ static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, > cur_buf); > return false; > } > - /* Let it continue to flush when >60% full */ > - if (avail_buf < UFS_WB_40_PERCENT_BUF_REMAIN) > + /* Let it continue to flush when available buffer exceeds threshold */ > + if (avail_buf < hba->vps->wb_flush_threshold) > return true; > > return false; > @@ -6839,6 +6839,7 @@ static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf) > if (!d_lu_wb_buf_alloc) > goto wb_disabled; > } > + Is this newline needed? > return; > > wb_disabled: > @@ -7462,6 +7463,7 @@ static const struct attribute_group *ufshcd_driver_groups[] = { > > static struct ufs_hba_variant_params ufs_hba_vps = { > .hba_enable_delay_us = 1000, > + .wb_flush_threshold = UFS_WB_40_PERCENT_BUF_REMAIN, > .devfreq_profile.polling_ms = 100, > .devfreq_profile.target = ufshcd_devfreq_target, > .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, > diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h > index f7bdf52ba8b0..e3dfb48e669e 100644 > --- a/drivers/scsi/ufs/ufshcd.h > +++ b/drivers/scsi/ufs/ufshcd.h > @@ -570,6 +570,7 @@ struct ufs_hba_variant_params { > struct devfreq_dev_profile devfreq_profile; > struct devfreq_simple_ondemand_data ondemand_data; > u16 hba_enable_delay_us; > + u32 wb_flush_threshold; > }; > > /** > Patch[3] & [4] may be combined into a single patch perhaps? Patch[4] just redoes what [3] did in a different way, so might as well just do what patch[4] does right away. -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, Linux Foundation Collaborative Project _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel