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Thu, 03 Sep 2020 00:51:35 -0400 X-MC-Unique: W42ZzB2YMkyImn0yMjakcQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 53866425D6; Thu, 3 Sep 2020 04:51:34 +0000 (UTC) Received: from [10.64.54.159] (vpn2-54-159.bne.redhat.com [10.64.54.159]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2829D100EBB8; Thu, 3 Sep 2020 04:51:31 +0000 (UTC) Subject: Re: [PATCH v3 14/21] KVM: arm64: Add support for stage-2 cache flushing in generic page-table To: Will Deacon , kvmarm@lists.cs.columbia.edu References: <20200825093953.26493-1-will@kernel.org> <20200825093953.26493-15-will@kernel.org> From: Gavin Shan Message-ID: <4198f2f9-abaa-2755-0113-38384150b595@redhat.com> Date: Thu, 3 Sep 2020 14:51:30 +1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20200825093953.26493-15-will@kernel.org> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=gshan@redhat.com X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: redhat.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200903_005140_448382_6CA165BB X-CRM114-Status: GOOD ( 21.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Gavin Shan Cc: Suzuki Poulose , Marc Zyngier , Quentin Perret , James Morse , Catalin Marinas , kernel-team@android.com, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On 8/25/20 7:39 PM, Will Deacon wrote: > From: Quentin Perret > > Add support for cache flushing a range of the stage-2 address space to > the generic page-table code. > > Cc: Marc Zyngier > Signed-off-by: Quentin Perret > Signed-off-by: Will Deacon > --- Reviewed-by: Gavin Shan > arch/arm64/include/asm/kvm_pgtable.h | 12 ++++++++++++ > arch/arm64/kvm/hyp/pgtable.c | 26 ++++++++++++++++++++++++++ > 2 files changed, 38 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > index 0c96b78d791d..ea823fe31913 100644 > --- a/arch/arm64/include/asm/kvm_pgtable.h > +++ b/arch/arm64/include/asm/kvm_pgtable.h > @@ -226,6 +226,18 @@ kvm_pte_t kvm_pgtable_stage2_mkold(struct kvm_pgtable *pgt, u64 addr); > */ > bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr); > > +/** > + * kvm_pgtable_stage2_flush_range() - Clean and invalidate data cache to Point > + * of Coherency for guest stage-2 address > + * range. > + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init(). > + * @addr: Intermediate physical address from which to flush. > + * @size: Size of the range. > + * > + * Return: 0 on success, negative error code on failure. > + */ > +int kvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size); > + > /** > * kvm_pgtable_walk() - Walk a page-table. > * @pgt: Page-table structure initialised by kvm_pgtable_*_init(). > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index c218651f8eba..75887185f1e2 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -762,6 +762,32 @@ bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr) > return pte & KVM_PTE_LEAF_ATTR_LO_S2_AF; > } > > +static int stage2_flush_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep, > + enum kvm_pgtable_walk_flags flag, > + void * const arg) > +{ > + kvm_pte_t pte = *ptep; > + > + if (!kvm_pte_valid(pte) || !stage2_pte_cacheable(pte)) > + return 0; > + > + stage2_flush_dcache(kvm_pte_follow(pte), kvm_granule_size(level)); > + return 0; > +} > + > +int kvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size) > +{ > + struct kvm_pgtable_walker walker = { > + .cb = stage2_flush_walker, > + .flags = KVM_PGTABLE_WALK_LEAF, > + }; > + > + if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > + return 0; > + > + return kvm_pgtable_walk(pgt, addr, size, &walker); > +} > + > int kvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm *kvm) > { > size_t pgd_sz; > Thanks, Gavin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel