From: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
To: rob.clark@oss.qualcomm.com
Cc: Akhil P Oommen <akhilpo@oss.qualcomm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jessica.zhang@oss.qualcomm.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
Date: Sun, 8 Jun 2025 18:22:54 +0300 [thread overview]
Message-ID: <42a69fa4-48ac-4a2f-a2ff-b4e1fe3a228a@oss.qualcomm.com> (raw)
In-Reply-To: <CACSVV03mNkELWDB_uxdjEa5GeWZUY=42O8QG4qTrg6zquT1Bgw@mail.gmail.com>
On 08/06/2025 18:20, Rob Clark wrote:
> On Sun, Jun 8, 2025 at 8:09 AM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>
>> On Sun, Jun 08, 2025 at 07:10:11AM -0700, Rob Clark wrote:
>>> On Sat, Jun 7, 2025 at 1:17 PM Dmitry Baryshkov
>>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>>>
>>>> On Sat, Jun 07, 2025 at 07:45:01PM +0530, Akhil P Oommen wrote:
>>>>> X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
>>>>> version of Adreno X1-85 GPU. Describe this new GPU and also add
>>>>> the secure gpu firmware path that should used for X1P42100 CRD.
>>>>>
>>>>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
>>>>> arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
>>>>> arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
>>>>> 3 files changed, 131 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>> index a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>> @@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
>>>>> interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>>>>> };
>>>>>
>>>>> + qfprom: efuse@221c8000 {
>>>>> + compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
>>>>> + reg = <0 0x221c8000 0 0x1000>;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <1>;
>>>>> + };
>>>>> +
>>>>> pmu@24091000 {
>>>>> compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
>>>>> reg = <0 0x24091000 0 0x1000>;
>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
>>>>> index cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
>>>>> +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
>>>>> @@ -15,3 +15,7 @@ / {
>>>>> model = "Qualcomm Technologies, Inc. X1P42100 CRD";
>>>>> compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
>>>>> };
>>>>> +
>>>>> +&gpu_zap_shader {
>>>>> + firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
>>>>> +};
>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
>>>>> index 27f479010bc330eb6445269a1c46bf78ec6f1bd4..5ed461ed5cca271d43647888aa6eacac3de2ac9d 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
>>>>> @@ -17,15 +17,134 @@
>>>>> /delete-node/ &cpu_pd9;
>>>>> /delete-node/ &cpu_pd10;
>>>>> /delete-node/ &cpu_pd11;
>>>>> +/delete-node/ &gpu_opp_table;
>>>>> /delete-node/ &pcie3_phy;
>>>>>
>>>>> &gcc {
>>>>> compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
>>>>> };
>>>>>
>>>>> -/* The GPU is physically different and will be brought up later */
>>>>> +&gmu {
>>>>> + /delete-property/ compatible;
>>>>> + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
>>>>> +};
>>>>> +
>>>>> +&qfprom {
>>>>> + gpu_speed_bin: gpu_speed_bin@119 {
>>>>> + reg = <0x119 0x2>;
>>>>> + bits = <7 9>;
>>>>> + };
>>>>> +};
>>>>> +
>>>>> &gpu {
>>>>> /delete-property/ compatible;
>>>>
>>>> I think, you can drop this line.
>>>>
>>>>> +
>>>>> + compatible = "qcom,adreno-43030c00", "qcom,adreno";
>>>>> +
>>>>> + nvmem-cells = <&gpu_speed_bin>;
>>>>> + nvmem-cell-names = "speed_bin";
>>>>> +
>>>>> + gpu_opp_table: opp-table {
>>>>> + compatible = "operating-points-v2-adreno", "operating-points-v2";
>>>>> +
>>>>> + opp-1400000000 {
>>>>> + opp-hz = /bits/ 64 <1400000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
>>>>> + opp-peak-kBps = <16500000>;
>>>>> + qcom,opp-acd-level = <0xa8295ffd>;
>>>>> + opp-supported-hw = <0x3>;
>>>>> + };
>>>>> +
>>>>> + opp-1250000000 {
>>>>> + opp-hz = /bits/ 64 <1250000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
>>>>> + opp-peak-kBps = <16500000>;
>>>>> + qcom,opp-acd-level = <0x882a5ffd>;
>>>>> + opp-supported-hw = <0x7>;
>>>>> + };
>>>>> +
>>>>> + opp-1107000000 {
>>>>> + opp-hz = /bits/ 64 <1107000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
>>>>> + opp-peak-kBps = <16500000>;
>>>>> + qcom,opp-acd-level = <0x882a5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-1014000000 {
>>>>> + opp-hz = /bits/ 64 <1014000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>>>>> + opp-peak-kBps = <14398438>;
>>>>> + qcom,opp-acd-level = <0xa82a5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-940000000 {
>>>>> + opp-hz = /bits/ 64 <940000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>>>>> + opp-peak-kBps = <14398438>;
>>>>> + qcom,opp-acd-level = <0xa82a5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-825000000 {
>>>>> + opp-hz = /bits/ 64 <825000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>>>>> + opp-peak-kBps = <12449219>;
>>>>> + qcom,opp-acd-level = <0x882b5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-720000000 {
>>>>> + opp-hz = /bits/ 64 <720000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
>>>>> + opp-peak-kBps = <10687500>;
>>>>> + qcom,opp-acd-level = <0xa82c5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-666000000-0 {
>>>>> + opp-hz = /bits/ 64 <666000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>>>> + opp-peak-kBps = <8171875>;
>>>>> + qcom,opp-acd-level = <0xa82d5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + /* Only applicable for SKUs which has 666Mhz as Fmax */
>>>>> + opp-666000000-1 {
>>>>> + opp-hz = /bits/ 64 <666000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>>>> + opp-peak-kBps = <16500000>;
>>>>
>>>> This looks odd, why is it so high?
>>>
>>> You want max bandwidth on max opp
>>
>> Yes, but can it actually sustain / provide this BW?
>>
>
> I'd have to trust Akhil on that one, but I have no reason to believe
> otherwise. Just pointing out we've done analogous things elsewhere
> (for ex, cpu bw for sc7180-lite.dtsi)
Ack. Then I'll wait for v2 with no deleting of compatible lines (a new
line here would just replace the existing one).
--
With best wishes
Dmitry
next prev parent reply other threads:[~2025-06-08 15:27 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-07 14:14 [PATCH 0/3] Support for Adreno X1-45 GPU Akhil P Oommen
2025-06-07 14:14 ` [PATCH 1/3] arm64: defconfig: Enable X1P42100_GPUCC driver Akhil P Oommen
2025-06-07 20:11 ` Dmitry Baryshkov
2025-06-07 14:15 ` [PATCH 2/3] drm/msm/adreno: Add Adreno X1-45 support Akhil P Oommen
2025-06-07 20:14 ` Dmitry Baryshkov
2025-06-08 20:10 ` Akhil P Oommen
2025-06-10 14:36 ` Konrad Dybcio
2025-06-07 14:15 ` [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC Akhil P Oommen
2025-06-07 20:17 ` Dmitry Baryshkov
2025-06-08 14:10 ` Rob Clark
2025-06-08 15:09 ` Dmitry Baryshkov
2025-06-08 15:20 ` Rob Clark
2025-06-08 15:22 ` Dmitry Baryshkov [this message]
2025-06-08 20:18 ` Akhil P Oommen
2025-06-08 22:19 ` Dmitry Baryshkov
2025-06-10 14:39 ` Konrad Dybcio
2025-06-08 15:21 ` [PATCH 0/3] Support for Adreno X1-45 GPU Rob Clark
2025-06-16 5:07 ` Akhil P Oommen
2025-06-09 15:01 ` Rob Herring (Arm)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=42a69fa4-48ac-4a2f-a2ff-b4e1fe3a228a@oss.qualcomm.com \
--to=dmitry.baryshkov@oss.qualcomm.com \
--cc=abhinav.kumar@linux.dev \
--cc=airlied@gmail.com \
--cc=akhilpo@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=freedreno@lists.freedesktop.org \
--cc=jessica.zhang@oss.qualcomm.com \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marijn.suijten@somainline.org \
--cc=rob.clark@oss.qualcomm.com \
--cc=robh@kernel.org \
--cc=sean@poorly.run \
--cc=simona@ffwll.ch \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox