* [PATCH 1/3] arm64: defconfig: Enable X1P42100_GPUCC driver
2025-06-07 14:14 [PATCH 0/3] Support for Adreno X1-45 GPU Akhil P Oommen
@ 2025-06-07 14:14 ` Akhil P Oommen
2025-06-07 20:11 ` Dmitry Baryshkov
2025-06-07 14:15 ` [PATCH 2/3] drm/msm/adreno: Add Adreno X1-45 support Akhil P Oommen
` (3 subsequent siblings)
4 siblings, 1 reply; 19+ messages in thread
From: Akhil P Oommen @ 2025-06-07 14:14 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, dri-devel,
freedreno, devicetree, Akhil P Oommen
In order to enable GPU support in Snapdragon X1P42100
(8 CPU core version), enable X1P42100 GPUCC driver as a module.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 62d3c87858e1817bac291780dff3823dacd72510..9cc473fd0d3308f7869d00425e17b114c87093b2 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1350,6 +1350,7 @@ CONFIG_CLK_X1E80100_CAMCC=m
CONFIG_CLK_X1E80100_DISPCC=m
CONFIG_CLK_X1E80100_GCC=y
CONFIG_CLK_X1E80100_GPUCC=m
+CONFIG_CLK_X1P42100_GPUCC=m
CONFIG_CLK_X1E80100_TCSRCC=y
CONFIG_CLK_QCM2290_GPUCC=m
CONFIG_QCOM_A53PLL=y
--
2.48.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 1/3] arm64: defconfig: Enable X1P42100_GPUCC driver
2025-06-07 14:14 ` [PATCH 1/3] arm64: defconfig: Enable X1P42100_GPUCC driver Akhil P Oommen
@ 2025-06-07 20:11 ` Dmitry Baryshkov
0 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2025-06-07 20:11 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Catalin Marinas, Will Deacon, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-kernel, linux-kernel, linux-arm-msm,
dri-devel, freedreno, devicetree
On Sat, Jun 07, 2025 at 07:44:59PM +0530, Akhil P Oommen wrote:
> In order to enable GPU support in Snapdragon X1P42100
> (8 CPU core version), enable X1P42100 GPUCC driver as a module.
... it is used on Asus Zenbook A14 and other similar laptops.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 62d3c87858e1817bac291780dff3823dacd72510..9cc473fd0d3308f7869d00425e17b114c87093b2 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1350,6 +1350,7 @@ CONFIG_CLK_X1E80100_CAMCC=m
> CONFIG_CLK_X1E80100_DISPCC=m
> CONFIG_CLK_X1E80100_GCC=y
> CONFIG_CLK_X1E80100_GPUCC=m
> +CONFIG_CLK_X1P42100_GPUCC=m
> CONFIG_CLK_X1E80100_TCSRCC=y
> CONFIG_CLK_QCM2290_GPUCC=m
> CONFIG_QCOM_A53PLL=y
>
> --
> 2.48.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 2/3] drm/msm/adreno: Add Adreno X1-45 support
2025-06-07 14:14 [PATCH 0/3] Support for Adreno X1-45 GPU Akhil P Oommen
2025-06-07 14:14 ` [PATCH 1/3] arm64: defconfig: Enable X1P42100_GPUCC driver Akhil P Oommen
@ 2025-06-07 14:15 ` Akhil P Oommen
2025-06-07 20:14 ` Dmitry Baryshkov
2025-06-10 14:36 ` Konrad Dybcio
2025-06-07 14:15 ` [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC Akhil P Oommen
` (2 subsequent siblings)
4 siblings, 2 replies; 19+ messages in thread
From: Akhil P Oommen @ 2025-06-07 14:15 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, dri-devel,
freedreno, devicetree, Akhil P Oommen
Add support for Adreno X1-45 GPU present Snapdragon X1P42100
series of compute chipsets. This GPU is a smaller version of
X1-85 GPU with lower core count and smaller internal memories.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 38 +++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 70f7ad806c34076352d84f32d62c2833422b6e5e..2db748ce7df57a9151ed1e7f1b025a537bb5f653 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1474,6 +1474,44 @@ static const struct adreno_info a7xx_gpus[] = {
},
},
.preempt_record_size = 3572 * SZ_1K,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x43030c00),
+ .family = ADRENO_7XX_GEN2,
+ .fw = {
+ [ADRENO_FW_SQE] = "gen71500_sqe.fw",
+ [ADRENO_FW_GMU] = "gen71500_gmu.bin",
+ },
+ .gmem = SZ_1M + SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV |
+ ADRENO_QUIRK_PREEMPTION,
+ .init = a6xx_gpu_init,
+ .a6xx = &(const struct a6xx_info) {
+ .hwcg = a740_hwcg,
+ .protect = &a730_protect,
+ .pwrup_reglist = &a7xx_pwrup_reglist,
+ .gmu_chipid = 0x70f0000,
+ .gmu_cgc_mode = 0x00020222,
+ .bcms = (const struct a6xx_bcm[]) {
+ { .name = "SH0", .buswidth = 16 },
+ { .name = "MC0", .buswidth = 4 },
+ {
+ .name = "ACV",
+ .fixed = true,
+ .perfmode = BIT(3),
+ .perfmode_bw = 16500000,
+ },
+ { /* sentinel */ },
+ },
+ },
+ .preempt_record_size = 4192 * SZ_1K,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 294, 1 },
+ { 263, 2 },
+ { 141, 3 },
+ ),
}
};
DECLARE_ADRENO_GPULIST(a7xx);
--
2.48.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 2/3] drm/msm/adreno: Add Adreno X1-45 support
2025-06-07 14:15 ` [PATCH 2/3] drm/msm/adreno: Add Adreno X1-45 support Akhil P Oommen
@ 2025-06-07 20:14 ` Dmitry Baryshkov
2025-06-08 20:10 ` Akhil P Oommen
2025-06-10 14:36 ` Konrad Dybcio
1 sibling, 1 reply; 19+ messages in thread
From: Dmitry Baryshkov @ 2025-06-07 20:14 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Catalin Marinas, Will Deacon, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-kernel, linux-kernel, linux-arm-msm,
dri-devel, freedreno, devicetree
On Sat, Jun 07, 2025 at 07:45:00PM +0530, Akhil P Oommen wrote:
> Add support for Adreno X1-45 GPU present Snapdragon X1P42100
> series of compute chipsets. This GPU is a smaller version of
> X1-85 GPU with lower core count and smaller internal memories.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 38 +++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 70f7ad806c34076352d84f32d62c2833422b6e5e..2db748ce7df57a9151ed1e7f1b025a537bb5f653 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1474,6 +1474,44 @@ static const struct adreno_info a7xx_gpus[] = {
> },
> },
> .preempt_record_size = 3572 * SZ_1K,
> + }, {
> + .chip_ids = ADRENO_CHIP_IDS(0x43030c00),
> + .family = ADRENO_7XX_GEN2,
> + .fw = {
> + [ADRENO_FW_SQE] = "gen71500_sqe.fw",
> + [ADRENO_FW_GMU] = "gen71500_gmu.bin",
Any chance of getting these and ZAP into linux-firmware?
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 2/3] drm/msm/adreno: Add Adreno X1-45 support
2025-06-07 20:14 ` Dmitry Baryshkov
@ 2025-06-08 20:10 ` Akhil P Oommen
0 siblings, 0 replies; 19+ messages in thread
From: Akhil P Oommen @ 2025-06-08 20:10 UTC (permalink / raw)
To: Dmitry Baryshkov, Akhil P Oommen
Cc: Catalin Marinas, Will Deacon, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-kernel, linux-kernel, linux-arm-msm,
dri-devel, freedreno, devicetree
On 6/8/2025 1:44 AM, Dmitry Baryshkov wrote:
> On Sat, Jun 07, 2025 at 07:45:00PM +0530, Akhil P Oommen wrote:
>> Add support for Adreno X1-45 GPU present Snapdragon X1P42100
>> series of compute chipsets. This GPU is a smaller version of
>> X1-85 GPU with lower core count and smaller internal memories.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 38 +++++++++++++++++++++++++++++++
>> 1 file changed, 38 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 70f7ad806c34076352d84f32d62c2833422b6e5e..2db748ce7df57a9151ed1e7f1b025a537bb5f653 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1474,6 +1474,44 @@ static const struct adreno_info a7xx_gpus[] = {
>> },
>> },
>> .preempt_record_size = 3572 * SZ_1K,
>> + }, {
>> + .chip_ids = ADRENO_CHIP_IDS(0x43030c00),
>> + .family = ADRENO_7XX_GEN2,
>> + .fw = {
>> + [ADRENO_FW_SQE] = "gen71500_sqe.fw",
>> + [ADRENO_FW_GMU] = "gen71500_gmu.bin",
>
> Any chance of getting these and ZAP into linux-firmware?
Yeah. Haven't got the legal clearance to publish the firmwares yet. Will
post it in a few days.
-Akhil.
>
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/3] drm/msm/adreno: Add Adreno X1-45 support
2025-06-07 14:15 ` [PATCH 2/3] drm/msm/adreno: Add Adreno X1-45 support Akhil P Oommen
2025-06-07 20:14 ` Dmitry Baryshkov
@ 2025-06-10 14:36 ` Konrad Dybcio
1 sibling, 0 replies; 19+ messages in thread
From: Konrad Dybcio @ 2025-06-10 14:36 UTC (permalink / raw)
To: Akhil P Oommen, Catalin Marinas, Will Deacon, Rob Clark,
Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar,
Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, dri-devel,
freedreno, devicetree
On 6/7/25 4:15 PM, Akhil P Oommen wrote:
> Add support for Adreno X1-45 GPU present Snapdragon X1P42100
> series of compute chipsets. This GPU is a smaller version of
> X1-85 GPU with lower core count and smaller internal memories.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
Matches what I had running, I don't know the source for fuses but
I trust you
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
2025-06-07 14:14 [PATCH 0/3] Support for Adreno X1-45 GPU Akhil P Oommen
2025-06-07 14:14 ` [PATCH 1/3] arm64: defconfig: Enable X1P42100_GPUCC driver Akhil P Oommen
2025-06-07 14:15 ` [PATCH 2/3] drm/msm/adreno: Add Adreno X1-45 support Akhil P Oommen
@ 2025-06-07 14:15 ` Akhil P Oommen
2025-06-07 20:17 ` Dmitry Baryshkov
2025-06-10 14:39 ` Konrad Dybcio
2025-06-08 15:21 ` [PATCH 0/3] Support for Adreno X1-45 GPU Rob Clark
2025-06-09 15:01 ` Rob Herring (Arm)
4 siblings, 2 replies; 19+ messages in thread
From: Akhil P Oommen @ 2025-06-07 14:15 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, dri-devel,
freedreno, devicetree, Akhil P Oommen
X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
version of Adreno X1-85 GPU. Describe this new GPU and also add
the secure gpu firmware path that should used for X1P42100 CRD.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
3 files changed, 131 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
+ qfprom: efuse@221c8000 {
+ compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
+ reg = <0 0x221c8000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
pmu@24091000 {
compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
reg = <0 0x24091000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
index cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
@@ -15,3 +15,7 @@ / {
model = "Qualcomm Technologies, Inc. X1P42100 CRD";
compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
+};
diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
index 27f479010bc330eb6445269a1c46bf78ec6f1bd4..5ed461ed5cca271d43647888aa6eacac3de2ac9d 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
@@ -17,15 +17,134 @@
/delete-node/ &cpu_pd9;
/delete-node/ &cpu_pd10;
/delete-node/ &cpu_pd11;
+/delete-node/ &gpu_opp_table;
/delete-node/ &pcie3_phy;
&gcc {
compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
};
-/* The GPU is physically different and will be brought up later */
+&gmu {
+ /delete-property/ compatible;
+ compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
+};
+
+&qfprom {
+ gpu_speed_bin: gpu_speed_bin@119 {
+ reg = <0x119 0x2>;
+ bits = <7 9>;
+ };
+};
+
&gpu {
/delete-property/ compatible;
+
+ compatible = "qcom,adreno-43030c00", "qcom,adreno";
+
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2-adreno", "operating-points-v2";
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa8295ffd>;
+ opp-supported-hw = <0x3>;
+ };
+
+ opp-1250000000 {
+ opp-hz = /bits/ 64 <1250000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0x882a5ffd>;
+ opp-supported-hw = <0x7>;
+ };
+
+ opp-1107000000 {
+ opp-hz = /bits/ 64 <1107000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0x882a5ffd>;
+ opp-supported-hw = <0xf>;
+ };
+
+ opp-1014000000 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <14398438>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0xf>;
+ };
+
+ opp-940000000 {
+ opp-hz = /bits/ 64 <940000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <14398438>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0xf>;
+ };
+
+ opp-825000000 {
+ opp-hz = /bits/ 64 <825000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <12449219>;
+ qcom,opp-acd-level = <0x882b5ffd>;
+ opp-supported-hw = <0xf>;
+ };
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <10687500>;
+ qcom,opp-acd-level = <0xa82c5ffd>;
+ opp-supported-hw = <0xf>;
+ };
+
+ opp-666000000-0 {
+ opp-hz = /bits/ 64 <666000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <8171875>;
+ qcom,opp-acd-level = <0xa82d5ffd>;
+ opp-supported-hw = <0xf>;
+ };
+
+ /* Only applicable for SKUs which has 666Mhz as Fmax */
+ opp-666000000-1 {
+ opp-hz = /bits/ 64 <666000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa82d5ffd>;
+ opp-supported-hw = <0x10>;
+ };
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <6074219>;
+ qcom,opp-acd-level = <0x882e5ffd>;
+ opp-supported-hw = <0x1f>;
+ };
+
+ opp-380000000 {
+ opp-hz = /bits/ 64 <380000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <3000000>;
+ qcom,opp-acd-level = <0xc82f5ffd>;
+ opp-supported-hw = <0x1f>;
+ };
+
+ opp-280000000 {
+ opp-hz = /bits/ 64 <280000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ opp-peak-kBps = <2136719>;
+ qcom,opp-acd-level = <0xc82f5ffd>;
+ opp-supported-hw = <0x1f>;
+ };
+ };
+
};
&gpucc {
--
2.48.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
2025-06-07 14:15 ` [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC Akhil P Oommen
@ 2025-06-07 20:17 ` Dmitry Baryshkov
2025-06-08 14:10 ` Rob Clark
2025-06-10 14:39 ` Konrad Dybcio
1 sibling, 1 reply; 19+ messages in thread
From: Dmitry Baryshkov @ 2025-06-07 20:17 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Catalin Marinas, Will Deacon, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-kernel, linux-kernel, linux-arm-msm,
dri-devel, freedreno, devicetree
On Sat, Jun 07, 2025 at 07:45:01PM +0530, Akhil P Oommen wrote:
> X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
> version of Adreno X1-85 GPU. Describe this new GPU and also add
> the secure gpu firmware path that should used for X1P42100 CRD.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
> arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
> arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
> 3 files changed, 131 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
> interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + qfprom: efuse@221c8000 {
> + compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
> + reg = <0 0x221c8000 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +
> pmu@24091000 {
> compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> reg = <0 0x24091000 0 0x1000>;
> diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> index cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
> --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> @@ -15,3 +15,7 @@ / {
> model = "Qualcomm Technologies, Inc. X1P42100 CRD";
> compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
> };
> +
> +&gpu_zap_shader {
> + firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> index 27f479010bc330eb6445269a1c46bf78ec6f1bd4..5ed461ed5cca271d43647888aa6eacac3de2ac9d 100644
> --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> @@ -17,15 +17,134 @@
> /delete-node/ &cpu_pd9;
> /delete-node/ &cpu_pd10;
> /delete-node/ &cpu_pd11;
> +/delete-node/ &gpu_opp_table;
> /delete-node/ &pcie3_phy;
>
> &gcc {
> compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
> };
>
> -/* The GPU is physically different and will be brought up later */
> +&gmu {
> + /delete-property/ compatible;
> + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
> +};
> +
> +&qfprom {
> + gpu_speed_bin: gpu_speed_bin@119 {
> + reg = <0x119 0x2>;
> + bits = <7 9>;
> + };
> +};
> +
> &gpu {
> /delete-property/ compatible;
I think, you can drop this line.
> +
> + compatible = "qcom,adreno-43030c00", "qcom,adreno";
> +
> + nvmem-cells = <&gpu_speed_bin>;
> + nvmem-cell-names = "speed_bin";
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2-adreno", "operating-points-v2";
> +
> + opp-1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
> + opp-peak-kBps = <16500000>;
> + qcom,opp-acd-level = <0xa8295ffd>;
> + opp-supported-hw = <0x3>;
> + };
> +
> + opp-1250000000 {
> + opp-hz = /bits/ 64 <1250000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
> + opp-peak-kBps = <16500000>;
> + qcom,opp-acd-level = <0x882a5ffd>;
> + opp-supported-hw = <0x7>;
> + };
> +
> + opp-1107000000 {
> + opp-hz = /bits/ 64 <1107000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + opp-peak-kBps = <16500000>;
> + qcom,opp-acd-level = <0x882a5ffd>;
> + opp-supported-hw = <0xf>;
> + };
> +
> + opp-1014000000 {
> + opp-hz = /bits/ 64 <1014000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + opp-peak-kBps = <14398438>;
> + qcom,opp-acd-level = <0xa82a5ffd>;
> + opp-supported-hw = <0xf>;
> + };
> +
> + opp-940000000 {
> + opp-hz = /bits/ 64 <940000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + opp-peak-kBps = <14398438>;
> + qcom,opp-acd-level = <0xa82a5ffd>;
> + opp-supported-hw = <0xf>;
> + };
> +
> + opp-825000000 {
> + opp-hz = /bits/ 64 <825000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + opp-peak-kBps = <12449219>;
> + qcom,opp-acd-level = <0x882b5ffd>;
> + opp-supported-hw = <0xf>;
> + };
> +
> + opp-720000000 {
> + opp-hz = /bits/ 64 <720000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> + opp-peak-kBps = <10687500>;
> + qcom,opp-acd-level = <0xa82c5ffd>;
> + opp-supported-hw = <0xf>;
> + };
> +
> + opp-666000000-0 {
> + opp-hz = /bits/ 64 <666000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <8171875>;
> + qcom,opp-acd-level = <0xa82d5ffd>;
> + opp-supported-hw = <0xf>;
> + };
> +
> + /* Only applicable for SKUs which has 666Mhz as Fmax */
> + opp-666000000-1 {
> + opp-hz = /bits/ 64 <666000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <16500000>;
This looks odd, why is it so high?
> + qcom,opp-acd-level = <0xa82d5ffd>;
> + opp-supported-hw = <0x10>;
> + };
> +
> + opp-550000000 {
> + opp-hz = /bits/ 64 <550000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + opp-peak-kBps = <6074219>;
> + qcom,opp-acd-level = <0x882e5ffd>;
> + opp-supported-hw = <0x1f>;
> + };
> +
> + opp-380000000 {
> + opp-hz = /bits/ 64 <380000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + opp-peak-kBps = <3000000>;
> + qcom,opp-acd-level = <0xc82f5ffd>;
> + opp-supported-hw = <0x1f>;
> + };
> +
> + opp-280000000 {
> + opp-hz = /bits/ 64 <280000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
> + opp-peak-kBps = <2136719>;
> + qcom,opp-acd-level = <0xc82f5ffd>;
> + opp-supported-hw = <0x1f>;
> + };
> + };
> +
> };
>
> &gpucc {
>
> --
> 2.48.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
2025-06-07 20:17 ` Dmitry Baryshkov
@ 2025-06-08 14:10 ` Rob Clark
2025-06-08 15:09 ` Dmitry Baryshkov
0 siblings, 1 reply; 19+ messages in thread
From: Rob Clark @ 2025-06-08 14:10 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Akhil P Oommen, Catalin Marinas, Will Deacon, Sean Paul,
Konrad Dybcio, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, linux-kernel,
linux-arm-msm, dri-devel, freedreno, devicetree
On Sat, Jun 7, 2025 at 1:17 PM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> On Sat, Jun 07, 2025 at 07:45:01PM +0530, Akhil P Oommen wrote:
> > X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
> > version of Adreno X1-85 GPU. Describe this new GPU and also add
> > the secure gpu firmware path that should used for X1P42100 CRD.
> >
> > Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
> > arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
> > arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
> > 3 files changed, 131 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > index a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > @@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
> > interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > };
> >
> > + qfprom: efuse@221c8000 {
> > + compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
> > + reg = <0 0x221c8000 0 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + };
> > +
> > pmu@24091000 {
> > compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> > reg = <0 0x24091000 0 0x1000>;
> > diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> > index cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
> > --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> > +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> > @@ -15,3 +15,7 @@ / {
> > model = "Qualcomm Technologies, Inc. X1P42100 CRD";
> > compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
> > };
> > +
> > +&gpu_zap_shader {
> > + firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
> > +};
> > diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> > index 27f479010bc330eb6445269a1c46bf78ec6f1bd4..5ed461ed5cca271d43647888aa6eacac3de2ac9d 100644
> > --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> > @@ -17,15 +17,134 @@
> > /delete-node/ &cpu_pd9;
> > /delete-node/ &cpu_pd10;
> > /delete-node/ &cpu_pd11;
> > +/delete-node/ &gpu_opp_table;
> > /delete-node/ &pcie3_phy;
> >
> > &gcc {
> > compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
> > };
> >
> > -/* The GPU is physically different and will be brought up later */
> > +&gmu {
> > + /delete-property/ compatible;
> > + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
> > +};
> > +
> > +&qfprom {
> > + gpu_speed_bin: gpu_speed_bin@119 {
> > + reg = <0x119 0x2>;
> > + bits = <7 9>;
> > + };
> > +};
> > +
> > &gpu {
> > /delete-property/ compatible;
>
> I think, you can drop this line.
>
> > +
> > + compatible = "qcom,adreno-43030c00", "qcom,adreno";
> > +
> > + nvmem-cells = <&gpu_speed_bin>;
> > + nvmem-cell-names = "speed_bin";
> > +
> > + gpu_opp_table: opp-table {
> > + compatible = "operating-points-v2-adreno", "operating-points-v2";
> > +
> > + opp-1400000000 {
> > + opp-hz = /bits/ 64 <1400000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
> > + opp-peak-kBps = <16500000>;
> > + qcom,opp-acd-level = <0xa8295ffd>;
> > + opp-supported-hw = <0x3>;
> > + };
> > +
> > + opp-1250000000 {
> > + opp-hz = /bits/ 64 <1250000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
> > + opp-peak-kBps = <16500000>;
> > + qcom,opp-acd-level = <0x882a5ffd>;
> > + opp-supported-hw = <0x7>;
> > + };
> > +
> > + opp-1107000000 {
> > + opp-hz = /bits/ 64 <1107000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> > + opp-peak-kBps = <16500000>;
> > + qcom,opp-acd-level = <0x882a5ffd>;
> > + opp-supported-hw = <0xf>;
> > + };
> > +
> > + opp-1014000000 {
> > + opp-hz = /bits/ 64 <1014000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> > + opp-peak-kBps = <14398438>;
> > + qcom,opp-acd-level = <0xa82a5ffd>;
> > + opp-supported-hw = <0xf>;
> > + };
> > +
> > + opp-940000000 {
> > + opp-hz = /bits/ 64 <940000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> > + opp-peak-kBps = <14398438>;
> > + qcom,opp-acd-level = <0xa82a5ffd>;
> > + opp-supported-hw = <0xf>;
> > + };
> > +
> > + opp-825000000 {
> > + opp-hz = /bits/ 64 <825000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> > + opp-peak-kBps = <12449219>;
> > + qcom,opp-acd-level = <0x882b5ffd>;
> > + opp-supported-hw = <0xf>;
> > + };
> > +
> > + opp-720000000 {
> > + opp-hz = /bits/ 64 <720000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> > + opp-peak-kBps = <10687500>;
> > + qcom,opp-acd-level = <0xa82c5ffd>;
> > + opp-supported-hw = <0xf>;
> > + };
> > +
> > + opp-666000000-0 {
> > + opp-hz = /bits/ 64 <666000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > + opp-peak-kBps = <8171875>;
> > + qcom,opp-acd-level = <0xa82d5ffd>;
> > + opp-supported-hw = <0xf>;
> > + };
> > +
> > + /* Only applicable for SKUs which has 666Mhz as Fmax */
> > + opp-666000000-1 {
> > + opp-hz = /bits/ 64 <666000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > + opp-peak-kBps = <16500000>;
>
> This looks odd, why is it so high?
You want max bandwidth on max opp
BR,
-R
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
2025-06-08 14:10 ` Rob Clark
@ 2025-06-08 15:09 ` Dmitry Baryshkov
2025-06-08 15:20 ` Rob Clark
0 siblings, 1 reply; 19+ messages in thread
From: Dmitry Baryshkov @ 2025-06-08 15:09 UTC (permalink / raw)
To: Rob Clark
Cc: Akhil P Oommen, Catalin Marinas, Will Deacon, Sean Paul,
Konrad Dybcio, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, linux-kernel,
linux-arm-msm, dri-devel, freedreno, devicetree
On Sun, Jun 08, 2025 at 07:10:11AM -0700, Rob Clark wrote:
> On Sat, Jun 7, 2025 at 1:17 PM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
> >
> > On Sat, Jun 07, 2025 at 07:45:01PM +0530, Akhil P Oommen wrote:
> > > X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
> > > version of Adreno X1-85 GPU. Describe this new GPU and also add
> > > the secure gpu firmware path that should used for X1P42100 CRD.
> > >
> > > Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
> > > arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
> > > arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
> > > 3 files changed, 131 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > > index a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
> > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > > @@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
> > > interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > > };
> > >
> > > + qfprom: efuse@221c8000 {
> > > + compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
> > > + reg = <0 0x221c8000 0 0x1000>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + };
> > > +
> > > pmu@24091000 {
> > > compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> > > reg = <0 0x24091000 0 0x1000>;
> > > diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> > > index cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
> > > --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> > > +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> > > @@ -15,3 +15,7 @@ / {
> > > model = "Qualcomm Technologies, Inc. X1P42100 CRD";
> > > compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
> > > };
> > > +
> > > +&gpu_zap_shader {
> > > + firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
> > > +};
> > > diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> > > index 27f479010bc330eb6445269a1c46bf78ec6f1bd4..5ed461ed5cca271d43647888aa6eacac3de2ac9d 100644
> > > --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> > > @@ -17,15 +17,134 @@
> > > /delete-node/ &cpu_pd9;
> > > /delete-node/ &cpu_pd10;
> > > /delete-node/ &cpu_pd11;
> > > +/delete-node/ &gpu_opp_table;
> > > /delete-node/ &pcie3_phy;
> > >
> > > &gcc {
> > > compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
> > > };
> > >
> > > -/* The GPU is physically different and will be brought up later */
> > > +&gmu {
> > > + /delete-property/ compatible;
> > > + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
> > > +};
> > > +
> > > +&qfprom {
> > > + gpu_speed_bin: gpu_speed_bin@119 {
> > > + reg = <0x119 0x2>;
> > > + bits = <7 9>;
> > > + };
> > > +};
> > > +
> > > &gpu {
> > > /delete-property/ compatible;
> >
> > I think, you can drop this line.
> >
> > > +
> > > + compatible = "qcom,adreno-43030c00", "qcom,adreno";
> > > +
> > > + nvmem-cells = <&gpu_speed_bin>;
> > > + nvmem-cell-names = "speed_bin";
> > > +
> > > + gpu_opp_table: opp-table {
> > > + compatible = "operating-points-v2-adreno", "operating-points-v2";
> > > +
> > > + opp-1400000000 {
> > > + opp-hz = /bits/ 64 <1400000000>;
> > > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
> > > + opp-peak-kBps = <16500000>;
> > > + qcom,opp-acd-level = <0xa8295ffd>;
> > > + opp-supported-hw = <0x3>;
> > > + };
> > > +
> > > + opp-1250000000 {
> > > + opp-hz = /bits/ 64 <1250000000>;
> > > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
> > > + opp-peak-kBps = <16500000>;
> > > + qcom,opp-acd-level = <0x882a5ffd>;
> > > + opp-supported-hw = <0x7>;
> > > + };
> > > +
> > > + opp-1107000000 {
> > > + opp-hz = /bits/ 64 <1107000000>;
> > > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> > > + opp-peak-kBps = <16500000>;
> > > + qcom,opp-acd-level = <0x882a5ffd>;
> > > + opp-supported-hw = <0xf>;
> > > + };
> > > +
> > > + opp-1014000000 {
> > > + opp-hz = /bits/ 64 <1014000000>;
> > > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> > > + opp-peak-kBps = <14398438>;
> > > + qcom,opp-acd-level = <0xa82a5ffd>;
> > > + opp-supported-hw = <0xf>;
> > > + };
> > > +
> > > + opp-940000000 {
> > > + opp-hz = /bits/ 64 <940000000>;
> > > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> > > + opp-peak-kBps = <14398438>;
> > > + qcom,opp-acd-level = <0xa82a5ffd>;
> > > + opp-supported-hw = <0xf>;
> > > + };
> > > +
> > > + opp-825000000 {
> > > + opp-hz = /bits/ 64 <825000000>;
> > > + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> > > + opp-peak-kBps = <12449219>;
> > > + qcom,opp-acd-level = <0x882b5ffd>;
> > > + opp-supported-hw = <0xf>;
> > > + };
> > > +
> > > + opp-720000000 {
> > > + opp-hz = /bits/ 64 <720000000>;
> > > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> > > + opp-peak-kBps = <10687500>;
> > > + qcom,opp-acd-level = <0xa82c5ffd>;
> > > + opp-supported-hw = <0xf>;
> > > + };
> > > +
> > > + opp-666000000-0 {
> > > + opp-hz = /bits/ 64 <666000000>;
> > > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > > + opp-peak-kBps = <8171875>;
> > > + qcom,opp-acd-level = <0xa82d5ffd>;
> > > + opp-supported-hw = <0xf>;
> > > + };
> > > +
> > > + /* Only applicable for SKUs which has 666Mhz as Fmax */
> > > + opp-666000000-1 {
> > > + opp-hz = /bits/ 64 <666000000>;
> > > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > > + opp-peak-kBps = <16500000>;
> >
> > This looks odd, why is it so high?
>
> You want max bandwidth on max opp
Yes, but can it actually sustain / provide this BW?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
2025-06-08 15:09 ` Dmitry Baryshkov
@ 2025-06-08 15:20 ` Rob Clark
2025-06-08 15:22 ` Dmitry Baryshkov
0 siblings, 1 reply; 19+ messages in thread
From: Rob Clark @ 2025-06-08 15:20 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Akhil P Oommen, Catalin Marinas, Will Deacon, Sean Paul,
Konrad Dybcio, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, linux-kernel,
linux-arm-msm, dri-devel, freedreno, devicetree
On Sun, Jun 8, 2025 at 8:09 AM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> On Sun, Jun 08, 2025 at 07:10:11AM -0700, Rob Clark wrote:
> > On Sat, Jun 7, 2025 at 1:17 PM Dmitry Baryshkov
> > <dmitry.baryshkov@oss.qualcomm.com> wrote:
> > >
> > > On Sat, Jun 07, 2025 at 07:45:01PM +0530, Akhil P Oommen wrote:
> > > > X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
> > > > version of Adreno X1-85 GPU. Describe this new GPU and also add
> > > > the secure gpu firmware path that should used for X1P42100 CRD.
> > > >
> > > > Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> > > > ---
> > > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
> > > > arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
> > > > arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
> > > > 3 files changed, 131 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > > > index a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
> > > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > > > @@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
> > > > interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > > > };
> > > >
> > > > + qfprom: efuse@221c8000 {
> > > > + compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
> > > > + reg = <0 0x221c8000 0 0x1000>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + };
> > > > +
> > > > pmu@24091000 {
> > > > compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> > > > reg = <0 0x24091000 0 0x1000>;
> > > > diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> > > > index cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
> > > > --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> > > > +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> > > > @@ -15,3 +15,7 @@ / {
> > > > model = "Qualcomm Technologies, Inc. X1P42100 CRD";
> > > > compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
> > > > };
> > > > +
> > > > +&gpu_zap_shader {
> > > > + firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
> > > > +};
> > > > diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> > > > index 27f479010bc330eb6445269a1c46bf78ec6f1bd4..5ed461ed5cca271d43647888aa6eacac3de2ac9d 100644
> > > > --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> > > > @@ -17,15 +17,134 @@
> > > > /delete-node/ &cpu_pd9;
> > > > /delete-node/ &cpu_pd10;
> > > > /delete-node/ &cpu_pd11;
> > > > +/delete-node/ &gpu_opp_table;
> > > > /delete-node/ &pcie3_phy;
> > > >
> > > > &gcc {
> > > > compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
> > > > };
> > > >
> > > > -/* The GPU is physically different and will be brought up later */
> > > > +&gmu {
> > > > + /delete-property/ compatible;
> > > > + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
> > > > +};
> > > > +
> > > > +&qfprom {
> > > > + gpu_speed_bin: gpu_speed_bin@119 {
> > > > + reg = <0x119 0x2>;
> > > > + bits = <7 9>;
> > > > + };
> > > > +};
> > > > +
> > > > &gpu {
> > > > /delete-property/ compatible;
> > >
> > > I think, you can drop this line.
> > >
> > > > +
> > > > + compatible = "qcom,adreno-43030c00", "qcom,adreno";
> > > > +
> > > > + nvmem-cells = <&gpu_speed_bin>;
> > > > + nvmem-cell-names = "speed_bin";
> > > > +
> > > > + gpu_opp_table: opp-table {
> > > > + compatible = "operating-points-v2-adreno", "operating-points-v2";
> > > > +
> > > > + opp-1400000000 {
> > > > + opp-hz = /bits/ 64 <1400000000>;
> > > > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
> > > > + opp-peak-kBps = <16500000>;
> > > > + qcom,opp-acd-level = <0xa8295ffd>;
> > > > + opp-supported-hw = <0x3>;
> > > > + };
> > > > +
> > > > + opp-1250000000 {
> > > > + opp-hz = /bits/ 64 <1250000000>;
> > > > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
> > > > + opp-peak-kBps = <16500000>;
> > > > + qcom,opp-acd-level = <0x882a5ffd>;
> > > > + opp-supported-hw = <0x7>;
> > > > + };
> > > > +
> > > > + opp-1107000000 {
> > > > + opp-hz = /bits/ 64 <1107000000>;
> > > > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> > > > + opp-peak-kBps = <16500000>;
> > > > + qcom,opp-acd-level = <0x882a5ffd>;
> > > > + opp-supported-hw = <0xf>;
> > > > + };
> > > > +
> > > > + opp-1014000000 {
> > > > + opp-hz = /bits/ 64 <1014000000>;
> > > > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> > > > + opp-peak-kBps = <14398438>;
> > > > + qcom,opp-acd-level = <0xa82a5ffd>;
> > > > + opp-supported-hw = <0xf>;
> > > > + };
> > > > +
> > > > + opp-940000000 {
> > > > + opp-hz = /bits/ 64 <940000000>;
> > > > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> > > > + opp-peak-kBps = <14398438>;
> > > > + qcom,opp-acd-level = <0xa82a5ffd>;
> > > > + opp-supported-hw = <0xf>;
> > > > + };
> > > > +
> > > > + opp-825000000 {
> > > > + opp-hz = /bits/ 64 <825000000>;
> > > > + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> > > > + opp-peak-kBps = <12449219>;
> > > > + qcom,opp-acd-level = <0x882b5ffd>;
> > > > + opp-supported-hw = <0xf>;
> > > > + };
> > > > +
> > > > + opp-720000000 {
> > > > + opp-hz = /bits/ 64 <720000000>;
> > > > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> > > > + opp-peak-kBps = <10687500>;
> > > > + qcom,opp-acd-level = <0xa82c5ffd>;
> > > > + opp-supported-hw = <0xf>;
> > > > + };
> > > > +
> > > > + opp-666000000-0 {
> > > > + opp-hz = /bits/ 64 <666000000>;
> > > > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > > > + opp-peak-kBps = <8171875>;
> > > > + qcom,opp-acd-level = <0xa82d5ffd>;
> > > > + opp-supported-hw = <0xf>;
> > > > + };
> > > > +
> > > > + /* Only applicable for SKUs which has 666Mhz as Fmax */
> > > > + opp-666000000-1 {
> > > > + opp-hz = /bits/ 64 <666000000>;
> > > > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > > > + opp-peak-kBps = <16500000>;
> > >
> > > This looks odd, why is it so high?
> >
> > You want max bandwidth on max opp
>
> Yes, but can it actually sustain / provide this BW?
>
I'd have to trust Akhil on that one, but I have no reason to believe
otherwise. Just pointing out we've done analogous things elsewhere
(for ex, cpu bw for sc7180-lite.dtsi)
BR,
-R
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
2025-06-08 15:20 ` Rob Clark
@ 2025-06-08 15:22 ` Dmitry Baryshkov
2025-06-08 20:18 ` Akhil P Oommen
0 siblings, 1 reply; 19+ messages in thread
From: Dmitry Baryshkov @ 2025-06-08 15:22 UTC (permalink / raw)
To: rob.clark
Cc: Akhil P Oommen, Catalin Marinas, Will Deacon, Sean Paul,
Konrad Dybcio, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, linux-kernel,
linux-arm-msm, dri-devel, freedreno, devicetree
On 08/06/2025 18:20, Rob Clark wrote:
> On Sun, Jun 8, 2025 at 8:09 AM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>
>> On Sun, Jun 08, 2025 at 07:10:11AM -0700, Rob Clark wrote:
>>> On Sat, Jun 7, 2025 at 1:17 PM Dmitry Baryshkov
>>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>>>
>>>> On Sat, Jun 07, 2025 at 07:45:01PM +0530, Akhil P Oommen wrote:
>>>>> X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
>>>>> version of Adreno X1-85 GPU. Describe this new GPU and also add
>>>>> the secure gpu firmware path that should used for X1P42100 CRD.
>>>>>
>>>>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
>>>>> arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
>>>>> arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
>>>>> 3 files changed, 131 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>> index a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>> @@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
>>>>> interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>>>>> };
>>>>>
>>>>> + qfprom: efuse@221c8000 {
>>>>> + compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
>>>>> + reg = <0 0x221c8000 0 0x1000>;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <1>;
>>>>> + };
>>>>> +
>>>>> pmu@24091000 {
>>>>> compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
>>>>> reg = <0 0x24091000 0 0x1000>;
>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
>>>>> index cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
>>>>> +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
>>>>> @@ -15,3 +15,7 @@ / {
>>>>> model = "Qualcomm Technologies, Inc. X1P42100 CRD";
>>>>> compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
>>>>> };
>>>>> +
>>>>> +&gpu_zap_shader {
>>>>> + firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
>>>>> +};
>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
>>>>> index 27f479010bc330eb6445269a1c46bf78ec6f1bd4..5ed461ed5cca271d43647888aa6eacac3de2ac9d 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
>>>>> @@ -17,15 +17,134 @@
>>>>> /delete-node/ &cpu_pd9;
>>>>> /delete-node/ &cpu_pd10;
>>>>> /delete-node/ &cpu_pd11;
>>>>> +/delete-node/ &gpu_opp_table;
>>>>> /delete-node/ &pcie3_phy;
>>>>>
>>>>> &gcc {
>>>>> compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
>>>>> };
>>>>>
>>>>> -/* The GPU is physically different and will be brought up later */
>>>>> +&gmu {
>>>>> + /delete-property/ compatible;
>>>>> + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
>>>>> +};
>>>>> +
>>>>> +&qfprom {
>>>>> + gpu_speed_bin: gpu_speed_bin@119 {
>>>>> + reg = <0x119 0x2>;
>>>>> + bits = <7 9>;
>>>>> + };
>>>>> +};
>>>>> +
>>>>> &gpu {
>>>>> /delete-property/ compatible;
>>>>
>>>> I think, you can drop this line.
>>>>
>>>>> +
>>>>> + compatible = "qcom,adreno-43030c00", "qcom,adreno";
>>>>> +
>>>>> + nvmem-cells = <&gpu_speed_bin>;
>>>>> + nvmem-cell-names = "speed_bin";
>>>>> +
>>>>> + gpu_opp_table: opp-table {
>>>>> + compatible = "operating-points-v2-adreno", "operating-points-v2";
>>>>> +
>>>>> + opp-1400000000 {
>>>>> + opp-hz = /bits/ 64 <1400000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
>>>>> + opp-peak-kBps = <16500000>;
>>>>> + qcom,opp-acd-level = <0xa8295ffd>;
>>>>> + opp-supported-hw = <0x3>;
>>>>> + };
>>>>> +
>>>>> + opp-1250000000 {
>>>>> + opp-hz = /bits/ 64 <1250000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
>>>>> + opp-peak-kBps = <16500000>;
>>>>> + qcom,opp-acd-level = <0x882a5ffd>;
>>>>> + opp-supported-hw = <0x7>;
>>>>> + };
>>>>> +
>>>>> + opp-1107000000 {
>>>>> + opp-hz = /bits/ 64 <1107000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
>>>>> + opp-peak-kBps = <16500000>;
>>>>> + qcom,opp-acd-level = <0x882a5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-1014000000 {
>>>>> + opp-hz = /bits/ 64 <1014000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>>>>> + opp-peak-kBps = <14398438>;
>>>>> + qcom,opp-acd-level = <0xa82a5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-940000000 {
>>>>> + opp-hz = /bits/ 64 <940000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>>>>> + opp-peak-kBps = <14398438>;
>>>>> + qcom,opp-acd-level = <0xa82a5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-825000000 {
>>>>> + opp-hz = /bits/ 64 <825000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>>>>> + opp-peak-kBps = <12449219>;
>>>>> + qcom,opp-acd-level = <0x882b5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-720000000 {
>>>>> + opp-hz = /bits/ 64 <720000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
>>>>> + opp-peak-kBps = <10687500>;
>>>>> + qcom,opp-acd-level = <0xa82c5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + opp-666000000-0 {
>>>>> + opp-hz = /bits/ 64 <666000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>>>> + opp-peak-kBps = <8171875>;
>>>>> + qcom,opp-acd-level = <0xa82d5ffd>;
>>>>> + opp-supported-hw = <0xf>;
>>>>> + };
>>>>> +
>>>>> + /* Only applicable for SKUs which has 666Mhz as Fmax */
>>>>> + opp-666000000-1 {
>>>>> + opp-hz = /bits/ 64 <666000000>;
>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>>>> + opp-peak-kBps = <16500000>;
>>>>
>>>> This looks odd, why is it so high?
>>>
>>> You want max bandwidth on max opp
>>
>> Yes, but can it actually sustain / provide this BW?
>>
>
> I'd have to trust Akhil on that one, but I have no reason to believe
> otherwise. Just pointing out we've done analogous things elsewhere
> (for ex, cpu bw for sc7180-lite.dtsi)
Ack. Then I'll wait for v2 with no deleting of compatible lines (a new
line here would just replace the existing one).
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
2025-06-08 15:22 ` Dmitry Baryshkov
@ 2025-06-08 20:18 ` Akhil P Oommen
2025-06-08 22:19 ` Dmitry Baryshkov
0 siblings, 1 reply; 19+ messages in thread
From: Akhil P Oommen @ 2025-06-08 20:18 UTC (permalink / raw)
To: Dmitry Baryshkov, rob.clark
Cc: Akhil P Oommen, Catalin Marinas, Will Deacon, Sean Paul,
Konrad Dybcio, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, linux-kernel,
linux-arm-msm, dri-devel, freedreno, devicetree
On 6/8/2025 8:52 PM, Dmitry Baryshkov wrote:
> On 08/06/2025 18:20, Rob Clark wrote:
>> On Sun, Jun 8, 2025 at 8:09 AM Dmitry Baryshkov
>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>>
>>> On Sun, Jun 08, 2025 at 07:10:11AM -0700, Rob Clark wrote:
>>>> On Sat, Jun 7, 2025 at 1:17 PM Dmitry Baryshkov
>>>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>>>>
>>>>> On Sat, Jun 07, 2025 at 07:45:01PM +0530, Akhil P Oommen wrote:
>>>>>> X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
>>>>>> version of Adreno X1-85 GPU. Describe this new GPU and also add
>>>>>> the secure gpu firmware path that should used for X1P42100 CRD.
>>>>>>
>>>>>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>>>>>> ---
>>>>>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
>>>>>> arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
>>>>>> arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 ++++++++++++++++
>>>>>> +++++++++++++-
>>>>>> 3 files changed, 131 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/
>>>>>> boot/dts/qcom/x1e80100.dtsi
>>>>>> index
>>>>>> a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>>>>> @@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
>>>>>> interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> };
>>>>>>
>>>>>> + qfprom: efuse@221c8000 {
>>>>>> + compatible = "qcom,x1e80100-qfprom",
>>>>>> "qcom,qfprom";
>>>>>> + reg = <0 0x221c8000 0 0x1000>;
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <1>;
>>>>>> + };
>>>>>> +
>>>>>> pmu@24091000 {
>>>>>> compatible = "qcom,x1e80100-llcc-bwmon",
>>>>>> "qcom,sc7280-llcc-bwmon";
>>>>>> reg = <0 0x24091000 0 0x1000>;
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/
>>>>>> arm64/boot/dts/qcom/x1p42100-crd.dts
>>>>>> index
>>>>>> cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
>>>>>> +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
>>>>>> @@ -15,3 +15,7 @@ / {
>>>>>> model = "Qualcomm Technologies, Inc. X1P42100 CRD";
>>>>>> compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
>>>>>> };
>>>>>> +
>>>>>> +&gpu_zap_shader {
>>>>>> + firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
>>>>>> +};
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/
>>>>>> boot/dts/qcom/x1p42100.dtsi
>>>>>> index
>>>>>> 27f479010bc330eb6445269a1c46bf78ec6f1bd4..5ed461ed5cca271d43647888aa6eacac3de2ac9d 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
>>>>>> @@ -17,15 +17,134 @@
>>>>>> /delete-node/ &cpu_pd9;
>>>>>> /delete-node/ &cpu_pd10;
>>>>>> /delete-node/ &cpu_pd11;
>>>>>> +/delete-node/ &gpu_opp_table;
>>>>>> /delete-node/ &pcie3_phy;
>>>>>>
>>>>>> &gcc {
>>>>>> compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
>>>>>> };
>>>>>>
>>>>>> -/* The GPU is physically different and will be brought up later */
>>>>>> +&gmu {
>>>>>> + /delete-property/ compatible;
>>>>>> + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
>>>>>> +};
>>>>>> +
>>>>>> +&qfprom {
>>>>>> + gpu_speed_bin: gpu_speed_bin@119 {
>>>>>> + reg = <0x119 0x2>;
>>>>>> + bits = <7 9>;
>>>>>> + };
>>>>>> +};
>>>>>> +
>>>>>> &gpu {
>>>>>> /delete-property/ compatible;
>>>>>
>>>>> I think, you can drop this line.
I wasn't sure about this and I thought it was harmless to delete it.
Anyway, I will remove the "delete" from both GPU and GMU nodes.
>>>>>
>>>>>> +
>>>>>> + compatible = "qcom,adreno-43030c00", "qcom,adreno";
>>>>>> +
>>>>>> + nvmem-cells = <&gpu_speed_bin>;
>>>>>> + nvmem-cell-names = "speed_bin";
>>>>>> +
>>>>>> + gpu_opp_table: opp-table {
>>>>>> + compatible = "operating-points-v2-adreno",
>>>>>> "operating-points-v2";
>>>>>> +
>>>>>> + opp-1400000000 {
>>>>>> + opp-hz = /bits/ 64 <1400000000>;
>>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
>>>>>> + opp-peak-kBps = <16500000>;
>>>>>> + qcom,opp-acd-level = <0xa8295ffd>;
>>>>>> + opp-supported-hw = <0x3>;
>>>>>> + };
>>>>>> +
>>>>>> + opp-1250000000 {
>>>>>> + opp-hz = /bits/ 64 <1250000000>;
>>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
>>>>>> + opp-peak-kBps = <16500000>;
>>>>>> + qcom,opp-acd-level = <0x882a5ffd>;
>>>>>> + opp-supported-hw = <0x7>;
>>>>>> + };
>>>>>> +
>>>>>> + opp-1107000000 {
>>>>>> + opp-hz = /bits/ 64 <1107000000>;
>>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
>>>>>> + opp-peak-kBps = <16500000>;
>>>>>> + qcom,opp-acd-level = <0x882a5ffd>;
>>>>>> + opp-supported-hw = <0xf>;
>>>>>> + };
>>>>>> +
>>>>>> + opp-1014000000 {
>>>>>> + opp-hz = /bits/ 64 <1014000000>;
>>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>>>>>> + opp-peak-kBps = <14398438>;
>>>>>> + qcom,opp-acd-level = <0xa82a5ffd>;
>>>>>> + opp-supported-hw = <0xf>;
>>>>>> + };
>>>>>> +
>>>>>> + opp-940000000 {
>>>>>> + opp-hz = /bits/ 64 <940000000>;
>>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>>>>>> + opp-peak-kBps = <14398438>;
>>>>>> + qcom,opp-acd-level = <0xa82a5ffd>;
>>>>>> + opp-supported-hw = <0xf>;
>>>>>> + };
>>>>>> +
>>>>>> + opp-825000000 {
>>>>>> + opp-hz = /bits/ 64 <825000000>;
>>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>>>>>> + opp-peak-kBps = <12449219>;
>>>>>> + qcom,opp-acd-level = <0x882b5ffd>;
>>>>>> + opp-supported-hw = <0xf>;
>>>>>> + };
>>>>>> +
>>>>>> + opp-720000000 {
>>>>>> + opp-hz = /bits/ 64 <720000000>;
>>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
>>>>>> + opp-peak-kBps = <10687500>;
>>>>>> + qcom,opp-acd-level = <0xa82c5ffd>;
>>>>>> + opp-supported-hw = <0xf>;
>>>>>> + };
>>>>>> +
>>>>>> + opp-666000000-0 {
>>>>>> + opp-hz = /bits/ 64 <666000000>;
>>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>>>>> + opp-peak-kBps = <8171875>;
>>>>>> + qcom,opp-acd-level = <0xa82d5ffd>;
>>>>>> + opp-supported-hw = <0xf>;
>>>>>> + };
>>>>>> +
>>>>>> + /* Only applicable for SKUs which has 666Mhz as Fmax */
>>>>>> + opp-666000000-1 {
>>>>>> + opp-hz = /bits/ 64 <666000000>;
>>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>>>>> + opp-peak-kBps = <16500000>;
>>>>>
>>>>> This looks odd, why is it so high?
>>>>
>>>> You want max bandwidth on max opp
>>>
>>> Yes, but can it actually sustain / provide this BW?
>>>
>>
>> I'd have to trust Akhil on that one, but I have no reason to believe
>> otherwise. Just pointing out we've done analogous things elsewhere
>> (for ex, cpu bw for sc7180-lite.dtsi)
Window's GPU KMD seems to vote Max bandwidth for this SKU, so I think
this is fine. Our GPUs from last few generations can easily saturate DDR
with the right usecase.
-Akhil
>
> Ack. Then I'll wait for v2 with no deleting of compatible lines (a new
> line here would just replace the existing one).
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
2025-06-08 20:18 ` Akhil P Oommen
@ 2025-06-08 22:19 ` Dmitry Baryshkov
0 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2025-06-08 22:19 UTC (permalink / raw)
To: Akhil P Oommen
Cc: rob.clark, Akhil P Oommen, Catalin Marinas, Will Deacon,
Sean Paul, Konrad Dybcio, Abhinav Kumar, Jessica Zhang,
Marijn Suijten, David Airlie, Simona Vetter, Bjorn Andersson,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
linux-kernel, linux-arm-msm, dri-devel, freedreno, devicetree
On Sun, 8 Jun 2025 at 23:18, Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
>
> On 6/8/2025 8:52 PM, Dmitry Baryshkov wrote:
> > On 08/06/2025 18:20, Rob Clark wrote:
> >> On Sun, Jun 8, 2025 at 8:09 AM Dmitry Baryshkov
> >> <dmitry.baryshkov@oss.qualcomm.com> wrote:
> >>>
> >>> On Sun, Jun 08, 2025 at 07:10:11AM -0700, Rob Clark wrote:
> >>>> On Sat, Jun 7, 2025 at 1:17 PM Dmitry Baryshkov
> >>>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
> >>>>>
> >>>>> On Sat, Jun 07, 2025 at 07:45:01PM +0530, Akhil P Oommen wrote:
> >>>>>> X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
> >>>>>> version of Adreno X1-85 GPU. Describe this new GPU and also add
> >>>>>> the secure gpu firmware path that should used for X1P42100 CRD.
> >>>>>>
> >>>>>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> >>>>>> ---
> >>>>>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
> >>>>>> arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
> >>>>>> arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 ++++++++++++++++
> >>>>>> +++++++++++++-
> >>>>>> 3 files changed, 131 insertions(+), 1 deletion(-)
> >>>>>>
> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/
> >>>>>> boot/dts/qcom/x1e80100.dtsi
> >>>>>> index
> >>>>>> a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
> >>>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> >>>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> >>>>>> @@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
> >>>>>> interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> >>>>>> };
> >>>>>>
> >>>>>> + qfprom: efuse@221c8000 {
> >>>>>> + compatible = "qcom,x1e80100-qfprom",
> >>>>>> "qcom,qfprom";
> >>>>>> + reg = <0 0x221c8000 0 0x1000>;
> >>>>>> + #address-cells = <1>;
> >>>>>> + #size-cells = <1>;
> >>>>>> + };
> >>>>>> +
> >>>>>> pmu@24091000 {
> >>>>>> compatible = "qcom,x1e80100-llcc-bwmon",
> >>>>>> "qcom,sc7280-llcc-bwmon";
> >>>>>> reg = <0 0x24091000 0 0x1000>;
> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/
> >>>>>> arm64/boot/dts/qcom/x1p42100-crd.dts
> >>>>>> index
> >>>>>> cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
> >>>>>> --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> >>>>>> +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
> >>>>>> @@ -15,3 +15,7 @@ / {
> >>>>>> model = "Qualcomm Technologies, Inc. X1P42100 CRD";
> >>>>>> compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
> >>>>>> };
> >>>>>> +
> >>>>>> +&gpu_zap_shader {
> >>>>>> + firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
> >>>>>> +};
> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/
> >>>>>> boot/dts/qcom/x1p42100.dtsi
> >>>>>> index
> >>>>>> 27f479010bc330eb6445269a1c46bf78ec6f1bd4..5ed461ed5cca271d43647888aa6eacac3de2ac9d 100644
> >>>>>> --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> >>>>>> +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
> >>>>>> @@ -17,15 +17,134 @@
> >>>>>> /delete-node/ &cpu_pd9;
> >>>>>> /delete-node/ &cpu_pd10;
> >>>>>> /delete-node/ &cpu_pd11;
> >>>>>> +/delete-node/ &gpu_opp_table;
> >>>>>> /delete-node/ &pcie3_phy;
> >>>>>>
> >>>>>> &gcc {
> >>>>>> compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
> >>>>>> };
> >>>>>>
> >>>>>> -/* The GPU is physically different and will be brought up later */
> >>>>>> +&gmu {
> >>>>>> + /delete-property/ compatible;
> >>>>>> + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
> >>>>>> +};
> >>>>>> +
> >>>>>> +&qfprom {
> >>>>>> + gpu_speed_bin: gpu_speed_bin@119 {
> >>>>>> + reg = <0x119 0x2>;
> >>>>>> + bits = <7 9>;
> >>>>>> + };
> >>>>>> +};
> >>>>>> +
> >>>>>> &gpu {
> >>>>>> /delete-property/ compatible;
> >>>>>
> >>>>> I think, you can drop this line.
>
> I wasn't sure about this and I thought it was harmless to delete it.
> Anyway, I will remove the "delete" from both GPU and GMU nodes.
You can always run fdtdump on the compiled file and check the contents.
>
> >>>>>
> >>>>>> +
> >>>>>> + compatible = "qcom,adreno-43030c00", "qcom,adreno";
> >>>>>> +
> >>>>>> + nvmem-cells = <&gpu_speed_bin>;
> >>>>>> + nvmem-cell-names = "speed_bin";
> >>>>>> +
> >>>>>> + gpu_opp_table: opp-table {
> >>>>>> + compatible = "operating-points-v2-adreno",
> >>>>>> "operating-points-v2";
> >>>>>> +
> >>>>>> + opp-1400000000 {
> >>>>>> + opp-hz = /bits/ 64 <1400000000>;
> >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
> >>>>>> + opp-peak-kBps = <16500000>;
> >>>>>> + qcom,opp-acd-level = <0xa8295ffd>;
> >>>>>> + opp-supported-hw = <0x3>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + opp-1250000000 {
> >>>>>> + opp-hz = /bits/ 64 <1250000000>;
> >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
> >>>>>> + opp-peak-kBps = <16500000>;
> >>>>>> + qcom,opp-acd-level = <0x882a5ffd>;
> >>>>>> + opp-supported-hw = <0x7>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + opp-1107000000 {
> >>>>>> + opp-hz = /bits/ 64 <1107000000>;
> >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> >>>>>> + opp-peak-kBps = <16500000>;
> >>>>>> + qcom,opp-acd-level = <0x882a5ffd>;
> >>>>>> + opp-supported-hw = <0xf>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + opp-1014000000 {
> >>>>>> + opp-hz = /bits/ 64 <1014000000>;
> >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> >>>>>> + opp-peak-kBps = <14398438>;
> >>>>>> + qcom,opp-acd-level = <0xa82a5ffd>;
> >>>>>> + opp-supported-hw = <0xf>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + opp-940000000 {
> >>>>>> + opp-hz = /bits/ 64 <940000000>;
> >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> >>>>>> + opp-peak-kBps = <14398438>;
> >>>>>> + qcom,opp-acd-level = <0xa82a5ffd>;
> >>>>>> + opp-supported-hw = <0xf>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + opp-825000000 {
> >>>>>> + opp-hz = /bits/ 64 <825000000>;
> >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> >>>>>> + opp-peak-kBps = <12449219>;
> >>>>>> + qcom,opp-acd-level = <0x882b5ffd>;
> >>>>>> + opp-supported-hw = <0xf>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + opp-720000000 {
> >>>>>> + opp-hz = /bits/ 64 <720000000>;
> >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> >>>>>> + opp-peak-kBps = <10687500>;
> >>>>>> + qcom,opp-acd-level = <0xa82c5ffd>;
> >>>>>> + opp-supported-hw = <0xf>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + opp-666000000-0 {
> >>>>>> + opp-hz = /bits/ 64 <666000000>;
> >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> >>>>>> + opp-peak-kBps = <8171875>;
> >>>>>> + qcom,opp-acd-level = <0xa82d5ffd>;
> >>>>>> + opp-supported-hw = <0xf>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + /* Only applicable for SKUs which has 666Mhz as Fmax */
> >>>>>> + opp-666000000-1 {
> >>>>>> + opp-hz = /bits/ 64 <666000000>;
> >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> >>>>>> + opp-peak-kBps = <16500000>;
> >>>>>
> >>>>> This looks odd, why is it so high?
> >>>>
> >>>> You want max bandwidth on max opp
> >>>
> >>> Yes, but can it actually sustain / provide this BW?
> >>>
> >>
> >> I'd have to trust Akhil on that one, but I have no reason to believe
> >> otherwise. Just pointing out we've done analogous things elsewhere
> >> (for ex, cpu bw for sc7180-lite.dtsi)
>
> Window's GPU KMD seems to vote Max bandwidth for this SKU, so I think
> this is fine. Our GPUs from last few generations can easily saturate DDR
> with the right usecase.
Ack
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC
2025-06-07 14:15 ` [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC Akhil P Oommen
2025-06-07 20:17 ` Dmitry Baryshkov
@ 2025-06-10 14:39 ` Konrad Dybcio
1 sibling, 0 replies; 19+ messages in thread
From: Konrad Dybcio @ 2025-06-10 14:39 UTC (permalink / raw)
To: Akhil P Oommen, Catalin Marinas, Will Deacon, Rob Clark,
Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar,
Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, dri-devel,
freedreno, devicetree
On 6/7/25 4:15 PM, Akhil P Oommen wrote:
> X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
> version of Adreno X1-85 GPU. Describe this new GPU and also add
> the secure gpu firmware path that should used for X1P42100 CRD.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
[...]
> -/* The GPU is physically different and will be brought up later */
> +&gmu {
> + /delete-property/ compatible;
> + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
> +};
> +
> +&qfprom {
> + gpu_speed_bin: gpu_speed_bin@119 {
> + reg = <0x119 0x2>;
> + bits = <7 9>;
> + };
> +};
Please sort the label references alpabetically
> +
> &gpu {
Konrad
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 0/3] Support for Adreno X1-45 GPU
2025-06-07 14:14 [PATCH 0/3] Support for Adreno X1-45 GPU Akhil P Oommen
` (2 preceding siblings ...)
2025-06-07 14:15 ` [PATCH 3/3] arm64: dts: qcom: Add GPU support to X1P42100 SoC Akhil P Oommen
@ 2025-06-08 15:21 ` Rob Clark
2025-06-16 5:07 ` Akhil P Oommen
2025-06-09 15:01 ` Rob Herring (Arm)
4 siblings, 1 reply; 19+ messages in thread
From: Rob Clark @ 2025-06-08 15:21 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Catalin Marinas, Will Deacon, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, linux-kernel,
linux-arm-msm, dri-devel, freedreno, devicetree
On Sat, Jun 7, 2025 at 7:15 AM Akhil P Oommen <akhilpo@oss.qualcomm.com> wrote:
>
> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
> version). X1-45 is a smaller version of X1-85 with lower core count and
> smaller memories. From UMD perspective, this is similar to "FD735"
> present in Mesa.
>
> Tested Glmark & Vkmark on Debian Gnome desktop.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
fyi, mesa part: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35404
BR,
-R
> ---
> Akhil P Oommen (3):
> arm64: defconfig: Enable X1P42100_GPUCC driver
> drm/msm/adreno: Add Adreno X1-45 support
> arm64: dts: qcom: Add GPU support to X1P42100 SoC
>
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
> arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
> arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
> arch/arm64/configs/defconfig | 1 +
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 38 ++++++++++
> 5 files changed, 170 insertions(+), 1 deletion(-)
> ---
> base-commit: b3bded85d838336326ce78e394e7818445e11f20
> change-id: 20250603-x1p-adreno-219da2fd4ca4
>
> Best regards,
> --
> Akhil P Oommen <akhilpo@oss.qualcomm.com>
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 0/3] Support for Adreno X1-45 GPU
2025-06-08 15:21 ` [PATCH 0/3] Support for Adreno X1-45 GPU Rob Clark
@ 2025-06-16 5:07 ` Akhil P Oommen
0 siblings, 0 replies; 19+ messages in thread
From: Akhil P Oommen @ 2025-06-16 5:07 UTC (permalink / raw)
To: rob.clark, Akhil P Oommen
Cc: Catalin Marinas, Will Deacon, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, linux-kernel,
linux-arm-msm, dri-devel, freedreno, devicetree
On 6/8/2025 8:51 PM, Rob Clark wrote:
> On Sat, Jun 7, 2025 at 7:15 AM Akhil P Oommen <akhilpo@oss.qualcomm.com> wrote:
>>
>> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
>> version). X1-45 is a smaller version of X1-85 with lower core count and
>> smaller memories. From UMD perspective, this is similar to "FD735"
>> present in Mesa.
>>
>> Tested Glmark & Vkmark on Debian Gnome desktop.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>
> fyi, mesa part: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35404
fyi, gpu firmwares: https://lore.kernel.org/linux-firmware/e036373e-0356-4fa1-b39b-78eaf02179d6@oss.qualcomm.com/T/#u
-Akhil
>
> BR,
> -R
>
>> ---
>> Akhil P Oommen (3):
>> arm64: defconfig: Enable X1P42100_GPUCC driver
>> drm/msm/adreno: Add Adreno X1-45 support
>> arm64: dts: qcom: Add GPU support to X1P42100 SoC
>>
>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
>> arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
>> arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
>> arch/arm64/configs/defconfig | 1 +
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 38 ++++++++++
>> 5 files changed, 170 insertions(+), 1 deletion(-)
>> ---
>> base-commit: b3bded85d838336326ce78e394e7818445e11f20
>> change-id: 20250603-x1p-adreno-219da2fd4ca4
>>
>> Best regards,
>> --
>> Akhil P Oommen <akhilpo@oss.qualcomm.com>
>>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 0/3] Support for Adreno X1-45 GPU
2025-06-07 14:14 [PATCH 0/3] Support for Adreno X1-45 GPU Akhil P Oommen
` (3 preceding siblings ...)
2025-06-08 15:21 ` [PATCH 0/3] Support for Adreno X1-45 GPU Rob Clark
@ 2025-06-09 15:01 ` Rob Herring (Arm)
4 siblings, 0 replies; 19+ messages in thread
From: Rob Herring (Arm) @ 2025-06-09 15:01 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Catalin Marinas, Abhinav Kumar, Will Deacon, linux-arm-kernel,
freedreno, Konrad Dybcio, Simona Vetter, Rob Clark,
Marijn Suijten, David Airlie, Jessica Zhang, dri-devel,
Dmitry Baryshkov, Krzysztof Kozlowski, linux-arm-msm,
Conor Dooley, Sean Paul, Bjorn Andersson, linux-kernel,
devicetree
On Sat, 07 Jun 2025 19:44:58 +0530, Akhil P Oommen wrote:
> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
> version). X1-45 is a smaller version of X1-85 with lower core count and
> smaller memories. From UMD perspective, this is similar to "FD735"
> present in Mesa.
>
> Tested Glmark & Vkmark on Debian Gnome desktop.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> Akhil P Oommen (3):
> arm64: defconfig: Enable X1P42100_GPUCC driver
> drm/msm/adreno: Add Adreno X1-45 support
> arm64: dts: qcom: Add GPU support to X1P42100 SoC
>
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++
> arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
> arch/arm64/boot/dts/qcom/x1p42100.dtsi | 121 +++++++++++++++++++++++++++++-
> arch/arm64/configs/defconfig | 1 +
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 38 ++++++++++
> 5 files changed, 170 insertions(+), 1 deletion(-)
> ---
> base-commit: b3bded85d838336326ce78e394e7818445e11f20
> change-id: 20250603-x1p-adreno-219da2fd4ca4
>
> Best regards,
> --
> Akhil P Oommen <akhilpo@oss.qualcomm.com>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: using specified base-commit b3bded85d838336326ce78e394e7818445e11f20
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250607-x1p-adreno-v1-0-a8ea80f3b18b@oss.qualcomm.com:
arch/arm64/boot/dts/qcom/x1p42100-crd.dtb: opp-table (operating-points-v2-adreno): 'opp-666000000-0', 'opp-666000000-1' do not match any of the regexes: '^opp-[0-9]+$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/opp/opp-v2-qcom-adreno.yaml#
^ permalink raw reply [flat|nested] 19+ messages in thread