From mboxrd@z Thu Jan 1 00:00:00 1970 From: hdegoede@redhat.com (Hans de Goede) Date: Tue, 2 Aug 2016 10:37:46 +0200 Subject: [linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers In-Reply-To: <20160801155246.b7b3c7f0f582394b4c25f6dc@free.fr> References: <20160721085615.GG5993@lukather> <20160721112655.941b1dad04f7a5b94d4172c1@free.fr> <20160729191730.GG6215@lukather> <9414aab0-ac2b-01c2-e16b-8f7394ea7b68@redhat.com> <20160801155246.b7b3c7f0f582394b4c25f6dc@free.fr> Message-ID: <439e8a4c-1219-bb01-1be9-f1e4d77f3fcf@redhat.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, On 01-08-16 15:52, Jean-Francois Moine wrote: > On Sat, 30 Jul 2016 12:19:03 +0200 > Hans de Goede wrote: > >> Jean-Francois, can you submit a v2 of your patch and make the writing of >> SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ? >> >> Also you should probably drop the bits about the clock stuff from the >> commit message as that just seems to confuse people. > > Hi Hans, > > I submitted a new patch (sorry, I forgot the history), but it asks for > some explanation. > > - in the old timings, the phase delays are set in the clock. > That's why there is a function clk_set_phase() which is called from > the MMC side. > > - in the new timings, the delays are in the MMC register SDXC_REG_NTSR > only. > In this case, the function clk_set_phase() is of no use > (also, by test, it seems that the phase delays set by hardware > reset do work, so, there is no need to set them), but, > > - there is a bit in the clock telling that the new timings are used, > i.e. that the phase delays of the clock must be ignored. > > Not setting this bit prevents the device to work (at least in the > A83T, the H3 seems more helpful). Thanks for the explanation, it would be good to put this in the commit msg of v3 of the patch. Regards, Hans