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Fri, 4 Jul 2025 18:14:39 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v8 29/29] iommu/tegra241-cmdqv: Add IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV support Date: Fri, 4 Jul 2025 18:13:45 -0700 Message-ID: <4481e959d0b74cb7a15f4e32b830e86a7ee4e221.1751677708.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|CY5PR12MB9055:EE_ X-MS-Office365-Filtering-Correlation-Id: 04e2b17d-78da-4cc2-3007-08ddbb61588f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nzhA5bFmUyW7jTW8Le+ouTodTO5o4xPZwnJuDlQNWffgn+/ExXgOwWOXRH4J?= =?us-ascii?Q?Rby1TTVJq4+VuO3APN3E7W/CR4GUQr6GZTWPolO5eTlrdfU9TqZzqT6osacV?= =?us-ascii?Q?XAL1JGt8UKb6N5lsyjiz6hlzCfkEjrwhgp4kVkTstRLUCd4eaG41DJl6pgAq?= =?us-ascii?Q?j3eaN/7ETdZ+Iw8HI3AZSMohOCNFdgJxuzvcoVQXrj59JBpqAkt6pATLzDbz?= =?us-ascii?Q?R4del9cpInjd/szvWNGjoKqp9+ipzU+eo9NHG1hGCqSPh4fNnPjWa6GxNmLo?= =?us-ascii?Q?L30IwK4buDgccseOuqaoHJohoyoMJsyh4t+1W4QQA1nDoeROM+tL185UKHAJ?= =?us-ascii?Q?JTNkkJRpQhj0sdB3ny/QnMz/tkUaTBnFk4mRATx4kSUmvKPerIhRjBs1b0Vh?= =?us-ascii?Q?BiOTulHEtDPQCYRkjKeTAMGKImAvVxSM/vQNogambkzffr+0vjNcgkTUBFUA?= =?us-ascii?Q?6IBV2xcjhwjFcp/gU8qDkf/R2EE74mb3tyTKh2sLUiHA4OqXyRcw5P+DT4Uq?= =?us-ascii?Q?gJIfgLM0Z5JmfRT9MAqMD0nWVpYENVWMzPID02+kRUElm8yCn/7YXMKXrPt4?= =?us-ascii?Q?s12x4ROCMGxQ4XkYtacgDVzmAlJJG5MS+JI3PSI5g5/BcofQTjVv9bKsEIa5?= =?us-ascii?Q?Ma4qRjXfNX1mLOcUxiBvMfZmvClEO/iyb9lM8RBb19rTL9sDHQ9YD9ePrq9w?= =?us-ascii?Q?rrnUw3JvTfV8DDol/HXTkhCZjEUjl3mZKgBF/kbmyvtRL2+JNtOkEvhj0csK?= =?us-ascii?Q?HmgcdBRpoAZk19R1Ieq5VUs3JMxkRs8L8TMLYauDaqzKZQkyLXgwQB6IY4Uj?= =?us-ascii?Q?db7wAC2eQ2jLHqaoVUtAl28a6mqVdYqxPyKdQ0pNKgUxlamDQCEDJ/ymEFQf?= =?us-ascii?Q?JQcpdjnDiHo3usd/LzDxsxa8yjByFTsiGOvPPIJpuAGL1WQOJ1+pPOTgmLB2?= =?us-ascii?Q?wtHOKgsVqSuzSGUz7b3y05HrMfXg5pNy9BRSSBJbS0SjboLynS1qCQQdvmXB?= =?us-ascii?Q?o7cnHMBpLYWm76S49iXPDmimkDg35pBd+pEqmXpHXSWKClpUEmZ0whZAs2hu?= =?us-ascii?Q?MVBOEJoM6exXwqvdfrZ9xBPMwBdzCcN+E1sLDTm04NJokKqqHeHxFf+whbY5?= =?us-ascii?Q?dNElzk7U9mz1eTIaaYb3O0eJS7MNmm/0Ag2mtAD9mmtPDBmZzRcwnqQLe0nY?= =?us-ascii?Q?jc2bTPOlW4L6OFTlkfWa6+31vt2JlwGHB5PlQodZy/6oFLbReO9/8p0omoSu?= =?us-ascii?Q?D/vRSlLF6KZ5B67EqtOKIznY2dviJXMYwL5v1/SfHY1ymuTuNrR3tGtkl91R?= =?us-ascii?Q?0ZlN1wu1GKVXOxyFAw72yUBui9e5hJRJzCN9dxDPInw5XrOmNEcwtzZRbkRF?= =?us-ascii?Q?nJMZsIiqwaaU2muYR5MO7NN/9vgdYFwzEIoQ3NWRbSi5NNBPmzznvizoAIC4?= =?us-ascii?Q?KSr4HPrAm/ux88f7lUv7pwBi2e+6bOvhxnJTRVbLdTvKkKyxyhy3LKIcO4Lc?= =?us-ascii?Q?EOFFAg7mRy0RCh3Id03nscISu/Hju3YLQuRk?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2025 01:14:52.7322 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04e2b17d-78da-4cc2-3007-08ddbb61588f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB9055 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250704_181457_547182_0563C48D X-CRM114-Status: GOOD ( 13.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a new vEVENTQ type for VINTFs that are assigned to the user space. Simply report the two 64-bit LVCMDQ_ERR_MAPs register values. Reviewed-by: Alok Tiwari Reviewed-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/uapi/linux/iommufd.h | 15 +++++++++++++ .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 22 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 4e81610390c7..111ea81f91a2 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1145,10 +1145,12 @@ struct iommufd_vevent_header { * enum iommu_veventq_type - Virtual Event Queue Type * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue + * @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ */ enum iommu_veventq_type { IOMMU_VEVENTQ_TYPE_DEFAULT = 0, IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2, }; /** @@ -1172,6 +1174,19 @@ struct iommu_vevent_arm_smmuv3 { __aligned_le64 evt[4]; }; +/** + * struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV IRQ + * (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV) + * @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian. + * (Refer to register LVCMDQ_ERR_MAPs per VINTF ) + * + * The 128-bit register value from HW exclusively reflect the error bits for a + * Virtual Interface represented by a vIOMMU object. Read and report directly. + */ +struct iommu_vevent_tegra241_cmdqv { + __aligned_le64 lvcmdq_err_map[2]; +}; + /** * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) * @size: sizeof(struct iommu_veventq_alloc) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 3eeb8444fadf..d5d43a1c7708 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -295,6 +295,20 @@ static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval) /* ISR Functions */ +static void tegra241_vintf_user_handle_error(struct tegra241_vintf *vintf) +{ + struct iommufd_viommu *viommu = &vintf->vsmmu.core; + struct iommu_vevent_tegra241_cmdqv vevent_data; + int i; + + for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) + vevent_data.lvcmdq_err_map[i] = + readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); + + iommufd_viommu_report_event(viommu, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + &vevent_data, sizeof(vevent_data)); +} + static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) { int i; @@ -340,6 +354,14 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) vintf_map &= ~BIT_ULL(0); } + /* Handle other user VINTFs and their LVCMDQs */ + while (vintf_map) { + unsigned long idx = __ffs64(vintf_map); + + tegra241_vintf_user_handle_error(cmdqv->vintfs[idx]); + vintf_map &= ~BIT_ULL(idx); + } + return IRQ_HANDLED; } -- 2.43.0