From mboxrd@z Thu Jan 1 00:00:00 1970 From: michal.simek@xilinx.com (Michal Simek) Date: Wed, 12 Mar 2014 07:01:38 +0100 Subject: [PATCH v2 7/7] ARM: zynq: DT: Migrate UART to Cadence binding In-Reply-To: <20140311154847.GI13293@xsjandreislx> References: <1394487610-2419-1-git-send-email-soren.brinkmann@xilinx.com> <1394487610-2419-8-git-send-email-soren.brinkmann@xilinx.com> <62cd32ad-8743-4d49-a1b6-c178054a9756@CO9EHSMHS011.ehs.local> <20140311154847.GI13293@xsjandreislx> Message-ID: <44c9eddf-9f61-4219-8564-a3019dc0fd87@AM1EHSMHS021.ehs.local> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 03/11/2014 04:48 PM, S?ren Brinkmann wrote: > On Tue, 2014-03-11 at 09:52AM +0100, Michal Simek wrote: >> On 03/10/2014 10:40 PM, Soren Brinkmann wrote: >>> The Zynq UART is Cadence IP and the driver has been renamed accordingly. >>> Migrate the DT to use the new binding for the UART driver. >>> >>> Signed-off-by: Soren Brinkmann >>> Acked-by: Peter Crosthwaite >>> Acked-by: Rob Herring >>> --- >>> This change depends on 'tty: xuartps: Rebrand driver as Cadence UART', >>> which introduces the new clock-names. >>> --- >>> arch/arm/boot/dts/zynq-7000.dtsi | 8 ++++---- >>> 1 file changed, 4 insertions(+), 4 deletions(-) >>> >>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi >>> index 8b67b19392ec..0ed0d4b0579a 100644 >>> --- a/arch/arm/boot/dts/zynq-7000.dtsi >>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi >>> @@ -67,19 +67,19 @@ >>> }; >>> >>> uart0: uart at e0000000 { >>> - compatible = "xlnx,xuartps"; >>> + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; >>> status = "disabled"; >>> clocks = <&clkc 23>, <&clkc 40>; >>> - clock-names = "ref_clk", "aper_clk"; >>> + clock-names = "uart_clk", "pclk"; >>> reg = <0xE0000000 0x1000>; >>> interrupts = <0 27 4>; >>> }; >>> >>> uart1: uart at e0001000 { >>> - compatible = "xlnx,xuartps"; >>> + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; >>> status = "disabled"; >>> clocks = <&clkc 24>, <&clkc 41>; >>> - clock-names = "ref_clk", "aper_clk"; >>> + clock-names = "uart_clk", "pclk"; >>> reg = <0xE0001000 0x1000>; >>> interrupts = <0 50 4>; >>> }; >> >> This should be at least the part of 5/7 because between 5/7 and 7/7 >> driver will fail to probe. > > The driver should never fail to probe. The old bindings will continue to > work. So, only dependency for this is, the new clock names must be > merged in. So, it has to be rather late in the series. We discussed this over phone and yes, I have missed that. Thanks, Michal