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From: "Heiko Stübner" <heiko@sntech.de>
To: linux-rockchip@lists.infradead.org,
	Diederik de Haas <didi.debian@cknow.org>
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: rockchip: add rock5 itx board
Date: Thu, 04 Jul 2024 12:05:10 +0200	[thread overview]
Message-ID: <4552794.8F6SAcFxjW@diego> (raw)
In-Reply-To: <2278169.QnsP76Vvrg@bagend>

Hi Diederik,

Am Donnerstag, 4. Juli 2024, 11:38:51 CEST schrieb Diederik de Haas:
> Thanks for submitting this. A quick scan indicates it should work with a 
> (recent) Debian kernel OOTB :-)
> 
> On Wednesday, 3 July 2024 23:05:24 CEST Heiko Stuebner wrote:
> > +&sdhci {
> > +       bus-width = <8>;
> > +       no-sdio;
> > +       no-sd;
> > +       non-removable;
> > +       max-frequency = <200000000>;
> > +       mmc-hs400-1_8v;
> > +       mmc-hs400-enhanced-strobe;
> > +       mmc-hs200-1_8v;
> > +       status = "okay";
> > +};
> > +
> > +&sdmmc {
> > +       max-frequency = <200000000>;
> > +       no-sdio;
> > +       no-mmc;
> > +       bus-width = <4>;
> > +       cap-mmc-highspeed;
> > +       cap-sd-highspeed;
> > +       disable-wp;
> > +       sd-uhs-sdr104;
> > +       vmmc-supply = <&vcc_3v3_s3>;
> > +       vqmmc-supply = <&vccio_sd_s0>;
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
> > +       status = "okay";
> > +};
> > +
> > +/* M.2 E-KEY */
> > +&sdio {
> > +       broken-cd;
> > +       bus-width = <4>;
> > +       cap-sdio-irq;
> > +       disable-wp;
> > +       keep-power-in-suspend;
> > +       max-frequency = <150000000>;
> > +       mmc-pwrseq = <&sdio_pwrseq>;
> > +       no-sd;
> > +       no-mmc;
> > +       non-removable;
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&sdiom0_pins>;
> > +       sd-uhs-sdr104;
> > +       vmmc-supply = <&vcc3v3_ekey>;
> > +       status = "okay";
> > +};
> > +
> > +&sfc {
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&fspim2_pins>;
> > +       status = "okay";
> 
> Shouldn't those properties be sorted alphabetically? Or at least consistently?
> Note that the same issue is present on other places too, but I believe the 
> above quoted part shows the issue enough.

The main sorting is
- compatible
- reg
[... alphabetically ...]
- status

But now that I look at it, you're right there are some non-alphabetical
shenanigans going on there in the sdmmc and sdhci nodes ;-)

Heiko




  reply	other threads:[~2024-07-04 10:05 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-03 21:05 [PATCH 0/2] Rock 5 ITX devicetree Heiko Stuebner
2024-07-03 21:05 ` [PATCH 1/2] dt-bindings: arm: rockchip: Add Rock 5 ITX board Heiko Stuebner
2024-07-03 21:11   ` Dragan Simic
2024-07-04  6:26   ` Krzysztof Kozlowski
2024-07-03 21:05 ` [PATCH 2/2] arm64: dts: rockchip: add rock5 itx board Heiko Stuebner
2024-07-03 21:16   ` Dragan Simic
2024-07-04  6:28   ` Krzysztof Kozlowski
2024-07-04  9:38   ` Diederik de Haas
2024-07-04 10:05     ` Heiko Stübner [this message]
2024-07-04 11:43       ` Alex Bee
2024-07-04 12:05         ` Heiko Stübner
2024-07-04 13:04           ` Alex Bee
2024-07-04 10:52   ` Alex Bee
2024-07-04 11:21     ` Heiko Stübner
2024-07-04 12:04     ` Dragan Simic

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