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Tue, 07 Jan 2025 06:51:24 -0800 (PST) Received: from smtpclient.apple ([131.111.5.201]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436612008b1sm595570305e9.15.2025.01.07.06.51.23 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Jan 2025 06:51:23 -0800 (PST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3826.300.87.4.3\)) Subject: Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities From: Jessica Clarke In-Reply-To: Date: Tue, 7 Jan 2025 14:51:12 +0000 Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linus Walleij , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King Content-Transfer-Encoding: quoted-printable Message-Id: <45E38F12-3585-4AE0-8F05-431DB355FC69@jrtc27.com> References: <20250103181623.1980433-1-vincenzo.frascino@arm.com> <20250103181623.1980433-3-vincenzo.frascino@arm.com> To: Vincenzo Frascino X-Mailer: Apple Mail (2.3826.300.87.4.3) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250107_065126_519142_F76DF4BC X-CRM114-Status: GOOD ( 25.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7 Jan 2025, at 14:34, Vincenzo Frascino = wrote: >=20 > Hi Jessica, >=20 > Thank you for your review. >=20 > On 07/01/2025 12:56, Jessica Clarke wrote: >> On Fri, Jan 03, 2025 at 04:14:31PM -0600, Rob Herring wrote: >>> On Fri, Jan 3, 2025 at 12:16=E2=80=AFPM Vincenzo Frascino >>> wrote: >>>> + cpus { >>>> + #address-cells =3D <2>; >>>> + #size-cells =3D <0>; >>>> + >>>> + cpu0: cpu@0 { >>>> + compatible =3D "arm,neoverse-n1"; >>>=20 >>> I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps >>> "arm,neoverse-n1-morello" if we want to capture what it is derived >>> from and since "arm,morello" is taken already. >>=20 >> Rainier is the codename of the core itself, and Morello LLVM = recognises >> -mcpu=3Drainier not -mcpu=3Dmorello (there's -march=3Dmorello = instead), so >> perhaps it should really be "arm,rainier". Though SMBIOS reports it = as >> Morello-R0P1 so it may be best to use "arm,morello" here. >>=20 >=20 > We agree on the concept. It should either be "arm,rainier" or = "arm,morello-r0p1" r0p1 isn=E2=80=99t right. Boards with r0p0 and r0p2 CPUs also exist = (although the former are now only within Arm, but the latter are in the wild in limited numbers, including a couple here at Cambridge). > if we want to capture the information of SMBIOS. When we reach = consensus I will > update the patches accordingly (Please have a look at my reply to = Rob). >=20 >> The real problem is that the board compatible has changed to include = a >> generic "arm,morello" node, with the argument that a v2 board could >> appear. So why not instead change *that* to be something like: >>=20 >> compatible =3D "arm,morello-sdp-v1", "arm,morello-sdp"; >>=20 >> Then you can use "arm,morello" here for the cores.> >=20 > The name morello on its own is too overloaded of meaning if we do not = specify to > what we are referring to. >=20 >> Though some of this may depend on what the FVP's DTS looks like; is = it >> going to claim to be a Morello SDP, or does there need to be a common >> denominator compatible beneath that it can use? >>=20 >=20 > I still did not start bringing up to speed the DTS for FVP but I think = that we > should distinguish in between SDP and FVP since not everything is the = same, > hence it should have something similar to: >=20 > compatible =3D "arm,morello-fvp", "arm,morello"; >=20 >> Please CC me on future versions of this series. >>=20 >=20 > Will do. >=20 >> Jess >=20 > --=20 > Regards, > Vincenzo