[PATCH v2 0/4] Fix USB controller support for RK3368

[PATCH v2 0/4] Fix USB controller support for RK3368

[WeiHao Li]

This series fixs USB controller support for the Rockchip RK3368 SoC.

Key changes:
 - Update phy-rockchip-inno-usb2 driver to preperly handle RK3368 usb
   phy initialization and configuration.
 - Add usb PHY node to rk3368.dtsi with correct clocks and register
   mapping.
 - Add missing OHCI node, add missing attribute for usb host node.
 - Add dt-bindings document.

The following changes since v1:
 - Remove the duplicate structure member I accidentally added.

These changes were tested on a RK3368-based board [1]. Both of USB ports
can emumerate device (HID and mass storage).

Main code changes come from the rockchip downstream source [2].

[1] https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368
[2] https://github.com/rockchip-linux/kernel

Tested-by: WeiHao Li <cn.liweihao@gmail.com>
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>

WeiHao Li (4):
  phy: rockchip: inno-usb2: Add usb2 phy support for RK3368
  arm64: dts: rockchip: Add USB2.0 PHY for RK3368
  dt-bindings: phy: rockchip,inno-usb2phy: Document rk3368 usb phy
  arm64: dts: rockchip: Add phys attribute of USB host node for RK3368

 .../bindings/phy/rockchip,inno-usb2phy.yaml   |  2 +
 arch/arm64/boot/dts/rockchip/rk3368.dtsi      | 47 +++++++++++++++++-
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 48 +++++++++++++++++++
 3 files changed, 95 insertions(+), 2 deletions(-)

-- 
2.47.2

[PATCH v2 1/4] phy: rockchip: inno-usb2: Add usb2 phy support for RK3368

[WeiHao Li]

RK3368 has one USB2.0 PHY with two ports. This adds device specific data
for it. Device specific data get form rockchip downstream source [1].

[1] https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/phy/rockchip/phy-rockchip-inno-usb2.c#L2805

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index b0f23690ec..df574337d4 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1847,6 +1847,53 @@ static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
 	{ /* sentinel */ }
 };
 
+static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = {
+	{
+		.reg = 0x700,
+		.num_ports	= 2,
+		.clkout_ctl	= { 0x0724, 15, 15, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0700, 8, 0, 0, 0x1d1 },
+				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
+				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
+				.bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
+				.idfall_det_en	= { 0x0680, 6, 6, 0, 1 },
+				.idfall_det_st	= { 0x0690, 6, 6, 0, 1 },
+				.idfall_det_clr	= { 0x06a0, 6, 6, 0, 1 },
+				.idrise_det_en	= { 0x0680, 5, 5, 0, 1 },
+				.idrise_det_st	= { 0x0690, 5, 5, 0, 1 },
+				.idrise_det_clr	= { 0x06a0, 5, 5, 0, 1 },
+				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
+				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
+				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
+				.utmi_bvalid	= { 0x04bc, 23, 23, 0, 1 },
+				.utmi_id	= { 0x04bc, 26, 26, 0, 1 },
+				.utmi_ls	= { 0x04bc, 25, 24, 0, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x0728, 8, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
+				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
+				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
+			}
+		},
+		.chg_det = {
+			.opmode		= { 0x0700, 8, 0, 0, 0x1d7 },
+			.cp_det		= { 0x04b8, 30, 30, 0, 1 },
+			.dcp_det	= { 0x04b8, 29, 29, 0, 1 },
+			.dp_det		= { 0x04b8, 31, 31, 0, 1 },
+			.idm_sink_en	= { 0x0718, 8, 8, 0, 1 },
+			.idp_sink_en	= { 0x0718, 7, 7, 0, 1 },
+			.idp_src_en	= { 0x0718, 9, 9, 0, 1 },
+			.rdm_pdwn_en	= { 0x0718, 10, 10, 0, 1 },
+			.vdm_src_en	= { 0x0718, 12, 12, 0, 1 },
+			.vdp_src_en	= { 0x0718, 11, 11, 0, 1 },
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
 	{
 		.reg		= 0xe450,
@@ -2289,6 +2336,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = {
 	{ .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
 	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
+	{ .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs },
 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
 	{ .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs },
 	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
-- 
2.47.2

[PATCH v2 2/4] arm64: dts: rockchip: Add USB2.0 PHY for RK3368

[WeiHao Li]

RK3368 has one USB2.0 PHY with two ports, This adds device tree node for
it.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 29 ++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 1b21787269..b09e431a64 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -766,11 +766,40 @@ cru: clock-controller@ff760000 {
 	grf: syscon@ff770000 {
 		compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xff770000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
 
 		io_domains: io-domains {
 			compatible = "rockchip,rk3368-io-voltage-domain";
 			status = "disabled";
 		};
+
+		u2phy: usb2-phy@700 {
+			compatible = "rockchip,rk3368-usb2phy";
+			reg = <0x700 0x2c>;
+			clocks = <&cru SCLK_OTGPHY0>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy";
+			#clock-cells = <0>;
+			status = "disabled";
+
+			u2phy_otg: otg-port {
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "otg-bvalid", "otg-id",
+						  "linestate";
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
+			u2phy_host: host-port {
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
 	};
 
 	wdt: watchdog@ff800000 {
-- 
2.47.2

[PATCH v2 3/4] dt-bindings: phy: rockchip,inno-usb2phy: Document rk3368 usb phy

[WeiHao Li]

Add compatible for the USB2 phy in the Rockchip RK3368 SoC.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 .../devicetree/bindings/phy/rockchip,inno-usb2phy.yaml          | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
index 58e735b5dd..6e3197c168 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
@@ -19,6 +19,7 @@ properties:
       - rockchip,rk3308-usb2phy
       - rockchip,rk3328-usb2phy
       - rockchip,rk3366-usb2phy
+      - rockchip,rk3368-usb2phy
       - rockchip,rk3399-usb2phy
       - rockchip,rk3562-usb2phy
       - rockchip,rk3568-usb2phy
@@ -192,6 +193,7 @@ allOf:
               - rockchip,rk3308-usb2phy
               - rockchip,rk3328-usb2phy
               - rockchip,rk3366-usb2phy
+              - rockchip,rk3368-usb2phy
               - rockchip,rk3399-usb2phy
               - rockchip,rk3562-usb2phy
               - rockchip,rk3568-usb2phy
-- 
2.47.2

[PATCH v2 4/4] arm64: dts: rockchip: Add phys attribute of USB host node for RK3368

[WeiHao Li]

RK3368 has a USB host controller and a OTG controller, both of them use
a extra phy, this add missing ohci node and add phys attribute for them.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index b09e431a64..cdcbc0a944 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -503,9 +503,21 @@ gmac: ethernet@ff290000 {
 
 	usb_host0_ehci: usb@ff500000 {
 		compatible = "generic-ehci";
-		reg = <0x0 0xff500000 0x0 0x100>;
+		reg = <0x0 0xff500000 0x0 0x20000>;
 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_HOST0>;
+		clocks = <&cru HCLK_HOST0>, <&u2phy>;
+		phys = <&u2phy_host>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_host0_ohci: usb@ff520000 {
+		compatible = "generic-ohci";
+		reg = <0x0 0xff520000 0x0 0x20000>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST0>, <&u2phy>;
+		phys = <&u2phy_host>;
+		phy-names = "usb";
 		status = "disabled";
 	};
 
@@ -520,6 +532,8 @@ usb_otg: usb@ff580000 {
 		g-np-tx-fifo-size = <16>;
 		g-rx-fifo-size = <275>;
 		g-tx-fifo-size = <256 128 128 64 64 32>;
+		phys = <&u2phy_otg>;
+		phy-names = "usb2-phy";
 		status = "disabled";
 	};
 
-- 
2.47.2

Re: [PATCH v2 1/4] phy: rockchip: inno-usb2: Add usb2 phy support for RK3368

[Heiko Stübner]

Am Dienstag, 9. September 2025, 15:29:55 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> RK3368 has one USB2.0 PHY with two ports. This adds device specific data
> for it. Device specific data get form rockchip downstream source [1].
> 
> [1] https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/phy/rockchip/phy-rockchip-inno-usb2.c#L2805
> 
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>

compared the register values to the TRM

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
>  drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 48 +++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> index b0f23690ec..df574337d4 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> @@ -1847,6 +1847,53 @@ static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
>  	{ /* sentinel */ }
>  };
>  
> +static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = {
> +	{
> +		.reg = 0x700,
> +		.num_ports	= 2,
> +		.clkout_ctl	= { 0x0724, 15, 15, 1, 0 },
> +		.port_cfgs	= {
> +			[USB2PHY_PORT_OTG] = {
> +				.phy_sus	= { 0x0700, 8, 0, 0, 0x1d1 },
> +				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
> +				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
> +				.bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
> +				.idfall_det_en	= { 0x0680, 6, 6, 0, 1 },
> +				.idfall_det_st	= { 0x0690, 6, 6, 0, 1 },
> +				.idfall_det_clr	= { 0x06a0, 6, 6, 0, 1 },
> +				.idrise_det_en	= { 0x0680, 5, 5, 0, 1 },
> +				.idrise_det_st	= { 0x0690, 5, 5, 0, 1 },
> +				.idrise_det_clr	= { 0x06a0, 5, 5, 0, 1 },
> +				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
> +				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
> +				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
> +				.utmi_bvalid	= { 0x04bc, 23, 23, 0, 1 },
> +				.utmi_id	= { 0x04bc, 26, 26, 0, 1 },
> +				.utmi_ls	= { 0x04bc, 25, 24, 0, 1 },
> +			},
> +			[USB2PHY_PORT_HOST] = {
> +				.phy_sus	= { 0x0728, 8, 0, 0, 0x1d1 },
> +				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
> +				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
> +				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
> +			}
> +		},
> +		.chg_det = {
> +			.opmode		= { 0x0700, 8, 0, 0, 0x1d7 },
> +			.cp_det		= { 0x04b8, 30, 30, 0, 1 },
> +			.dcp_det	= { 0x04b8, 29, 29, 0, 1 },
> +			.dp_det		= { 0x04b8, 31, 31, 0, 1 },
> +			.idm_sink_en	= { 0x0718, 8, 8, 0, 1 },
> +			.idp_sink_en	= { 0x0718, 7, 7, 0, 1 },
> +			.idp_src_en	= { 0x0718, 9, 9, 0, 1 },
> +			.rdm_pdwn_en	= { 0x0718, 10, 10, 0, 1 },
> +			.vdm_src_en	= { 0x0718, 12, 12, 0, 1 },
> +			.vdp_src_en	= { 0x0718, 11, 11, 0, 1 },
> +		},
> +	},
> +	{ /* sentinel */ }
> +};
> +
>  static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
>  	{
>  		.reg		= 0xe450,
> @@ -2289,6 +2336,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = {
>  	{ .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
>  	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
>  	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
> +	{ .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs },
>  	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
>  	{ .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs },
>  	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
> 

Re: [PATCH v2 2/4] arm64: dts: rockchip: Add USB2.0 PHY for RK3368

[Vladimir Oltean]

On Tue, Sep 09, 2025 at 09:29:56PM +0800, WeiHao Li wrote:
> RK3368 has one USB2.0 PHY with two ports, This adds device tree node for
> it.
> 
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3368.dtsi | 29 ++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> index 1b21787269..b09e431a64 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> @@ -766,11 +766,40 @@ cru: clock-controller@ff760000 {
>  	grf: syscon@ff770000 {
>  		compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
>  		reg = <0x0 0xff770000 0x0 0x1000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;

This introduces a device tree warning. You cannot mix nodes with no unit
address (io-domains) with nodes with a unit address (usb2-phy@700) on
the same hierarchical level. You have to pick a format and stick to it.

>  
>  		io_domains: io-domains {
>  			compatible = "rockchip,rk3368-io-voltage-domain";
>  			status = "disabled";
>  		};
> +
> +		u2phy: usb2-phy@700 {
> +			compatible = "rockchip,rk3368-usb2phy";
> +			reg = <0x700 0x2c>;
> +			clocks = <&cru SCLK_OTGPHY0>;
> +			clock-names = "phyclk";
> +			clock-output-names = "usb480m_phy";
> +			#clock-cells = <0>;
> +			status = "disabled";
> +
> +			u2phy_otg: otg-port {
> +				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "otg-bvalid", "otg-id",
> +						  "linestate";
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			u2phy_host: host-port {
> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "linestate";
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
>  	};
>  
>  	wdt: watchdog@ff800000 {
> -- 
> 2.47.2
> 
> 

Re: [PATCH v2 2/4] arm64: dts: rockchip: Add USB2.0 PHY for RK3368

[Johan Jonker]

On 2/12/26 17:55, Vladimir Oltean wrote:
> On Tue, Sep 09, 2025 at 09:29:56PM +0800, WeiHao Li wrote:
>> RK3368 has one USB2.0 PHY with two ports, This adds device tree node for
>> it.
>>
>> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
>> ---
>>  arch/arm64/boot/dts/rockchip/rk3368.dtsi | 29 ++++++++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
>> index 1b21787269..b09e431a64 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
>> @@ -766,11 +766,40 @@ cru: clock-controller@ff760000 {
>>  	grf: syscon@ff770000 {
>>  		compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
>>  		reg = <0x0 0xff770000 0x0 0x1000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
> 

> This introduces a device tree warning. You cannot mix nodes with no unit
> address (io-domains) with nodes with a unit address (usb2-phy@700) on
> the same hierarchical level. You have to pick a format and stick to it.

nope

Please add rockchip,rk3368-usb2phy to the list in grf.yaml in the same patch that you change rockchip,inno-usb2phy.yaml
Requires a bit of SOC and PHY maintainers coordination.

Place dt-binding compatible change patches before the patch that uses it. (patch 3 before patch 1)
due to: ./scripts/checkpatch.pl --strict 

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/soc/rockchip/grf.yaml#n244

> 
>>  
>>  		io_domains: io-domains {
>>  			compatible = "rockchip,rk3368-io-voltage-domain";
>>  			status = "disabled";
>>  		};
>> +
>> +		u2phy: usb2-phy@700 {
>> +			compatible = "rockchip,rk3368-usb2phy";
>> +			reg = <0x700 0x2c>;
>> +			clocks = <&cru SCLK_OTGPHY0>;
>> +			clock-names = "phyclk";
>> +			clock-output-names = "usb480m_phy";
>> +			#clock-cells = <0>;
>> +			status = "disabled";
>> +
>> +			u2phy_otg: otg-port {
>> +				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> +				interrupt-names = "otg-bvalid", "otg-id",
>> +						  "linestate";
>> +				#phy-cells = <0>;
>> +				status = "disabled";
>> +			};
>> +
>> +			u2phy_host: host-port {
>> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> +				interrupt-names = "linestate";
>> +				#phy-cells = <0>;
>> +				status = "disabled";
>> +			};
>> +		};
>>  	};
>>  
>>  	wdt: watchdog@ff800000 {
>> -- 
>> 2.47.2
>>
>>
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
> 

Re: [PATCH v2 1/4] phy: rockchip: inno-usb2: Add usb2 phy support for RK3368

[Heiko Stübner]

Hi,

Am Dienstag, 9. September 2025, 15:29:55 Mitteleuropäische Normalzeit schrieb WeiHao Li:
> RK3368 has one USB2.0 PHY with two ports. This adds device specific data
> for it. Device specific data get form rockchip downstream source [1].
> 
> [1] https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/phy/rockchip/phy-rockchip-inno-usb2.c#L2805
> 
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>

just realized, this patch is missing the phy maintainer/reviewer as
recipient, the phy-list is likely not enough.

Please use scripts/get_maintainer.pl for the whole series, to get necessary
people. Because this phy-patch needs to go through the phy tree.

Thanks
Heiko