[PATCH v3 0/6] Introduce ASPEED AST27XX BMC SoC

[PATCH v3 0/6] Introduce ASPEED AST27XX BMC SoC

[Kevin Chen]

---
v3:
  - Split clk and reset driver to other commits, which are in series of
    "Add support for AST2700 clk driver".
  - For BMC console by UART12, add uart12 using ASPEED INTC architecture.

aspeed,ast2700-intc.yaml
  - Add minItems to 1 to fix the warning by "make dtbs_check W=1".
  - Add intc1 into example.

Kconfig.platforms
  - Remove MACH_ASPEED_G7.

Kevin Chen (6):
  dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.
  dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC
  arm64: aspeed: Add support for ASPEED AST27XX BMC SoC
  arm64: dts: aspeed: Add initial AST27XX device tree
  arm64: dts: aspeed: Add initial AST2700 EVB device tree
  arm64: defconfig: Add ASPEED AST2700 family support

 .../bindings/arm/aspeed/aspeed.yaml           |   6 +
 .../aspeed,ast2700-intc.yaml                  |  60 ++++-
 MAINTAINERS                                   |   1 +
 arch/arm64/Kconfig.platforms                  |   6 +
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/aspeed/Makefile           |   4 +
 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     | 236 ++++++++++++++++++
 arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |  57 +++++
 arch/arm64/configs/defconfig                  |   1 +
 9 files changed, 359 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
 create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
 create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts

-- 
2.34.1

[PATCH v3 1/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC

[Kevin Chen]

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index 2f92b8ab08fa..600424929df9 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -8,6 +8,7 @@ title: Aspeed SoC based boards
 
 maintainers:
   - Joel Stanley <joel@jms.id.au>
+  - Kevin Chen <kevin_chen@aspeedtech.com>
 
 properties:
   $nodename:
@@ -101,4 +102,10 @@ properties:
               - ufispace,ncplite-bmc
           - const: aspeed,ast2600
 
+      - description: AST2700 based boards
+        items:
+          - enum:
+              - aspeed,ast2700-evb
+          - const: aspeed,ast2700
+
 additionalProperties: true
-- 
2.34.1

[PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.

[Kevin Chen]

1. Because size-cells is no need to use 2, modify to 1 for use.
2. Add minItems to 1 for interrupts for intc1.
3. Add 1 interrupt of intc1 example into yaml file.
4. Add intc1 sub-module of uart12 as example using the intc0 and intc1.
---
 .../aspeed,ast2700-intc.yaml                  | 60 +++++++++++++++----
 1 file changed, 47 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
index 55636d06a674..eadfbc45326b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
@@ -31,6 +31,7 @@ properties:
       type as defined in interrupt.txt in this directory.
 
   interrupts:
+    minItems: 1
     maxItems: 6
     description: |
       Depend to which INTC0 or INTC1 used.
@@ -68,19 +69,52 @@ examples:
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
     bus {
+      #address-cells = <2>;
+      #size-cells = <1>;
+
+      intc0: interrupt-controller@12100000 {
+        compatible = "simple-mfd";
+        reg = <0 0x12100000 0x4000>;
+        ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
         #address-cells = <2>;
-        #size-cells = <2>;
-
-        interrupt-controller@12101b00 {
-            compatible = "aspeed,ast2700-intc-ic";
-            reg = <0 0x12101b00 0 0x10>;
-            #interrupt-cells = <2>;
-            interrupt-controller;
-            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+        #size-cells = <1>;
+
+        intc0_11: interrupt-controller@1b00 {
+          compatible = "aspeed,ast2700-intc-ic";
+          reg = <0 0x12101b00 0x10>;
+          #interrupt-cells = <2>;
+          interrupt-controller;
+          interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                       <GIC_SPI 193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                       <GIC_SPI 194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                       <GIC_SPI 195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                       <GIC_SPI 196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                       <GIC_SPI 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
         };
+      };
+
+      intc1: interrupt-controller@14c18000 {
+        compatible = "simple-mfd";
+        reg = <0 0x14c18000 0x400>;
+        ranges = <0x0 0x0 0x0 0x14c18000 0x400>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+
+        intc1_4: interrupt-controller@140 {
+          compatible = "aspeed,ast2700-intc-ic";
+          reg = <0x0 0x140 0x10>;
+          #interrupt-cells = <2>;
+          interrupt-controller;
+          interrupts-extended = <&intc0_11 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
+      };
+
+      uart12: serial@14c33b00 {
+        compatible = "ns16550a";
+        reg = <0x0 0x14c33b00 0x100>;
+        interrupts-extended = <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        reg-shift = <2>;
+        reg-io-width = <4>;
+        no-loopback-test;
+      };
     };
-- 
2.34.1

[PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC

[Kevin Chen]

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index 2f92b8ab08fa..20191fee1f5b 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -101,4 +101,10 @@ properties:
               - ufispace,ncplite-bmc
           - const: aspeed,ast2600
 
+      - description: AST2700 based boards
+        items:
+          - enum:
+              - aspeed,ast2700-evb
+          - const: aspeed,ast2700
+
 additionalProperties: true
-- 
2.34.1

[PATCH v3 2/6] dt-bindings: interrupt-controller: Fix the size-cells in ast2700-intc

[Kevin Chen]

It is no need to let size-cells to 2 for the ASPEED AST27XX INTC. Modify
the ast2700-intc example usage.

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 .../bindings/interrupt-controller/aspeed,ast2700-intc.yaml    | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
index 55636d06a674..69503aa638fb 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
@@ -69,11 +69,11 @@ examples:
 
     bus {
         #address-cells = <2>;
-        #size-cells = <2>;
+        #size-cells = <1>;
 
         interrupt-controller@12101b00 {
             compatible = "aspeed,ast2700-intc-ic";
-            reg = <0 0x12101b00 0 0x10>;
+            reg = <0 0x12101b00 0x10>;
             #interrupt-cells = <2>;
             interrupt-controller;
             interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.34.1

[PATCH v3 3/6] arm64: aspeed: Add support for ASPEED AST27XX BMC SoC

[Kevin Chen]

Add ARCH_ASPEED in current arm64 architecture.

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 MAINTAINERS                  | 1 +
 arch/arm64/Kconfig.platforms | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 17daa9ee9384..c6d04cea43d6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2261,6 +2261,7 @@ Q:	https://patchwork.ozlabs.org/project/linux-aspeed/list/
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc.git
 F:	Documentation/devicetree/bindings/arm/aspeed/
 F:	arch/arm/boot/dts/aspeed/
+F:	arch/arm64/boot/dts/aspeed/
 F:	arch/arm/mach-aspeed/
 N:	aspeed
 
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 370a9d2b6919..894b80434776 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -40,6 +40,12 @@ config ARCH_APPLE
 	  This enables support for Apple's in-house ARM SoC family, such
 	  as the Apple M1.
 
+config ARCH_ASPEED
+	bool "Aspeed SoC family"
+	help
+	  Say yes if you intend to run on an Aspeed ast2700 or similar
+	  seventh generation Aspeed BMCs.
+
 menuconfig ARCH_BCM
 	bool "Broadcom SoC Support"
 
-- 
2.34.1

[PATCH v3 4/6] arm64: dts: aspeed: Add initial AST27XX device tree

[Kevin Chen]

Add aspeed-g7.dtsi to be AST27XX device tree.

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 arch/arm64/boot/dts/Makefile              |   1 +
 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 236 ++++++++++++++++++++++
 2 files changed, 237 insertions(+)
 create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 21cd3a87f385..6a590a66e1a9 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += amlogic
 subdir-y += apm
 subdir-y += apple
 subdir-y += arm
+subdir-y += aspeed
 subdir-y += bitmain
 subdir-y += broadcom
 subdir-y += cavium
diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
new file mode 100644
index 000000000000..3f1e801dec4c
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include <dt-bindings/clock/aspeed,ast2700-scu.h>
+#include <dt-bindings/reset/aspeed,ast2700-scu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
+
+/ {
+	compatible = "aspeed,ast2700";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			reg = <0x0 0x1>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			reg = <0x0 0x2>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			reg = <0x0 0x3>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x80000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a35-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		arm,cpu-registers-not-fw-configured;
+		always-on;
+	};
+
+	soc0: soc@10000000 {
+		compatible = "simple-bus";
+		reg = <0x0 0x10000000 0x10000000>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		syscon0: syscon@12c02000 {
+			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
+			reg = <0x0 0x12c02000 0x1000>;
+			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		intc0: interrupt-controller@12100000 {
+			compatible = "simple-mfd";
+			reg = <0 0x12100000 0x4000>;
+			ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+
+			intc0_11: interrupt-controller@1b00 {
+				compatible = "aspeed,ast2700-intc-ic";
+				reg = <0x0 0x1b00 0x10>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+					     <GIC_SPI 193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+					     <GIC_SPI 194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+					     <GIC_SPI 195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+					     <GIC_SPI 196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+					     <GIC_SPI 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			};
+		};
+
+		gic: interrupt-controller@12200000 {
+			compatible = "arm,gic-v3";
+			reg = <0 0x12200000 0x10000>, /* GICD */
+			      <0 0x12280000 0x80000>, /* GICR */
+			      <0 0x40440000 0x1000>;  /* GICC */
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupt-parent = <&gic>;
+		};
+	};
+
+	soc1: soc@14000000 {
+		compatible = "simple-bus";
+		reg = <0x0 0x14000000 0x10000000>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		syscon1: syscon@14c02000 {
+			compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
+			reg = <0x0 0x14c02000 0x1000>;
+			ranges = <0x0 0x0 0x0 0x14c02000 0x1000>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		intc1: interrupt-controller@14c18000 {
+			compatible = "simple-mfd";
+			reg = <0 0x14c18000 0x400>;
+			ranges = <0x0 0x0 0x0 0x14c18000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+
+			intc1_0: interrupt-controller@100 {
+				compatible = "aspeed,ast2700-intc-ic";
+				reg = <0x0 0x100 0x10>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				interrupts-extended = <&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			};
+
+			intc1_1: interrupt-controller@110 {
+				compatible = "aspeed,ast2700-intc-ic";
+				reg = <0x0 0x110 0x10>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				interrupts-extended = <&intc0_11 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			};
+
+			intc1_2: interrupt-controller@120 {
+				compatible = "aspeed,ast2700-intc-ic";
+				reg = <0x0 0x120 0x10>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				interrupts-extended = <&intc0_11 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			};
+
+			intc1_3: interrupt-controller@130 {
+				compatible = "aspeed,ast2700-intc-ic";
+				reg = <0x0 0x130 0x10>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				interrupts-extended = <&intc0_11 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			};
+
+			intc1_4: interrupt-controller@140 {
+				compatible = "aspeed,ast2700-intc-ic";
+				reg = <0x0 0x140 0x10>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				interrupts-extended = <&intc0_11 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			};
+
+			intc1_5: interrupt-controller@150 {
+				compatible = "aspeed,ast2700-intc-ic";
+				reg = <0x0 0x150 0x10>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				interrupts-extended = <&intc0_11 5 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			};
+		};
+
+		uart12: serial@14c33b00 {
+			compatible = "ns16550a";
+			reg = <0x0 0x14c33b00 0x100>;
+			interrupts-extended = <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			no-loopback-test;
+		};
+	};
+};
-- 
2.34.1

[PATCH v3 5/6] arm64: dts: aspeed: Add initial AST2700 EVB device tree

[Kevin Chen]

Add EVB board of AST2700 in ASPEED Architecture.

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 arch/arm64/boot/dts/aspeed/Makefile        |  4 ++
 arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 57 ++++++++++++++++++++++
 2 files changed, 61 insertions(+)
 create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
 create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts

diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspeed/Makefile
new file mode 100644
index 000000000000..ffe7e15017cc
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+dtb-$(CONFIG_ARCH_ASPEED) += \
+	ast2700-evb.dtb
diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
new file mode 100644
index 000000000000..6dad88c98ce0
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include "aspeed-g7.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+	model = "AST2700A1-EVB";
+	compatible = "aspeed,ast2700-evb", "aspeed,ast2700";
+
+	aliases {
+		serial12 = &uart12;
+	};
+
+	chosen {
+		bootargs = "console=ttyS12,115200n8";
+		stdout-path = &uart12;
+	};
+
+	firmware {
+		optee: optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
+	memory@400000000 {
+		device_type = "memory";
+		reg = <0x4 0x00000000 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		mcu_fw: mcu-firmware@42fe00000 {
+			reg = <0x4 0x2fe00000 0x200000>;
+			no-map;
+		};
+
+		atf: trusted-firmware-a@430000000 {
+			reg = <0x4 0x30000000 0x80000>;
+			no-map;
+		};
+
+		optee_core: optee_core@430080000 {
+			reg = <0x4 0x30080000 0x1000000>;
+			no-map;
+		};
+	};
+};
+
+&uart12 {
+	status = "okay";
+};
-- 
2.34.1

[PATCH v3 6/6] arm64: defconfig: Add ASPEED AST2700 family support

[Kevin Chen]

Enable CONFIG_ARCH_ASPEED in arm64 defconfig.

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c62831e61586..8826068c7c1d 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_APPLE=y
+CONFIG_ARCH_ASPEED=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM2835=y
 CONFIG_ARCH_BCM_IPROC=y
-- 
2.34.1

Re: [PATCH v3 0/6] Introduce ASPEED AST27XX BMC SoC

[Andrew Jeffery]

Hi Kevin,

On Thu, 2024-12-12 at 23:52 +0800, Kevin Chen wrote:
> ---
> v3:
>   - Split clk and reset driver to other commits, which are in series
> of
>     "Add support for AST2700 clk driver".
>   - For BMC console by UART12, add uart12 using ASPEED INTC
> architecture.
> 
> aspeed,ast2700-intc.yaml
>   - Add minItems to 1 to fix the warning by "make dtbs_check W=1".
>   - Add intc1 into example.
> 
> Kconfig.platforms
>   - Remove MACH_ASPEED_G7.
> 
> Kevin Chen (6):
>   dt-bindings: interrupt-controller: Refine size/interrupt-cell
> usage.
>   dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC
>   arm64: aspeed: Add support for ASPEED AST27XX BMC SoC
>   arm64: dts: aspeed: Add initial AST27XX device tree
>   arm64: dts: aspeed: Add initial AST2700 EVB device tree
>   arm64: defconfig: Add ASPEED AST2700 family support

Do you mind sending a v4, because I received a confusing arrangement of
patches:

[PATCH v3 1/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC
[PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.
[PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC
[PATCH v3 2/6] dt-bindings: interrupt-controller: Fix the size-cells in ast2700-intc
...

Where the content of 

   [PATCH v3 1/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC
   
and

   [PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC
   
Differs, as does the content of

   [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.
   
and

   [PATCH v3 2/6] dt-bindings: interrupt-controller: Fix the size-cells in ast2700-intc

Despite sounding like they might have the same intent

Andrew

Re: [PATCH v3 1/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC

[Krzysztof Kozlowski]

On 12/12/2024 16:52, Kevin Chen wrote:
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
> ---
Please run scripts/checkpatch.pl and fix reported warnings. Then please
run `scripts/checkpatch.pl --strict` and (probably) fix more warnings.
Some warnings can be ignored, especially from --strict run, but the code
here looks like it needs a fix. Feel free to get in touch if the warning
is not clear.

Best regards,
Krzysztof

Re: [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.

[Krzysztof Kozlowski]

On 12/12/2024 16:52, Kevin Chen wrote:
> 1. Because size-cells is no need to use 2, modify to 1 for use.

???

> 2. Add minItems to 1 for interrupts for intc1.

???

> 3. Add 1 interrupt of intc1 example into yaml file.

> 4. Add intc1 sub-module of uart12 as example using the intc0 and intc1.

What is all this?

BTW, there was no such patch in previous version and your changelog is
silent about it.

Subject: drop all full stops. Subject never ends with full stop.

> ---
>  .../aspeed,ast2700-intc.yaml                  | 60 +++++++++++++++----
>  1 file changed, 47 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
> index 55636d06a674..eadfbc45326b 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
> @@ -31,6 +31,7 @@ properties:
>        type as defined in interrupt.txt in this directory.
>  
>    interrupts:
> +    minItems: 1

Nope, not explained, not constrained. Your schema is supposed to be
constrained.


>      maxItems: 6
>      description: |
>        Depend to which INTC0 or INTC1 used.
> @@ -68,19 +69,52 @@ examples:
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
>  
>      bus {
> +      #address-cells = <2>;
> +      #size-cells = <1>;
> +
> +      intc0: interrupt-controller@12100000 {
> +        compatible = "simple-mfd";
> +        reg = <0 0x12100000 0x4000>;
> +        ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
>          #address-cells = <2>;
> -        #size-cells = <2>;
> -
> -        interrupt-controller@12101b00 {
> -            compatible = "aspeed,ast2700-intc-ic";
> -            reg = <0 0x12101b00 0 0x10>;
> -            #interrupt-cells = <2>;
> -            interrupt-controller;
> -            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> -                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> -                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> -                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> -                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> -                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;


I don't understand what is all this.

> +        #size-cells = <1>;
> +
> +        intc0_11: interrupt-controller@1b00 {
> +          compatible = "aspeed,ast2700-intc-ic";
> +          reg = <0 0x12101b00 0x10>;
> +          #interrupt-cells = <2>;
> +          interrupt-controller;
> +          interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +                       <GIC_SPI 193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +                       <GIC_SPI 194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +                       <GIC_SPI 195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +                       <GIC_SPI 196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +                       <GIC_SPI 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>          };
> +      };
> +
> +      intc1: interrupt-controller@14c18000 {
> +        compatible = "simple-mfd";
> +        reg = <0 0x14c18000 0x400>;
> +        ranges = <0x0 0x0 0x0 0x14c18000 0x400>;
> +        #address-cells = <2>;
> +        #size-cells = <1>;
> +
> +        intc1_4: interrupt-controller@140 {
> +          compatible = "aspeed,ast2700-intc-ic";
> +          reg = <0x0 0x140 0x10>;
> +          #interrupt-cells = <2>;
> +          interrupt-controller;
> +          interrupts-extended = <&intc0_11 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +        };
> +      };
> +
> +      uart12: serial@14c33b00 {
> +        compatible = "ns16550a";
> +        reg = <0x0 0x14c33b00 0x100>;
> +        interrupts-extended = <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +        reg-shift = <2>;
> +        reg-io-width = <4>;
> +        no-loopback-test;
> +      };

And above is not related at all. Don't add entirely unrelated changes. Drop.


Best regards,
Krzysztof

Re: [PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC

[Krzysztof Kozlowski]

On 12/12/2024 16:52, Kevin Chen wrote:
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
> ---
>  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> index 2f92b8ab08fa..20191fee1f5b 100644
> --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> @@ -101,4 +101,10 @@ properties:
>                - ufispace,ncplite-bmc
>            - const: aspeed,ast2600
>  
> +      - description: AST2700 based boards
> +        items:
> +          - enum:
> +              - aspeed,ast2700-evb
> +          - const: aspeed,ast2700
> +
>  additionalProperties: true



This patchset is just corrupted. You already sent it as patch #1.

Please run scripts/checkpatch.pl and fix reported warnings. Then please
run `scripts/checkpatch.pl --strict` and (probably) fix more warnings.
Some warnings can be ignored, especially from --strict run, but the code
here looks like it needs a fix. Feel free to get in touch if the warning
is not clear.

Best regards,
Krzysztof

Re: [PATCH v3 2/6] dt-bindings: interrupt-controller: Fix the size-cells in ast2700-intc

[Krzysztof Kozlowski]

On 12/12/2024 16:52, Kevin Chen wrote:
> It is no need to let size-cells to 2 for the ASPEED AST27XX INTC. Modify
> the ast2700-intc example usage.

Why?

This just looks useless.

> 
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
> ---
>  .../bindings/interrupt-controller/aspeed,ast2700-intc.yaml    | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 


Best regards,
Krzysztof

Re: [PATCH v3 4/6] arm64: dts: aspeed: Add initial AST27XX device tree

[Krzysztof Kozlowski]

On 12/12/2024 16:52, Kevin Chen wrote:
> Add aspeed-g7.dtsi to be AST27XX device tree.
> 
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>

Where are all the bindings? Why are you silent about this? The patchset
adding new SoC DTS, when separate, is supposed to explain where we can
find the bindings.

> ---
>  arch/arm64/boot/dts/Makefile              |   1 +
>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 236 ++++++++++++++++++++++
>  2 files changed, 237 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.


Best regards,
Krzysztof

Re: [PATCH v3 5/6] arm64: dts: aspeed: Add initial AST2700 EVB device tree

[Krzysztof Kozlowski]

On 12/12/2024 16:52, Kevin Chen wrote:
> Add EVB board of AST2700 in ASPEED Architecture.
> 
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
> ---
>  arch/arm64/boot/dts/aspeed/Makefile        |  4 ++
>  arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 57 ++++++++++++++++++++++
>  2 files changed, 61 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
>  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> 
> diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspeed/Makefile
> new file mode 100644
> index 000000000000..ffe7e15017cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/aspeed/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_ASPEED) += \
> +	ast2700-evb.dtb
> diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> new file mode 100644
> index 000000000000..6dad88c98ce0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +/dts-v1/;
> +
> +#include "aspeed-g7.dtsi"
> +#include <dt-bindings/gpio/aspeed-gpio.h>
> +
> +/ {
> +	model = "AST2700A1-EVB";
> +	compatible = "aspeed,ast2700-evb", "aspeed,ast2700";
> +
> +	aliases {
> +		serial12 = &uart12;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS12,115200n8";
> +		stdout-path = &uart12;

Nothing improved. You keep ignoring my comments: not responding, not
addressing, not fixing the code.

> +	};
> +
> +	firmware {
> +		optee: optee {
> +			compatible = "linaro,optee-tz";
> +			method = "smc";
> +		};
> +	};
> +
> +	memory@400000000 {
> +		device_type = "memory";
> +		reg = <0x4 0x00000000 0x40000000>;
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		mcu_fw: mcu-firmware@42fe00000 {
> +			reg = <0x4 0x2fe00000 0x200000>;
> +			no-map;
> +		};
> +
> +		atf: trusted-firmware-a@430000000 {
> +			reg = <0x4 0x30000000 0x80000>;
> +			no-map;
> +		};
> +
> +		optee_core: optee_core@430080000 {

Follow DTS Coding style document. That's the same comment as before.


Best regards,
Krzysztof

Re: [PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC

[Krzysztof Kozlowski]

On 13/12/2024 08:59, Krzysztof Kozlowski wrote:
> On 12/12/2024 16:52, Kevin Chen wrote:
>> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
>> ---
>>  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>> index 2f92b8ab08fa..20191fee1f5b 100644
>> --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>> +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>> @@ -101,4 +101,10 @@ properties:
>>                - ufispace,ncplite-bmc
>>            - const: aspeed,ast2600
>>  
>> +      - description: AST2700 based boards
>> +        items:
>> +          - enum:
>> +              - aspeed,ast2700-evb
>> +          - const: aspeed,ast2700
>> +
>>  additionalProperties: true
> 
> 
> 
> This patchset is just corrupted. You already sent it as patch #1.
> 
> Please run scripts/checkpatch.pl and fix reported warnings. Then please
> run `scripts/checkpatch.pl --strict` and (probably) fix more warnings.
> Some warnings can be ignored, especially from --strict run, but the code
> here looks like it needs a fix. Feel free to get in touch if the warning
> is not clear.
BTW, you already got here same comments before and this is third time
you send exactly the same without implementing what we asked you.

Three times same issue.

NAK

Best regards,
Krzysztof

Re: [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.

[Krzysztof Kozlowski]

On Thu, Dec 12, 2024 at 11:52:31PM +0800, Kevin Chen wrote:
> 1. Because size-cells is no need to use 2, modify to 1 for use.
> 2. Add minItems to 1 for interrupts for intc1.
> 3. Add 1 interrupt of intc1 example into yaml file.
> 4. Add intc1 sub-module of uart12 as example using the intc0 and intc1.
> ---
>  .../aspeed,ast2700-intc.yaml                  | 60 +++++++++++++++----
>  1 file changed, 47 insertions(+), 13 deletions(-)
> 

As with all your patches, repeating since v1 the same comment, so one
more last time:

Please run scripts/checkpatch.pl and fix reported warnings. Then please
run 'scripts/checkpatch.pl --strict' and (probably) fix more warnings.
Some warnings can be ignored, especially from --strict run, but the code
here looks like it needs a fix. Feel free to get in touch if the warning
is not clear.

Best regards,
Krzysztof

RE: [PATCH v3 0/6] Introduce ASPEED AST27XX BMC SoC

[Kevin Chen]

Hi,

> > ---
> > v3:
> >   - Split clk and reset driver to other commits, which are in series
> > of
> >     "Add support for AST2700 clk driver".
> >   - For BMC console by UART12, add uart12 using ASPEED INTC
> > architecture.
> >
> > aspeed,ast2700-intc.yaml
> >   - Add minItems to 1 to fix the warning by "make dtbs_check W=1".
> >   - Add intc1 into example.
> >
> > Kconfig.platforms
> >   - Remove MACH_ASPEED_G7.
> >
> > Kevin Chen (6):
> >   dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.
> >   dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC
> >   arm64: aspeed: Add support for ASPEED AST27XX BMC SoC
> >   arm64: dts: aspeed: Add initial AST27XX device tree
> >   arm64: dts: aspeed: Add initial AST2700 EVB device tree
> >   arm64: defconfig: Add ASPEED AST2700 family support
> 
> Do you mind sending a v4, because I received a confusing arrangement of
> patches:
OK. I put a mixed commits in our send-mail server. I will try to send v4 patches.
Thanks for your reminder.

> 
> [PATCH v3 1/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC [PATCH v3
> 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.
> [PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC [PATCH v3
> 2/6] dt-bindings: interrupt-controller: Fix the size-cells in ast2700-intc ...
> 
> Where the content of
> 
>    [PATCH v3 1/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC
> 
> and
> 
>    [PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC
> 
> Differs, as does the content of
> 
>    [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell
> usage.
> 
> and
> 
>    [PATCH v3 2/6] dt-bindings: interrupt-controller: Fix the size-cells in
> ast2700-intc
> 
> Despite sounding like they might have the same intent
> 
> Andrew

RE: [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.

[Kevin Chen]

Hi,

> > 1. Because size-cells is no need to use 2, modify to 1 for use.
> > 2. Add minItems to 1 for interrupts for intc1.
> > 3. Add 1 interrupt of intc1 example into yaml file.
> > 4. Add intc1 sub-module of uart12 as example using the intc0 and intc1.
> > ---
> >  .../aspeed,ast2700-intc.yaml                  | 60
> +++++++++++++++----
> >  1 file changed, 47 insertions(+), 13 deletions(-)
> >
> 
> As with all your patches, repeating since v1 the same comment, so one more
> last time:
> 
> Please run scripts/checkpatch.pl and fix reported warnings. Then please run
> 'scripts/checkpatch.pl --strict' and (probably) fix more warnings.
> Some warnings can be ignored, especially from --strict run, but the code here
> looks like it needs a fix. Feel free to get in touch if the warning is not clear.
OK.
I need to wait the Ryan's series of " "Add support for AST2700 clk driver"" for clk and reset drivers.
I will wait for his commits to be merged with the warnings fixed.


> 
> Best regards,
> Krzysztof

RE: [PATCH v3 5/6] arm64: dts: aspeed: Add initial AST2700 EVB device tree

[Kevin Chen]

Hi Krzk,

> > Add EVB board of AST2700 in ASPEED Architecture.
> >
> > Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
> > ---
> >  arch/arm64/boot/dts/aspeed/Makefile        |  4 ++
> >  arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 57
> > ++++++++++++++++++++++
> >  2 files changed, 61 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
> >  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> >
> > diff --git a/arch/arm64/boot/dts/aspeed/Makefile
> > b/arch/arm64/boot/dts/aspeed/Makefile
> > new file mode 100644
> > index 000000000000..ffe7e15017cc
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/aspeed/Makefile
> > @@ -0,0 +1,4 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +
> > +dtb-$(CONFIG_ARCH_ASPEED) += \
> > +	ast2700-evb.dtb
> > diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> > b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> > new file mode 100644
> > index 000000000000..6dad88c98ce0
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> > @@ -0,0 +1,57 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +
> > +/dts-v1/;
> > +
> > +#include "aspeed-g7.dtsi"
> > +#include <dt-bindings/gpio/aspeed-gpio.h>
> > +
> > +/ {
> > +	model = "AST2700A1-EVB";
> > +	compatible = "aspeed,ast2700-evb", "aspeed,ast2700";
> > +
> > +	aliases {
> > +		serial12 = &uart12;
> > +	};
> > +
> > +	chosen {
> > +		bootargs = "console=ttyS12,115200n8";
> > +		stdout-path = &uart12;
> 
> Nothing improved. You keep ignoring my comments: not responding, not
> addressing, not fixing the code.
OK. I will remove the bootargs.

> 
> > +	};
> > +
> > +	firmware {
> > +		optee: optee {
> > +			compatible = "linaro,optee-tz";
> > +			method = "smc";
> > +		};
> > +	};
> > +
> > +	memory@400000000 {
> > +		device_type = "memory";
> > +		reg = <0x4 0x00000000 0x40000000>;
> > +	};
> > +
> > +	reserved-memory {
> > +		#address-cells = <2>;
> > +		#size-cells = <1>;
> > +		ranges;
> > +
> > +		mcu_fw: mcu-firmware@42fe00000 {
> > +			reg = <0x4 0x2fe00000 0x200000>;
> > +			no-map;
> > +		};
> > +
> > +		atf: trusted-firmware-a@430000000 {
> > +			reg = <0x4 0x30000000 0x80000>;
> > +			no-map;
> > +		};
> > +
> > +		optee_core: optee_core@430080000 {
> 
> Follow DTS Coding style document. That's the same comment as before.
OK. I will fix to optee-core:optee-core@430080000 {

> 
> 
> Best regards,
> Krzysztof

RE: [PATCH v3 4/6] arm64: dts: aspeed: Add initial AST27XX device tree

[Kevin Chen]

Hi Krzk,

> > Add aspeed-g7.dtsi to be AST27XX device tree.
> >
> > Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
> 
> Where are all the bindings? Why are you silent about this? The patchset adding
> new SoC DTS, when separate, is supposed to explain where we can find the
> bindings.
Do you mean apseed,ast2700-scu0 and aspeed,ast2700-scu1?
Could I make sure this new SoC DTS how to submit?

Thanks.

> 
> > ---
> >  arch/arm64/boot/dts/Makefile              |   1 +
> >  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 236
> > ++++++++++++++++++++++
> >  2 files changed, 237 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.
> 
> 
> Best regards,
> Krzysztof

Best Regards,
Kevin. Chen

RE: [PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC

[Kevin Chen]

Hi Krzk,

> > On 12/12/2024 16:52, Kevin Chen wrote:
> >> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
> >> ---
> >>  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 6 ++++++
> >>  1 file changed, 6 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> >> b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> >> index 2f92b8ab08fa..20191fee1f5b 100644
> >> --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> >> +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
> >> @@ -101,4 +101,10 @@ properties:
> >>                - ufispace,ncplite-bmc
> >>            - const: aspeed,ast2600
> >>
> >> +      - description: AST2700 based boards
> >> +        items:
> >> +          - enum:
> >> +              - aspeed,ast2700-evb
> >> +          - const: aspeed,ast2700
> >> +
> >>  additionalProperties: true
> >
> >
> >
> > This patchset is just corrupted. You already sent it as patch #1.
> >
> > Please run scripts/checkpatch.pl and fix reported warnings. Then
> > please run `scripts/checkpatch.pl --strict` and (probably) fix more warnings.
> > Some warnings can be ignored, especially from --strict run, but the
> > code here looks like it needs a fix. Feel free to get in touch if the
> > warning is not clear.
> BTW, you already got here same comments before and this is third time you
> send exactly the same without implementing what we asked you.
Please check the following message.
https://lore.kernel.org/lkml/PSAPR06MB494943F3F34881D23CEEBD9A897D2@PSAPR06MB4949.apcprd06.prod.outlook.com/

Or, how do you think what is better for me to add ast2700-evb?

> 
> Three times same issue.
> 
> NAK
> 
> Best regards,
> Krzysztof

Best Regards,
Kevin. Chen

RE: [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.

[Kevin Chen]

Hi Krzk,

> > 1. Because size-cells is no need to use 2, modify to 1 for use.
> 
> ???
So, is it OK that I change the size-cells back to 2 include the aspeed,ast2700-intc.yaml examples and aspeed-g7.dtsi?

> 
> > 2. Add minItems to 1 for interrupts for intc1.
> 
> ???
For variable interrupt numbers, I need to fix the below warnings by minItems.
  DTC [C] arch/arm64/boot/dts/aspeed/ast2700-evb.dtb
/home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@100: interrupts-extended: [[3, 0, 3844]] is too short
        from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
/home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@110: interrupts-extended: [[3, 1, 3844]] is too short
        from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
/home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@120: interrupts-extended: [[3, 2, 3844]] is too short
        from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
/home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@130: interrupts-extended: [[3, 3, 3844]] is too short
        from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
/home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@140: interrupts-extended: [[3, 4, 3844]] is too short
        from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
/home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@150: interrupts-extended: [[3, 5, 3844]] is too short
        from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#

> 
> > 3. Add 1 interrupt of intc1 example into yaml file.
> 
> > 4. Add intc1 sub-module of uart12 as example using the intc0 and intc1.
> 
> What is all this?
> 
> BTW, there was no such patch in previous version and your changelog is silent
> about it.
Agree, I will restore the previous version.

> 
> Subject: drop all full stops. Subject never ends with full stop.
> 
> > ---
> >  .../aspeed,ast2700-intc.yaml                  | 60
> +++++++++++++++----
> >  1 file changed, 47 insertions(+), 13 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
> > 0-intc.yaml
> > b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
> > 0-intc.yaml index 55636d06a674..eadfbc45326b 100644
> > ---
> > a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
> > 0-intc.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,as
> > +++ t2700-intc.yaml
> > @@ -31,6 +31,7 @@ properties:
> >        type as defined in interrupt.txt in this directory.
> >
> >    interrupts:
> > +    minItems: 1
> 
> Nope, not explained, not constrained. Your schema is supposed to be
> constrained.
> 
> 
> >      maxItems: 6
> >      description: |
> >        Depend to which INTC0 or INTC1 used.
> > @@ -68,19 +69,52 @@ examples:
> >      #include <dt-bindings/interrupt-controller/arm-gic.h>
> >
> >      bus {
> > +      #address-cells = <2>;
> > +      #size-cells = <1>;
> > +
> > +      intc0: interrupt-controller@12100000 {
> > +        compatible = "simple-mfd";
> > +        reg = <0 0x12100000 0x4000>;
> > +        ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
> >          #address-cells = <2>;
> > -        #size-cells = <2>;
> > -
> > -        interrupt-controller@12101b00 {
> > -            compatible = "aspeed,ast2700-intc-ic";
> > -            reg = <0 0x12101b00 0 0x10>;
> > -            #interrupt-cells = <2>;
> > -            interrupt-controller;
> > -            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> > -                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
> 
> 
> I don't understand what is all this.
> 
> > +        #size-cells = <1>;
> > +
> > +        intc0_11: interrupt-controller@1b00 {
> > +          compatible = "aspeed,ast2700-intc-ic";
> > +          reg = <0 0x12101b00 0x10>;
> > +          #interrupt-cells = <2>;
> > +          interrupt-controller;
> > +          interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>,
> > +                       <GIC_SPI 193 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>,
> > +                       <GIC_SPI 194 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>,
> > +                       <GIC_SPI 195 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>,
> > +                       <GIC_SPI 196 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>,
> > +                       <GIC_SPI 197 (GIC_CPU_MASK_SIMPLE(4) |
> > + IRQ_TYPE_LEVEL_HIGH)>;
> >          };
> > +      };
> > +
> > +      intc1: interrupt-controller@14c18000 {
> > +        compatible = "simple-mfd";
> > +        reg = <0 0x14c18000 0x400>;
> > +        ranges = <0x0 0x0 0x0 0x14c18000 0x400>;
> > +        #address-cells = <2>;
> > +        #size-cells = <1>;
> > +
> > +        intc1_4: interrupt-controller@140 {
> > +          compatible = "aspeed,ast2700-intc-ic";
> > +          reg = <0x0 0x140 0x10>;
> > +          #interrupt-cells = <2>;
> > +          interrupt-controller;
> > +          interrupts-extended = <&intc0_11 4
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > +        };
> > +      };
> > +
> > +      uart12: serial@14c33b00 {
> > +        compatible = "ns16550a";
> > +        reg = <0x0 0x14c33b00 0x100>;
> > +        interrupts-extended = <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4)
> | IRQ_TYPE_LEVEL_HIGH)>;
> > +        reg-shift = <2>;
> > +        reg-io-width = <4>;
> > +        no-loopback-test;
> > +      };
> 
> And above is not related at all. Don't add entirely unrelated changes. Drop.
> 
> 
> Best regards,
> Krzysztof

Best Regards,
Kevin. Chen

Re: [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage.

[Krzysztof Kozlowski]

On 18/12/2024 04:04, Kevin Chen wrote:
> Hi Krzk,
> 
>>> 1. Because size-cells is no need to use 2, modify to 1 for use.
>>
>> ???
> So, is it OK that I change the size-cells back to 2 include the aspeed,ast2700-intc.yaml examples and aspeed-g7.dtsi?

No, my total surprise is that I did not understand what it maens. Is
this changelog? Commit msg? Why such change is made?

> 
>>
>>> 2. Add minItems to 1 for interrupts for intc1.
>>
>> ???
> For variable interrupt numbers, I need to fix the below warnings by minItems.
>   DTC [C] arch/arm64/boot/dts/aspeed/ast2700-evb.dtb
> /home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@100: interrupts-extended: [[3, 0, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> /home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@110: interrupts-extended: [[3, 1, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> /home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@120: interrupts-extended: [[3, 2, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> /home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@130: interrupts-extended: [[3, 3, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> /home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@140: interrupts-extended: [[3, 4, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> /home/kevin/linux-mainline/arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@150: interrupts-extended: [[3, 5, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> 
>>
>>> 3. Add 1 interrupt of intc1 example into yaml file.
>>
>>> 4. Add intc1 sub-module of uart12 as example using the intc0 and intc1.
>>
>> What is all this?
>>
>> BTW, there was no such patch in previous version and your changelog is silent
>> about it.
> Agree, I will restore the previous version.
> 
>>
>> Subject: drop all full stops. Subject never ends with full stop.
>>
>>> ---
>>>  .../aspeed,ast2700-intc.yaml                  | 60
>> +++++++++++++++----
>>>  1 file changed, 47 insertions(+), 13 deletions(-)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
>>> 0-intc.yaml
>>> b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
>>> 0-intc.yaml index 55636d06a674..eadfbc45326b 100644
>>> ---
>>> a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
>>> 0-intc.yaml
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,as
>>> +++ t2700-intc.yaml
>>> @@ -31,6 +31,7 @@ properties:
>>>        type as defined in interrupt.txt in this directory.
>>>
>>>    interrupts:
>>> +    minItems: 1
>>
>> Nope, not explained, not constrained. Your schema is supposed to be
>> constrained.

I still do not understand this commit at all.


Best regards,
Krzysztof

Re: [PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC

[Krzysztof Kozlowski]

On 18/12/2024 03:55, Kevin Chen wrote:
> Hi Krzk,
> 
>>> On 12/12/2024 16:52, Kevin Chen wrote:
>>>> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
>>>> ---
>>>>  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 6 ++++++
>>>>  1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>>>> b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>>>> index 2f92b8ab08fa..20191fee1f5b 100644
>>>> --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
>>>> @@ -101,4 +101,10 @@ properties:
>>>>                - ufispace,ncplite-bmc
>>>>            - const: aspeed,ast2600
>>>>
>>>> +      - description: AST2700 based boards
>>>> +        items:
>>>> +          - enum:
>>>> +              - aspeed,ast2700-evb
>>>> +          - const: aspeed,ast2700
>>>> +
>>>>  additionalProperties: true
>>>
>>>
>>>
>>> This patchset is just corrupted. You already sent it as patch #1.
>>>
>>> Please run scripts/checkpatch.pl and fix reported warnings. Then
>>> please run `scripts/checkpatch.pl --strict` and (probably) fix more warnings.
>>> Some warnings can be ignored, especially from --strict run, but the
>>> code here looks like it needs a fix. Feel free to get in touch if the
>>> warning is not clear.
>> BTW, you already got here same comments before and this is third time you
>> send exactly the same without implementing what we asked you.
> Please check the following message.
> https://lore.kernel.org/lkml/PSAPR06MB494943F3F34881D23CEEBD9A897D2@PSAPR06MB4949.apcprd06.prod.outlook.com/
> 
> Or, how do you think what is better for me to add ast2700-evb?
Please stop responding just to make me go away.

Read the comments from half a year ago, which you have never implemented:

https://lore.kernel.org/lkml/e6cb6f26-fef2-49bc-ab25-fdc9a659f593@kernel.org/

On every new patch I was asking you to go back, but again you were
ignoring each of such messages.

Best regards,
Krzysztof