[PATCH 0/3] Add devicetree nodes for RK3528, RK3562 and RK356x

[PATCH 0/3] Add devicetree nodes for RK3528, RK3562 and RK356x

[Heiko Stuebner]

This is a companion series to the binding+driver changes [0], that adds
the relevant OTP controller nodes to the core SoC devicetrees.

[0] https://lore.kernel.org/linux-rockchip/20260205211901.490181-1-heiko@sntech.de/T/#t

Heiko Stuebner (2):
  arm64: dts: rockchip: Enable OTP controller for RK3562
  arm64: dts: rockchip: Enable OTP controller for RK356x

Jonas Karlman (1):
  arm64: dts: rockchip: Enable OTP controller for RK3528

 arch/arm64/boot/dts/rockchip/rk3528.dtsi      | 47 +++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3562.dtsi      | 46 ++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 ++++++++++++++++++
 3 files changed, 139 insertions(+)

-- 
2.47.2

[PATCH 1/3] arm64: dts: rockchip: Enable OTP controller for RK3562

[Heiko Stuebner]

Enable the One Time Programmable Controller (OTPC) in RK3562 and add
an initial nvmem fixed layout.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm64/boot/dts/rockchip/rk3562.dtsi | 46 ++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
index f84676b47b27..07626dba21bf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
@@ -1093,6 +1093,52 @@ sdmmc1: mmc@ff890000 {
 			status = "disabled";
 		};
 
+		otp: otp@ff930000 {
+			compatible = "rockchip,rk3562-otp";
+			reg = <0x0 0xff930000 0x0 0x4000>;
+			clocks = <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+				 <&cru PCLK_OTPPHY>, <&cru CLK_SBPI_OTPC_NS>;
+			clock-names = "otp", "apb_pclk", "phy", "sbpi";
+			resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
+				 <&cru SRST_P_OTPPHY>, <&cru SRST_SBPI_OTPC_NS>;
+			reset-names = "otp", "apb", "phy", "sbpi";
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				cpu_code: cpu-code@2 {
+					reg = <0x02 0x2>;
+				};
+
+				otp_cpu_version: cpu-version@8 {
+					reg = <0x08 0x1>;
+					bits = <3 3>;
+				};
+
+				otp_id: id@a {
+					reg = <0x0a 0x10>;
+				};
+
+				cpu_leakage: cpu-leakage@1a {
+					reg = <0x1a 0x1>;
+				};
+
+				log_leakage: log-leakage@1b {
+					reg = <0x1b 0x1>;
+				};
+
+				npu_leakage: npu-leakage@1c {
+					reg = <0x1c 0x1>;
+				};
+
+				gpu_leakage: gpu-leakage@1d {
+					reg = <0x1d 0x1>;
+				};
+			};
+		};
+
 		dmac: dma-controller@ff990000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x0 0xff990000 0x0 0x4000>;
-- 
2.47.2

Re: [PATCH 1/3] arm64: dts: rockchip: Enable OTP controller for RK3562

[Jonas Karlman]

Hi Heiko,

Thanks for including my RK3528 patches :-)

On 2/5/2026 10:23 PM, Heiko Stuebner wrote:
> Enable the One Time Programmable Controller (OTPC) in RK3562 and add
> an initial nvmem fixed layout.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk3562.dtsi | 46 ++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> index f84676b47b27..07626dba21bf 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> @@ -1093,6 +1093,52 @@ sdmmc1: mmc@ff890000 {
>  			status = "disabled";
>  		};
>  
> +		otp: otp@ff930000 {

I noticed that the node names is not consistent for all three patches in
this series.

A quick grep at Linux src also suggest that efuse@ being the most common
node name used for similar otpc/efuse, efuse is also listed under
2.2.2 Generic Names Recommendation in DT spec.

Maybe the nodes should be renamed to use efuse@ or something else?

I am mostly concerned on what the name ends up as and how that may
affect U-Boot in a future dts/upstream sync. U-Boot currently have
limited otp nodes in soc u-boot.dtsi files for these SoCs.

Regards,
Jonas

> +			compatible = "rockchip,rk3562-otp";
> +			reg = <0x0 0xff930000 0x0 0x4000>;
> +			clocks = <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>,
> +				 <&cru PCLK_OTPPHY>, <&cru CLK_SBPI_OTPC_NS>;
> +			clock-names = "otp", "apb_pclk", "phy", "sbpi";
> +			resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
> +				 <&cru SRST_P_OTPPHY>, <&cru SRST_SBPI_OTPC_NS>;
> +			reset-names = "otp", "apb", "phy", "sbpi";
> +
> +			nvmem-layout {
> +				compatible = "fixed-layout";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				cpu_code: cpu-code@2 {
> +					reg = <0x02 0x2>;
> +				};
> +
> +				otp_cpu_version: cpu-version@8 {
> +					reg = <0x08 0x1>;
> +					bits = <3 3>;
> +				};
> +
> +				otp_id: id@a {
> +					reg = <0x0a 0x10>;
> +				};
> +
> +				cpu_leakage: cpu-leakage@1a {
> +					reg = <0x1a 0x1>;
> +				};
> +
> +				log_leakage: log-leakage@1b {
> +					reg = <0x1b 0x1>;
> +				};
> +
> +				npu_leakage: npu-leakage@1c {
> +					reg = <0x1c 0x1>;
> +				};
> +
> +				gpu_leakage: gpu-leakage@1d {
> +					reg = <0x1d 0x1>;
> +				};
> +			};
> +		};
> +
>  		dmac: dma-controller@ff990000 {
>  			compatible = "arm,pl330", "arm,primecell";
>  			reg = <0x0 0xff990000 0x0 0x4000>;

Re: [PATCH 1/3] arm64: dts: rockchip: Enable OTP controller for RK3562

[Heiko Stübner]

Am Montag, 9. Februar 2026, 17:54:51 Mitteleuropäische Normalzeit schrieb Jonas Karlman:
> Hi Heiko,
> 
> Thanks for including my RK3528 patches :-)
> 
> On 2/5/2026 10:23 PM, Heiko Stuebner wrote:
> > Enable the One Time Programmable Controller (OTPC) in RK3562 and add
> > an initial nvmem fixed layout.
> > 
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3562.dtsi | 46 ++++++++++++++++++++++++
> >  1 file changed, 46 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> > index f84676b47b27..07626dba21bf 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> > @@ -1093,6 +1093,52 @@ sdmmc1: mmc@ff890000 {
> >  			status = "disabled";
> >  		};
> >  
> > +		otp: otp@ff930000 {
> 
> I noticed that the node names is not consistent for all three patches in
> this series.
> 
> A quick grep at Linux src also suggest that efuse@ being the most common
> node name used for similar otpc/efuse, efuse is also listed under
> 2.2.2 Generic Names Recommendation in DT spec.
> 
> Maybe the nodes should be renamed to use efuse@ or something else?

Fine by me :-)
So we'll make this efuse@ for all 3 newly added otp controllers.

Heiko

[PATCH 2/3] arm64: dts: rockchip: Enable OTP controller for RK356x

[Heiko Stuebner]

Enable the One Time Programmable Controller (OTPC) in RK356x and add
an initial nvmem fixed layout.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index 8893b7b6cc9f..72c98337f359 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -1104,6 +1104,52 @@ rng: rng@fe388000 {
 		status = "disabled";
 	};
 
+	otp: otp@fe38c000 {
+		compatible = "rockchip,rk3568-otp";
+		reg = <0x0 0xfe38c000 0x0 0x4000>;
+		clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>,
+			 <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>;
+		clock-names = "otp", "apb_pclk", "phy", "sbpi";
+		resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>,
+			 <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>;
+		reset-names = "otp", "apb", "phy", "sbpi";
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cpu_code: cpu-code@2 {
+				reg = <0x02 0x2>;
+			};
+
+			otp_cpu_version: cpu-version@8 {
+				reg = <0x08 0x1>;
+				bits = <3 3>;
+			};
+
+			otp_id: id@a {
+				reg = <0x0a 0x10>;
+			};
+
+			cpu_leakage: cpu-leakage@1a {
+				reg = <0x1a 0x1>;
+			};
+
+			log_leakage: log-leakage@1b {
+				reg = <0x1b 0x1>;
+			};
+
+			npu_leakage: npu-leakage@1c {
+				reg = <0x1c 0x1>;
+			};
+
+			gpu_leakage: gpu-leakage@1d {
+				reg = <0x1d 0x1>;
+			};
+		};
+	};
+
 	i2s0_8ch: i2s@fe400000 {
 		compatible = "rockchip,rk3568-i2s-tdm";
 		reg = <0x0 0xfe400000 0x0 0x1000>;
-- 
2.47.2

[PATCH 3/3] arm64: dts: rockchip: Enable OTP controller for RK3528

[Heiko Stuebner]

From: Jonas Karlman <jonas@kwiboo.se>

Enable the One Time Programmable Controller (OTPC) in RK3528 and add
an initial nvmem fixed layout.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm64/boot/dts/rockchip/rk3528.dtsi | 47 ++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index d402f2828814..171b48c9cdb7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -1190,6 +1190,53 @@ sdmmc: mmc@ffc30000 {
 			status = "disabled";
 		};
 
+		otp: nvmem@ffce0000 {
+			compatible = "rockchip,rk3528-otp";
+			reg = <0x0 0xffce0000 0x0 0x4000>;
+			clocks = <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+				 <&cru CLK_SBPI_OTPC_NS>;
+			clock-names = "otp", "apb_pclk", "sbpi";
+			resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
+				 <&cru SRST_SBPI_OTPC_NS>;
+			reset-names = "otp", "apb", "sbpi";
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				cpu_code: cpu-code@2 {
+					reg = <0x02 0x2>;
+				};
+
+				otp_cpu_version: cpu-version@8 {
+					reg = <0x08 0x1>;
+					bits = <3 3>;
+				};
+
+				otp_id: id@a {
+					reg = <0x0a 0x10>;
+				};
+
+				cpu_leakage: cpu-leakage@1a {
+					reg = <0x1a 0x1>;
+				};
+
+				logic_leakage: logic-leakage@1b {
+					reg = <0x1b 0x1>;
+				};
+
+				gpu_leakage: gpu-leakage@1c {
+					reg = <0x1c 0x1>;
+				};
+
+				tsadc_trim: tsadc-trim@44 {
+					reg = <0x44 0x2>;
+					bits = <0 10>;
+				};
+			};
+		};
+
 		dmac: dma-controller@ffd60000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x0 0xffd60000 0x0 0x4000>;
-- 
2.47.2