From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7DDFC43334 for ; Sun, 3 Jul 2022 18:44:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A9ePJhKv7XTEBpR0NatL58JaruqEuk6fFjw5PNVYm9w=; b=ehbI6x/iSqVRwL KidmpnrzfCMwuLTLJ4E7Dt/s3RXHmm/X6/wOgvnzjuIjDWq5Hws3foT/DFGu5Z2sxb43ja62Ay/nf GTot7S8rmLdTMf28QWsUa40XJrkwFb1Mw8lXDPmVtL4RL58lkdBubAPR43rIodmxHS0lzSc58jU80 wYzpSNWdnr93Qf3P0/EXF+xEysF3UvftCStZ59fMMBNXjPijAS6DXgYp1mZ7zTpXCkig4IODW3mB9 CqIivAFJ/zWey/rN4fsniS7QAiSwbfygUftUL/CNdUhqnLHX74ULDbtyhll1VnxK8DqEGbkjSYejm JY0UKL95aeyBeazjeSFQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o84ZY-000G6S-4B; Sun, 03 Jul 2022 18:43:56 +0000 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o84ZU-000G5Y-53 for linux-arm-kernel@lists.infradead.org; Sun, 03 Jul 2022 18:43:53 +0000 Received: by mail-ej1-x62b.google.com with SMTP id dn9so7849168ejc.7 for ; Sun, 03 Jul 2022 11:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YNiliZWXNoSejurrkg/bZM1+hwajBnqHCSCntKvBUaI=; b=npbI1nD+znAoMU7pXRx5AAX2LM820YJ/YUybd49rlin0LVoZdUNVLe9DSUHETWBfh5 LlBJioKkqM6GkY/WB0BE2keebr0ENUPFlCaQ3FQWJ9+n0kS8Nvu+u/fSUo4Sk59Rr0nG rSs4yJ9A9wIJzkjMqJU0nQ0PWemZJ593KwBvQ5pT5YmIshoS/123yM1iJsw+PvRGxReo lkiUH+q1nltWejKztICUVGfEWbJ72NTWGhuVnzs5LW7KY0e1Tuyf9SYxjN0AntHJRyxe yTzfcQVCLnrWqNtT/3BA7S7Xaz9PPg2stfswbBVVUpi30mxEpPNXFWawNED7W4cVugNr wwzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YNiliZWXNoSejurrkg/bZM1+hwajBnqHCSCntKvBUaI=; b=B+idD2non/O466R8rhg2ffJDv3E3koMMBle0DpL6AigSB3m+Kgk5/jax2oetHmgDY4 r5ZOMJpga4FN6C/CIoA9laA1TnCNoXSHmVk5oU71xmF54D6KhXCWzL4OhaAr5XvVAiI9 UPtU5mXxYA4nbyCUpHTG3IA5TQ9ABGptVZtj2R93hnTdjKF1e+VLbzcZRswmZxhkfpO3 Ksqj5RlbZvEFyYWFeZ+m4YaG5twiIIShkDy4gdU3Wc24Ji2gCU/msA8HsTvy7bVeMFQn uXqC8gzIAKH14smWIhSI7s0Z0k3sQs7TrvvdEDQYVtKQmfmx6l2ql1OhzC4nHmEfLyJN rVpw== X-Gm-Message-State: AJIora/Zndu0k8V7nbV22+nxWycDQjWTXjJRQ5OBTW/D1IGVOLRLzWAD M80JcFc8p6hd5wJdj3QC8MA= X-Google-Smtp-Source: AGRyM1uhjp+RgS2ynpA11LiieVXvsXwvY7y8TuIgmM3sQHxv0yU0hV6peQrIhc6stvF4D+KvPe7s3Q== X-Received: by 2002:a17:907:3e8c:b0:726:41fa:2866 with SMTP id hs12-20020a1709073e8c00b0072641fa2866mr24122132ejc.562.1656873830342; Sun, 03 Jul 2022 11:43:50 -0700 (PDT) Received: from jernej-laptop.localnet (213-161-3-76.dynamic.telemach.net. [213.161.3.76]) by smtp.gmail.com with ESMTPSA id s10-20020a1709060c0a00b0070beb9401d9sm13390726ejf.171.2022.07.03.11.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 11:43:49 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: samuel@sholland.org, Roman Stratiienko Cc: peron.clem@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, mripard@kernel.org, wens@csie.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Roman Stratiienko Subject: Re: [PATCH v2] clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS Date: Sun, 03 Jul 2022 20:43:48 +0200 Message-ID: <4748270.31r3eYUQgx@jernej-laptop> In-Reply-To: <20220703164514.308622-1-r.stratiienko@gmail.com> References: <20220703164514.308622-1-r.stratiienko@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220703_114352_268439_4B11D5B9 X-CRM114-Status: GOOD ( 25.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dne nedelja, 03. julij 2022 ob 18:45:14 CEST je Roman Stratiienko napisal(a): > Using simple bash script it was discovered that not all CCU registers > can be safely used for DFS, e.g.: > > while true > do > devmem 0x3001030 4 0xb0003e02 > devmem 0x3001030 4 0xb0001e02 > done > > Script above changes the GPU_PLL multiplier register value. While the > script is running, the user should interact with the user interface. > > Using this method the following results were obtained: > | Register | Name | Bits | Values | Result | > | -- | -- | -- | -- | -- | > | 0x3001030 | GPU_PLL.MULT | 15..8 | 20-62 | OK | > | 0x3001030 | GPU_PLL.INDIV | 1 | 0-1 | OK | > | 0x3001030 | GPU_PLL.OUTDIV | 0 | 0-1 | FAIL | > | 0x3001670 | GPU_CLK.DIV | 3..0 | ANY | FAIL | > > DVFS started to work seamlessly once dividers which caused the > glitches were set to fixed values. > > Signed-off-by: Roman Stratiienko > > --- > > Changelog: > > V2: > - Drop changes related to mux > - Drop frequency limiting > - Add unused dividers initialization > --- > drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c > b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 2ddf0a0da526f..1b0205ff24108 > 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c > @@ -95,13 +95,13 @@ static struct ccu_nkmp pll_periph1_clk = { > }, > }; > > +/* For GPU PLL, using an output divider for DFS causes system to fail */ > #define SUN50I_H6_PLL_GPU_REG 0x030 > static struct ccu_nkmp pll_gpu_clk = { > .enable = BIT(31), > .lock = BIT(28), > .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), > .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ > - .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ Having minimum (288 MHz) as per vendor GPU driver and maximum, either max. opp or max. from datasheet is equally good. I know that both are basically limited with opp table, but people like to play with these, so it's good to have them in. > .common = { > .reg = 0x030, > .hw.init = CLK_HW_INIT("pll-gpu", "osc24M", > @@ -294,9 +294,9 @@ static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, > "deinterlace", static SUNXI_CCU_GATE(bus_deinterlace_clk, > "bus-deinterlace", "psi-ahb1-ahb2", 0x62c, BIT(0), 0); > > +/* Keep GPU_CLK divider const to avoid DFS instability. */ > static const char * const gpu_parents[] = { "pll-gpu" }; > -static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, > - 0, 3, /* M */ > +static SUNXI_CCU_MUX_WITH_GATE(gpu_clk, "gpu", gpu_parents, 0x670, > 24, 1, /* mux */ > BIT(31), /* gate */ > CLK_SET_RATE_PARENT); > @@ -1193,6 +1193,16 @@ static int sun50i_h6_ccu_probe(struct platform_device > *pdev) if (IS_ERR(reg)) > return PTR_ERR(reg); > > + /* Force PLL_GPU output divider to 0 */ Divider 0 here > + val = readl(reg + SUN50I_H6_PLL_GPU_REG); > + val &= ~BIT(0); > + writel(val, reg + SUN50I_H6_PLL_GPU_REG); > + > + /* Force GPU_CLK divider to 0 */ and here sounds wrong, since division by zero is not defined. Using 1 is more intuitive and correct, since that's what HW actually uses. Patch looks good otherwise. Best regards, Jernej > + val = readl(reg + gpu_clk.common.reg); > + val &= ~GENMASK(3, 0); > + writel(val, reg + gpu_clk.common.reg); > + > /* Enable the lock bits on all PLLs */ > for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { > val = readl(reg + pll_regs[i]); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel