[PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range

Yakir Yang
2015-10-12T07:20:27Z

On 10/12/2015 02:54 PM, Krzysztof Kozlowski wrote:
> On 12.10.2015 13:29, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>> But presumably Exynos still relies on the DT properties, so take
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> *just add a note that this is v7 of only fifth patch.*
>>
>> Changes in v7:
>> - Back to use the of_property_read_bool() interfacs to provoid backward
>> compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
>> to avoid -EOVERFLOW error (Krzysztof)
>>
>> Changes in v6: None
>> Changes in v5:
>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>> to get the backword timing values. Krzysztof suggest me that driver could use
>> the "of_property_read_bool" to get backword timing values, but that interfacs
>> would modify the original drm_display_mode timing directly (whether those
>> properties exists or not).
>>
>> Changes in v4:
>> - Provide backword compatibility with samsung. (Krzysztof)
>>
>> Changes in v3:
>> - Dynamic parse video timing info from struct drm_display_mode and
>> struct drm_display_info. (Thierry)
>>
>> Changes in v2: None
>>
>> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
>> drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 +-
>> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 14 +-
>> 3 files changed, 103 insertions(+), 61 deletions(-)
>>
> Looks good and backward compatible to me:
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Thanks,

- Yakir

> Best regards,
> Krzysztof
>
>
>
>