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Fri, 16 Jul 2021 23:35:01 +0000 Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=[IPv6:::1]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1m4XMA-00044U-Nq; Sat, 17 Jul 2021 01:34:58 +0200 Message-ID: <47e87f9368b719925dc1794fa73d30c9d2a0a2bd.camel@pengutronix.de> Subject: Re: [PATCH 1/2] soc: imx: gpcv2: Turn domain->pgc into bitfield From: Lucas Stach To: Marek Vasut , linux-arm-kernel@lists.infradead.org Cc: ch@denx.de, Frieder Schrempf , NXP Linux Team , Peng Fan , Shawn Guo Date: Sat, 17 Jul 2021 01:34:57 +0200 In-Reply-To: <62cfb9ca-d4b6-ce4d-bfc5-a00e40535b6e@denx.de> References: <20210630230129.237658-1-marex@denx.de> <62cfb9ca-d4b6-ce4d-bfc5-a00e40535b6e@denx.de> User-Agent: Evolution 3.40.3 (3.40.3-1.fc34) MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210717_003459_587152_5A63CCCC X-CRM114-Status: GOOD ( 18.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marek, Am Freitag, dem 02.07.2021 um 19:48 +0200 schrieb Marek Vasut: > On 7/2/21 7:02 PM, Lucas Stach wrote: > > Am Donnerstag, dem 01.07.2021 um 01:01 +0200 schrieb Marek Vasut: > > > There is currently the MX8MM GPU domain, which is in fact a composite domain > > > for both GPU2D and GPU3D. To correctly configure this domain, it is necessary > > > to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same > > > time. This is currently not possible. > > > > > > Turn the domain->pgc from value into bitfield and use for_each_set_bit() to > > > iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL > > > register array. This way it is possible to configure all GPC_PGC_nCTRL > > > registers required in a particular domain. > > > > > > This is a preparatory patch, no functional change. > > > > Which tree was used to generate this patch? This does not apply on top > > of next or Shawn's imx/drivers tree and from a glance is at least > > missing the 8MN power domains. > > Next with this additional patch > [PATCH] soc: imx: gpcv2: Assert reset before ungating clock I've picked up this patch in the series of i.MX8MM power domain improvements I just sent. Compared to your version I dropped the above base patch and fixed up the i.MX8MN domains. Regards, Lucas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel