From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/2] Documentation: DT: Exynos: Bind SRAM though DT
Date: Fri, 02 May 2014 10:53:44 +0200 [thread overview]
Message-ID: <4811186.9DeISv2WWp@wuerfel> (raw)
In-Reply-To: <1399007180-20680-2-git-send-email-sachin.kamat@linaro.org>
On Friday 02 May 2014 10:36:20 Sachin Kamat wrote:
> + sram at 02020000 {
> + compatible = "mmio-sram";
> + reg = <0x02020000 0x54000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x02020000 0x54000>;
> +
That is actually quite a lot of unused SRAM. Since it came up this
morning in another thread, there may be value in using this for
coherent DMA allocations for some devices. Not sure about how
to best hook this up, but there could be some serious performance
improvements. A typical case would be DMA descriptors for a
gigabit ethernet adapter, which are a pain to maintain on platforms
without cache-coherent DMA.
You could check what drivers you have that call dma_alloc_coherent,
and see if any of them are performance-critical, then hack them
up to use this memory instead as an experiment.
Arnd
next prev parent reply other threads:[~2014-05-02 8:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-02 5:06 [PATCH v2 1/2] ARM: EXYNOS: Map SYSRAM through generic SRAM bindings Sachin Kamat
2014-05-02 5:06 ` [PATCH v2 2/2] Documentation: DT: Exynos: Bind SRAM though DT Sachin Kamat
2014-05-02 8:53 ` Arnd Bergmann [this message]
2014-05-02 17:54 ` [PATCH v2 1/2] ARM: EXYNOS: Map SYSRAM through generic SRAM bindings Tomasz Figa
2014-05-04 15:17 ` Sachin Kamat
-- strict thread matches above, loose matches on Subject: below --
2014-05-06 8:10 Sachin Kamat
2014-05-06 8:10 ` [PATCH v2 2/2] Documentation: DT: Exynos: Bind SRAM though DT Sachin Kamat
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