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Mon, 06 Jan 2025 20:10:54 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 506KArrY029637 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 6 Jan 2025 20:10:53 GMT Received: from [10.216.24.147] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 6 Jan 2025 12:10:50 -0800 Message-ID: <48373519-2867-419d-9f51-e7bd330b311c@quicinc.com> Date: Tue, 7 Jan 2025 01:40:47 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] iommu/arm-smmu-qcom: Only enable stall on smmu-v2 From: Akhil P Oommen To: Rob Clark , CC: , , Robin Murphy , Will Deacon , Rob Clark , Joerg Roedel , "moderated list:ARM SMMU DRIVERS" , open list References: <20250102183232.115279-1-robdclark@gmail.com> <76b822f0-c4c5-4d47-8e0b-c1eee513e228@quicinc.com> Content-Language: en-US In-Reply-To: <76b822f0-c4c5-4d47-8e0b-c1eee513e228@quicinc.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0zZpxDVwd0sIlNSE1sDlJoY_CJ80Fchs X-Proofpoint-GUID: 0zZpxDVwd0sIlNSE1sDlJoY_CJ80Fchs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 mlxlogscore=823 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501060175 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250106_121120_599443_B353C230 X-CRM114-Status: GOOD ( 11.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/3/2025 1:00 AM, Akhil P Oommen wrote: > On 1/3/2025 12:02 AM, Rob Clark wrote: >> From: Rob Clark >> >> On mmu-500, stall-on-fault seems to stall all context banks, causing the >> GMU to misbehave. So limit this feature to smmu-v2 for now. >> >> This fixes an issue with an older mesa bug taking outo the system >> because of GMU going off into the weeds. >> >> What we _think_ is happening is that, if the GPU generates 1000's of >> faults at ~once (which is something that GPUs can be good at), it can >> result in a sufficient number of stalled translations preventing other >> transactions from entering the same TBU. >> >> Signed-off-by: Rob Clark > > Reviewed-by: Akhil P Oommen > Btw, if stall is not enabled, I think there is no point in capturing coredump from adreno pagefault handler. By the time we start coredump, gpu might have switched context. -Akhil. > -Akhil >