[PATCH 00/14] drm: rockchip: Add RV1126 Display (MIPI DSI) support

[PATCH 00/14] drm: rockchip: Add RV1126 Display (MIPI DSI) support

[Jagan Teki]

Rockchip RV1126 has VOP_LITE Display engine which can route
RGB and MIPI DSI display interfaces.

This patchset adds MIPI-DSI pipeline support for RV1126.

Any inputs?
Jagan.

Jagan Teki (14):
  genpd: rockchip: Add PD_VO entry for rv1126
  clk: rockchip: rv1126: Add PD_VO clock tree
  dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126
  phy: rockchip: inno-dsidphy: Add rv1126 support
  dt-bindings: display: rockchip-vop: Document rv1126 vop
  drm/rockchip: vop: Add rv1126 vop_lite support
  dt-bindings: display: rockchip-dw-mipi-dsi: Document rv1126 DSI
  drm/rockchip: dsi: Add rv1126 MIPI DSI support
  ARM: dts: rockchip: rv1126: Add PD_VO entry
  ARM: dts: rockchip: rv1126: Add VOP_LITE support
  ARM: dts: rockchip: rv1126: Add MIPI DSI pipeline
  ARM: dts: rockchip: rv1126: Add Edgeble Neu2 IO DSI overlay
  ARM: dts: rockchip: Add Radxa Display 10HD overlay
  ARM: dts: rockchip: Add Radxa Display 8HD overlay

 .../rockchip/rockchip,dw-mipi-dsi.yaml        |   2 +
 .../display/rockchip/rockchip-vop.yaml        |   1 +
 .../bindings/phy/rockchip,px30-dsi-dphy.yaml  |   1 +
 arch/arm/boot/dts/rockchip/Makefile           |   3 +
 .../boot/dts/rockchip/radxa-display-10hd.dtso |  14 ++
 .../boot/dts/rockchip/radxa-display-8hd.dtso  |  14 ++
 .../rockchip/rv1126-edgeble-neu2-io-dsi.dtso  | 112 +++++++++++++++
 arch/arm/boot/dts/rockchip/rv1126.dtsi        | 130 ++++++++++++++++++
 drivers/clk/rockchip/clk-rv1126.c             |  59 ++++++++
 drivers/genpd/rockchip/pm-domains.c           |   1 +
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  20 +++
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c   |  55 ++++++++
 .../phy/rockchip/phy-rockchip-inno-dsidphy.c  |   3 +
 13 files changed, 415 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/radxa-display-10hd.dtso
 create mode 100644 arch/arm/boot/dts/rockchip/radxa-display-8hd.dtso
 create mode 100644 arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io-dsi.dtso

-- 
2.25.1


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[PATCH 01/14] genpd: rockchip: Add PD_VO entry for rv1126

[Jagan Teki]

PD_VO power-domain entry in RV1126 are connected to
- BIU_VO
- VOP
- RGA
- IEP
- DSIHOST

Add an entry for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: linux-pm@vger.kernel.org
Cc: Ulf Hansson <ulf.hansson@linaro.org>

 drivers/genpd/rockchip/pm-domains.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/genpd/rockchip/pm-domains.c b/drivers/genpd/rockchip/pm-domains.c
index e3de49e671dc..d5d3ecb38283 100644
--- a/drivers/genpd/rockchip/pm-domains.c
+++ b/drivers/genpd/rockchip/pm-domains.c
@@ -976,6 +976,7 @@ static const struct rockchip_domain_info px30_pm_domains[] = {
 static const struct rockchip_domain_info rv1126_pm_domains[] = {
 	[RV1126_PD_VEPU]	= DOMAIN_RV1126("vepu", BIT(2),  BIT(9),  BIT(9), false),
 	[RV1126_PD_VI]		= DOMAIN_RV1126("vi", BIT(4),  BIT(6),  BIT(6),  false),
+	[RV1126_PD_VO]		= DOMAIN_RV1126("vo", BIT(5),  BIT(7),  BIT(7),  false),
 	[RV1126_PD_ISPP]	= DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8),  false),
 	[RV1126_PD_VDPU]	= DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
 	[RV1126_PD_NVM]		= DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11),  false),
-- 
2.25.1


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[PATCH 02/14] clk: rockchip: rv1126: Add PD_VO clock tree

[Jagan Teki]

PD_VO clock tree diagram in RV1126 is connected to
- BIU_VO
- VOP
- RGA
- IEP
- DSIHOST

Add entire PD_VO clock tree for rv1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>

 drivers/clk/rockchip/clk-rv1126.c | 59 +++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c
index 5c6f1ce34a2f..fc19c5522490 100644
--- a/drivers/clk/rockchip/clk-rv1126.c
+++ b/drivers/clk/rockchip/clk-rv1126.c
@@ -175,6 +175,7 @@ PNAME(mux_i2s2_p)			= { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xi
 PNAME(mux_i2s2_out2io_p)		= { "mclk_i2s2", "xin12m" };
 PNAME(mux_gpll_cpll_xin24m_p)		= { "gpll", "cpll", "xin24m" };
 PNAME(mux_audpwm_p)			= { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
+PNAME(mux_dclk_vop_p)			= { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
 PNAME(mux_usb480m_gpll_p)		= { "usb480m", "gpll" };
 PNAME(clk_gmac_src_m0_p)		= { "clk_gmac_div", "clk_gmac_rgmii_m0" };
 PNAME(clk_gmac_src_m1_p)		= { "clk_gmac_div", "clk_gmac_rgmii_m1" };
@@ -259,6 +260,10 @@ static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
 	MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
 			RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
 
+static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata =
+	MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
+	    RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
+
 static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
 	/*
 	 * Clock-Architecture Diagram 2
@@ -714,6 +719,49 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
 			RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
 			RV1126_CLKGATE_CON(11), 1, GFLAGS),
 
+	/*
+	 * Clock-Architecture Diagram 9
+	 */
+	/* PD_VO */
+	COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
+		  RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
+		  RV1126_CLKGATE_CON(14), 0, GFLAGS),
+	COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0,
+			RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
+			RV1126_CLKGATE_CON(14), 1, GFLAGS),
+	COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0,
+			RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
+			RV1126_CLKGATE_CON(14), 2, GFLAGS),
+	GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
+	     RV1126_CLKGATE_CON(14), 6, GFLAGS),
+	GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
+	     RV1126_CLKGATE_CON(14), 7, GFLAGS),
+	COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0,
+		  RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
+		  RV1126_CLKGATE_CON(14), 8, GFLAGS),
+	GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
+	     RV1126_CLKGATE_CON(14), 9, GFLAGS),
+	GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
+	     RV1126_CLKGATE_CON(14), 10, GFLAGS),
+	COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
+		  RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
+		  RV1126_CLKGATE_CON(14), 11, GFLAGS),
+	COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div",
+			  CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0,
+			  RV1126_CLKGATE_CON(14), 12, GFLAGS,
+			  &rv1126_dclk_vop_fracmux),
+	GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
+	     RV1126_CLKGATE_CON(14), 13, GFLAGS),
+	GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
+	     RV1126_CLKGATE_CON(14), 14, GFLAGS),
+	GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
+	     RV1126_CLKGATE_CON(12), 7, GFLAGS),
+	GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
+	     RV1126_CLKGATE_CON(12), 8, GFLAGS),
+	COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0,
+		  RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
+		  RV1126_CLKGATE_CON(12), 9, GFLAGS),
+
 	/*
 	 * Clock-Architecture Diagram 12
 	 */
@@ -905,6 +953,17 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
 	GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
 			RV1126_CLKGATE_CON(9), 3, GFLAGS),
 
+	/*
+	 * Clock-Architecture Diagram 9
+	 */
+	/* PD_VO */
+	GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
+	     RV1126_CLKGATE_CON(14), 3, GFLAGS),
+	GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
+	     RV1126_CLKGATE_CON(14), 4, GFLAGS),
+	GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
+	     RV1126_CLKGATE_CON(14), 5, GFLAGS),
+
 	/*
 	 * Clock-Architecture Diagram 12
 	 */
-- 
2.25.1


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[PATCH 03/14] dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126

[Jagan Teki]

Document a compatible string for the rv1126 dsi-dphy.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: linux-phy@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>

 .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml          | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
index 5c35e5ceec0b..46e64fa293d5 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
@@ -19,6 +19,7 @@ properties:
       - rockchip,rk3128-dsi-dphy
       - rockchip,rk3368-dsi-dphy
       - rockchip,rk3568-dsi-dphy
+      - rockchip,rv1126-dsi-dphy
 
   reg:
     maxItems: 1
-- 
2.25.1


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[PATCH 04/14] phy: rockchip: inno-dsidphy: Add rv1126 support

[Jagan Teki]

Add support for Rockchip RV1126 DSI-DPHY.

The existing 2.5GHz phy timing table added for RK3568 is working
as it is for RV1126 as well.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: linux-phy@lists.infradead.org
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>

 drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
index c879ec69bfd6..6405943a2676 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -770,6 +770,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = {
 	}, {
 		.compatible = "rockchip,rk3568-dsi-dphy",
 		.data = &max_2_5ghz_video_phy_plat_data,
+	}, {
+		.compatible = "rockchip,rv1126-dsi-dphy",
+		.data = &max_2_5ghz_video_phy_plat_data,
 	},
 	{}
 };
-- 
2.25.1


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[PATCH 05/14] dt-bindings: display: rockchip-vop: Document rv1126 vop

[Jagan Teki]

Document the VOP for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: dri-devel@lists.freedesktop.org
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Sandy Huang <hjc@rock-chips.com>
Cc: David Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>

 .../devicetree/bindings/display/rockchip/rockchip-vop.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
index df61cb5f5c54..b339b7e708c6 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
@@ -31,6 +31,7 @@ properties:
       - rockchip,rk3368-vop
       - rockchip,rk3399-vop-big
       - rockchip,rk3399-vop-lit
+      - rockchip,rv1126-vop
 
   reg:
     minItems: 1
-- 
2.25.1


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[PATCH 06/14] drm/rockchip: vop: Add rv1126 vop_lite support

[Jagan Teki]

RV1126 VOP_LITE supports the video output processing ofMIPI DSI,
RGB display interfaces with max output resolution of 1920x1080.

Add support for rv1126 vop.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: dri-devel@lists.freedesktop.org
Cc: Sandy Huang <hjc@rock-chips.com>
Cc: David Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>

 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 55 +++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 7b2805006776..d053ef027552 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -1120,6 +1120,59 @@ static const struct vop_data rk3328_vop = {
 	.max_output = { 4096, 2160 },
 };
 
+static const struct vop_common rv1126_common = {
+	.standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1),
+	.out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16),
+	.dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14),
+	.dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8),
+	.dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7),
+	.dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6),
+	.cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0),
+	.dither_up = VOP_REG(PX30_DSP_CTRL2, 0x1, 2),
+	.dsp_lut_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 5),
+	.gate_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 0),
+};
+
+static const struct vop_modeset rv1126_modeset = {
+	.htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
+	.hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0),
+	.vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
+	.vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0),
+};
+
+static const struct vop_output rv1126_output = {
+	.rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1),
+	.rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2),
+	.rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0),
+	.mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25),
+	.mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26),
+	.mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24),
+};
+
+static const struct vop_misc rv1126_misc = {
+	.global_regdone_en = VOP_REG(PX30_SYS_CTRL2, 0x1, 13),
+};
+
+static const struct vop_win_data rv1126_vop_win_data[] = {
+	{ .base = 0x00, .phy = &px30_win0_data,
+	  .type = DRM_PLANE_TYPE_OVERLAY },
+	{ .base = 0x00, .phy = &px30_win2_data,
+	  .type = DRM_PLANE_TYPE_PRIMARY },
+};
+
+static const struct vop_data rv1126_vop = {
+	.version = VOP_VERSION(2, 0xb),
+	.intr = &px30_intr,
+	.common = &rv1126_common,
+	.modeset = &rv1126_modeset,
+	.output = &rv1126_output,
+	.misc = &rv1126_misc,
+	.win = rv1126_vop_win_data,
+	.win_size = ARRAY_SIZE(rv1126_vop_win_data),
+	.max_output = { 1920, 1080 },
+	.lut_size = 1024,
+};
+
 static const struct of_device_id vop_driver_dt_match[] = {
 	{ .compatible = "rockchip,rk3036-vop",
 	  .data = &rk3036_vop },
@@ -1147,6 +1200,8 @@ static const struct of_device_id vop_driver_dt_match[] = {
 	  .data = &rk3228_vop },
 	{ .compatible = "rockchip,rk3328-vop",
 	  .data = &rk3328_vop },
+	{ .compatible = "rockchip,rv1126-vop",
+	  .data = &rv1126_vop },
 	{},
 };
 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
-- 
2.25.1


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[PATCH 07/14] dt-bindings: display: rockchip-dw-mipi-dsi: Document rv1126 DSI

[Jagan Teki]

Document the MIPI DSI for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: dri-devel@lists.freedesktop.org
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Sandy Huang <hjc@rock-chips.com>
Cc: David Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>

 .../bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml         | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
index 8e8a40879140..ccf79e738fa1 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
@@ -18,6 +18,7 @@ properties:
           - rockchip,rk3288-mipi-dsi
           - rockchip,rk3399-mipi-dsi
           - rockchip,rk3568-mipi-dsi
+          - rockchip,rv1126-mipi-dsi
       - const: snps,dw-mipi-dsi
 
   interrupts:
@@ -77,6 +78,7 @@ allOf:
             enum:
               - rockchip,px30-mipi-dsi
               - rockchip,rk3568-mipi-dsi
+              - rockchip,rv1126-mipi-dsi
 
     then:
       properties:
-- 
2.25.1


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[PATCH 08/14] drm/rockchip: dsi: Add rv1126 MIPI DSI support

[Jagan Teki]

RV1126 MIPI DSI supports V1.2 DPHY with 4 lanes and 1Gbps transfer
rate for lane.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: dri-devel@lists.freedesktop.org
Cc: Sandy Huang <hjc@rock-chips.com>
Cc: David Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>

 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 0100162a73b2..8bafb2a2747f 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -198,6 +198,11 @@
 #define RK3568_DSI1_TURNDISABLE		BIT(2)
 #define RK3568_DSI1_FORCERXMODE		BIT(0)
 
+#define RV1126_GRF_DSIPHY_CON		0x10220
+#define RV1126_DSI_FORCETXSTOPMODE	(0xf << 4)
+#define RV1126_DSI_TURNDISABLE		BIT(2)
+#define RV1126_DSI_FORCERXMODE		BIT(0)
+
 #define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)
 
 enum {
@@ -1651,6 +1656,18 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
 	{ /* sentinel */ }
 };
 
+static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = {
+	{
+		.reg = 0xffb30000,
+		.lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON,
+		.lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE |
+					     RV1126_DSI_FORCERXMODE |
+					     RV1126_DSI_FORCETXSTOPMODE),
+		.max_data_lanes = 4,
+	},
+	{ /* sentinel */ }
+};
+
 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
 	{
 	 .compatible = "rockchip,px30-mipi-dsi",
@@ -1664,6 +1681,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
 	}, {
 	 .compatible = "rockchip,rk3568-mipi-dsi",
 	 .data = &rk3568_chip_data,
+	}, {
+	 .compatible = "rockchip,rv1126-mipi-dsi",
+	 .data = &rv1126_chip_data,
 	},
 	{ /* sentinel */ }
 };
-- 
2.25.1


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[PATCH 09/14] ARM: dts: rockchip: rv1126: Add PD_VO entry

[Jagan Teki]

PD_VO power-domain tree diagram in RV1126 is connected to
- BIU_VO
- VOP
- RGA
- IEP
- DSIHOST

Add PD_VO power-domain entry in RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>

 arch/arm/boot/dts/rockchip/rv1126.dtsi | 39 ++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi
index afa5a68f766f..4d74d3d998ab 100644
--- a/arch/arm/boot/dts/rockchip/rv1126.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi
@@ -125,6 +125,26 @@ qos_sdio: qos@fe86c000 {
 		reg = <0xfe86c000 0x20>;
 	};
 
+	qos_iep: qos@fe8a0000 {
+		compatible = "rockchip,rv1126-qos", "syscon";
+		reg = <0xfe8a0000 0x20>;
+	};
+
+	qos_rga_rd: qos@fe8a0080 {
+		compatible = "rockchip,rv1126-qos", "syscon";
+		reg = <0xfe8a0080 0x20>;
+	};
+
+	qos_rga_wr: qos@fe8a0100 {
+		compatible = "rockchip,rv1126-qos", "syscon";
+		reg = <0xfe8a0100 0x20>;
+	};
+
+	qos_vop: qos@fe8a0180 {
+		compatible = "rockchip,rv1126-qos", "syscon";
+		reg = <0xfe8a0180 0x20>;
+	};
+
 	gic: interrupt-controller@feff0000 {
 		compatible = "arm,gic-400";
 		interrupt-controller;
@@ -170,6 +190,25 @@ power-domain@RV1126_PD_SDIO {
 				pm_qos = <&qos_sdio>;
 				#power-domain-cells = <0>;
 			};
+
+			power-domain@RV1126_PD_VO {
+				reg = <RV1126_PD_VO>;
+				clocks = <&cru ACLK_RGA>,
+					 <&cru HCLK_RGA>,
+					 <&cru CLK_RGA_CORE>,
+					 <&cru ACLK_VOP>,
+					 <&cru HCLK_VOP>,
+					 <&cru DCLK_VOP>,
+					 <&cru PCLK_DSIHOST>,
+					 <&cru ACLK_IEP>,
+					 <&cru HCLK_IEP>,
+					 <&cru CLK_IEP_CORE>;
+				pm_qos = <&qos_rga_rd>,
+					 <&qos_rga_wr>,
+					 <&qos_vop>,
+					 <&qos_iep>;
+				#power-domain-cells = <0>;
+			};
 		};
 	};
 
-- 
2.25.1


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[PATCH 10/14] ARM: dts: rockchip: rv1126: Add VOP_LITE support

[Jagan Teki]

RV1126 VOP_LITE supports the video output processing ofMIPI DSI,
RGB display interfaces with max output resolution of 1920x1080.

Add support for vop in rv1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>

 arch/arm/boot/dts/rockchip/rv1126.dtsi | 42 ++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi
index 4d74d3d998ab..9ccd1bad6229 100644
--- a/arch/arm/boot/dts/rockchip/rv1126.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi
@@ -83,6 +83,11 @@ timer {
 		clock-frequency = <24000000>;
 	};
 
+	display_subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <&vop_out>;
+	};
+
 	xin24m: oscillator {
 		compatible = "fixed-clock";
 		clock-frequency = <24000000>;
@@ -393,6 +398,43 @@ timer0: timer@ff660000 {
 		clock-names = "pclk", "timer";
 	};
 
+	vop: vop@ffb00000 {
+		compatible = "rockchip,rv1126-vop";
+		reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+		reset-names = "axi", "ahb", "dclk";
+		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
+		iommus = <&vop_mmu>;
+		power-domains = <&power RV1126_PD_VO>;
+		status = "disabled";
+
+		vop_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vop_out_rgb: endpoint@0 {
+				reg = <0>;
+			};
+
+			vop_out_dsi: endpoint@1 {
+				reg = <1>;
+			};
+		};
+	};
+
+	vop_mmu: iommu@ffb00f00 {
+		compatible = "rockchip,iommu";
+		reg = <0xffb00f00 0x100>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "aclk", "iface";
+		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+		#iommu-cells = <0>;
+		power-domains = <&power RV1126_PD_VO>;
+		status = "disabled";
+	};
+
 	gmac: ethernet@ffc40000 {
 		compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
 		reg = <0xffc40000 0x4000>;
-- 
2.25.1


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[PATCH 11/14] ARM: dts: rockchip: rv1126: Add MIPI DSI pipeline

[Jagan Teki]

MIPI DSI controller in RV1126 has integrated MIPI D-PHY V1.2
that supports up to 4 lanes with a 4Gbps transfer rate.

Add MIPI DSI pipeline for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>

 arch/arm/boot/dts/rockchip/rv1126.dtsi | 49 ++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi
index 9ccd1bad6229..512cc18762b6 100644
--- a/arch/arm/boot/dts/rockchip/rv1126.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi
@@ -276,6 +276,20 @@ cru: clock-controller@ff490000 {
 		#reset-cells = <1>;
 	};
 
+	dsi_dphy: mipi-dphy@ff4d0000 {
+		compatible = "rockchip,rv1126-dsi-dphy";
+		reg = <0xff4d0000 0x500>;
+		assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>;
+		assigned-clock-rates = <24000000>;
+		clock-names = "ref", "pclk";
+		clocks = <&pmucru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>;
+		#phy-cells = <0>;
+		power-domains = <&power RV1126_PD_VO>;
+		reset-names = "apb";
+		resets = <&cru SRST_DSIPHY_P>;
+		status = "disabled";
+	};
+
 	dmac: dma-controller@ff4e0000 {
 		compatible = "arm,pl330", "arm,primecell";
 		reg = <0xff4e0000 0x4000>;
@@ -420,6 +434,7 @@ vop_out_rgb: endpoint@0 {
 
 			vop_out_dsi: endpoint@1 {
 				reg = <1>;
+				remote-endpoint = <&dsi_in_vop>;
 			};
 		};
 	};
@@ -435,6 +450,40 @@ vop_mmu: iommu@ffb00f00 {
 		status = "disabled";
 	};
 
+	dsi: dsi@ffb30000 {
+		compatible = "rockchip,rv1126-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0xffb30000 0x500>;
+		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk";
+		clocks = <&cru PCLK_DSIHOST>;
+		phy-names = "dphy";
+		phys = <&dsi_dphy>;
+		power-domains = <&power RV1126_PD_VO>;
+		reset-names = "apb";
+		resets = <&cru SRST_DSIHOST_P>;
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				dsi_in_vop: endpoint {
+					remote-endpoint = <&vop_out_dsi>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+			};
+		};
+	};
+
 	gmac: ethernet@ffc40000 {
 		compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
 		reg = <0xffc40000 0x4000>;
-- 
2.25.1


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[PATCH 12/14] ARM: dts: rockchip: rv1126: Add Edgeble Neu2 IO DSI overlay

[Jagan Teki]

Add DSI pipeline for Edgeble Neu2 IO board via DT-overlay

The DSI connector in Edgeble Neu2 IO board support different
resolution panels and those compatible is added in another
DT-overlay.

Add Edgeble Neu2 IO DSI connector DT-overlay.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>

 arch/arm/boot/dts/rockchip/Makefile           |   1 +
 .../rockchip/rv1126-edgeble-neu2-io-dsi.dtso  | 112 ++++++++++++++++++
 2 files changed, 113 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io-dsi.dtso

diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile
index 0f46e18fe275..c8c8e1292650 100644
--- a/arch/arm/boot/dts/rockchip/Makefile
+++ b/arch/arm/boot/dts/rockchip/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb \
 	rv1126-edgeble-neu2-io.dtb \
+	rv1126-edgeble-neu2-io-dsi.dtbo \
 	rk3036-evb.dtb \
 	rk3036-kylin.dtb \
 	rk3066a-bqcurie2.dtb \
diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io-dsi.dtso b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io-dsi.dtso
new file mode 100644
index 000000000000..88431e1e30f8
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io-dsi.dtso
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ *
+ * DT-overlay for Edgeble Neu2 IO DSI Connector.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&{/} {
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 0 25000 0>;
+		enable-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&backlight_en>;
+	};
+
+	vcc_lcd_mipi_2: vcc-lcd-mipi-2-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_lcd_mipi_2";
+		enable-active-high;
+		gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_lcd_mipi_2_en>;
+		regulator-boot-on;
+		vin-supply = <&v3v3_sys>;
+	};
+
+	vcc_1v8_2: vcc-1v8-2-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8_2";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&dsi_dphy {
+	status = "okay";
+};
+
+&dsi {
+	clock-master;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+
+			mipi_out_panel: endpoint {
+				remote-endpoint = <&mipi_in_panel>;
+			};
+		};
+	};
+
+	panel: panel@0 {
+		/* different resolution panels are used, compatibles are in DTO */
+		reg = <0>;
+		vdd-supply = <&vcc_lcd_mipi_2>;
+		vccio-supply = <&vcc_1v8_2>;
+		reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_reset>;
+		backlight = <&backlight>;
+
+		port {
+			mipi_in_panel: endpoint {
+				remote-endpoint = <&mipi_out_panel>;
+			};
+		};
+	};
+};
+
+&pinctrl {
+	lcd {
+		backlight_en: backlight-en {
+			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		lcd_reset: lcd-reset {
+			rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vcc_lcd_mipi_2_en: vcc-lcd-mipi-2-en {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
-- 
2.25.1


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[PATCH 13/14] ARM: dts: rockchip: Add Radxa Display 10HD overlay

[Jagan Teki]

Add compatible string of Radxa Display 10HD via DT-overlay.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>

 arch/arm/boot/dts/rockchip/Makefile                |  1 +
 arch/arm/boot/dts/rockchip/radxa-display-10hd.dtso | 14 ++++++++++++++
 2 files changed, 15 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/radxa-display-10hd.dtso

diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile
index c8c8e1292650..0a275549b213 100644
--- a/arch/arm/boot/dts/rockchip/Makefile
+++ b/arch/arm/boot/dts/rockchip/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+	radxa-display-10hd.dtbo \
 	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb \
 	rv1126-edgeble-neu2-io.dtb \
diff --git a/arch/arm/boot/dts/rockchip/radxa-display-10hd.dtso b/arch/arm/boot/dts/rockchip/radxa-display-10hd.dtso
new file mode 100644
index 000000000000..7393b9417647
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/radxa-display-10hd.dtso
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Radxa Computer Co., Ltd.
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ *
+ * DT-overlay for Radxa Display 10HD compatible.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&panel {
+	compatible = "radxa,display-10hd-ad001", "jadard,jd9365da-h3";
+};
-- 
2.25.1


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[PATCH 14/14] ARM: dts: rockchip: Add Radxa Display 8HD overlay

[Jagan Teki]

Add compatible string of Radxa Display 8HD via DT-overlay.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>

 arch/arm/boot/dts/rockchip/Makefile               |  1 +
 arch/arm/boot/dts/rockchip/radxa-display-8hd.dtso | 14 ++++++++++++++
 2 files changed, 15 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/radxa-display-8hd.dtso

diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile
index 0a275549b213..053d24978f82 100644
--- a/arch/arm/boot/dts/rockchip/Makefile
+++ b/arch/arm/boot/dts/rockchip/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	radxa-display-10hd.dtbo \
+	radxa-display-8hd.dtbo \
 	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb \
 	rv1126-edgeble-neu2-io.dtb \
diff --git a/arch/arm/boot/dts/rockchip/radxa-display-8hd.dtso b/arch/arm/boot/dts/rockchip/radxa-display-8hd.dtso
new file mode 100644
index 000000000000..d42499f8d6b2
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/radxa-display-8hd.dtso
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Radxa Computer Co., Ltd.
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ *
+ * DT-overlay for Radxa Display 8HD compatible.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&panel {
+	compatible = "radxa,display-8hd-ad002", "jadard,jd9365da-h3";
+};
-- 
2.25.1


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Re: [PATCH 01/14] genpd: rockchip: Add PD_VO entry for rv1126

[Heiko Stübner]

Am Montag, 31. Juli 2023, 12:59:59 CEST schrieb Jagan Teki:
> PD_VO power-domain entry in RV1126 are connected to
> - BIU_VO
> - VOP
> - RGA
> - IEP
> - DSIHOST
> 
> Add an entry for it.
> 
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

@Ulf: now that we have a genpd subsystem, I assume you're going
to pick up this patch, right?

Thanks
Heiko

> ---
> Cc: linux-pm@vger.kernel.org
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> 
>  drivers/genpd/rockchip/pm-domains.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/genpd/rockchip/pm-domains.c b/drivers/genpd/rockchip/pm-domains.c
> index e3de49e671dc..d5d3ecb38283 100644
> --- a/drivers/genpd/rockchip/pm-domains.c
> +++ b/drivers/genpd/rockchip/pm-domains.c
> @@ -976,6 +976,7 @@ static const struct rockchip_domain_info px30_pm_domains[] = {
>  static const struct rockchip_domain_info rv1126_pm_domains[] = {
>  	[RV1126_PD_VEPU]	= DOMAIN_RV1126("vepu", BIT(2),  BIT(9),  BIT(9), false),
>  	[RV1126_PD_VI]		= DOMAIN_RV1126("vi", BIT(4),  BIT(6),  BIT(6),  false),
> +	[RV1126_PD_VO]		= DOMAIN_RV1126("vo", BIT(5),  BIT(7),  BIT(7),  false),
>  	[RV1126_PD_ISPP]	= DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8),  false),
>  	[RV1126_PD_VDPU]	= DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
>  	[RV1126_PD_NVM]		= DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11),  false),
> 





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Re: [PATCH 03/14] dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126

[Heiko Stübner]

Am Montag, 31. Juli 2023, 13:00:01 CEST schrieb Jagan Teki:
> Document a compatible string for the rv1126 dsi-dphy.
> 
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>

Acked-by: Heiko Stuebner <heiko@sntech.de>

> ---
> Cc: linux-phy@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: Kishon Vijay Abraham I <kishon@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> 
>  .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml          | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
> index 5c35e5ceec0b..46e64fa293d5 100644
> --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
> @@ -19,6 +19,7 @@ properties:
>        - rockchip,rk3128-dsi-dphy
>        - rockchip,rk3368-dsi-dphy
>        - rockchip,rk3568-dsi-dphy
> +      - rockchip,rv1126-dsi-dphy
>  
>    reg:
>      maxItems: 1
> 





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Re: [PATCH 04/14] phy: rockchip: inno-dsidphy: Add rv1126 support

[Heiko Stübner]

Am Montag, 31. Juli 2023, 13:00:02 CEST schrieb Jagan Teki:
> Add support for Rockchip RV1126 DSI-DPHY.
> 
> The existing 2.5GHz phy timing table added for RK3568 is working
> as it is for RV1126 as well.
> 
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>



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Re: [PATCH 07/14] dt-bindings: display: rockchip-dw-mipi-dsi: Document rv1126 DSI

[Conor Dooley]

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On Mon, Jul 31, 2023 at 04:30:05PM +0530, Jagan Teki wrote:
> Document the MIPI DSI for Rockchip RV1126.
> 
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> ---
> Cc: dri-devel@lists.freedesktop.org
> Cc: devicetree@vger.kernel.org
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Sandy Huang <hjc@rock-chips.com>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> 
>  .../bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml         | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
> index 8e8a40879140..ccf79e738fa1 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
> @@ -18,6 +18,7 @@ properties:
>            - rockchip,rk3288-mipi-dsi
>            - rockchip,rk3399-mipi-dsi
>            - rockchip,rk3568-mipi-dsi
> +          - rockchip,rv1126-mipi-dsi
>        - const: snps,dw-mipi-dsi
>  
>    interrupts:
> @@ -77,6 +78,7 @@ allOf:
>              enum:
>                - rockchip,px30-mipi-dsi
>                - rockchip,rk3568-mipi-dsi
> +              - rockchip,rv1126-mipi-dsi
>  
>      then:
>        properties:
> -- 
> 2.25.1
> 

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Re: [PATCH 05/14] dt-bindings: display: rockchip-vop: Document rv1126 vop

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1446 bytes --]

On Mon, Jul 31, 2023 at 04:30:03PM +0530, Jagan Teki wrote:
> Document the VOP for Rockchip RV1126.
> 
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>

There's no commentary here about compatibility with other, existing,
devices nor did you CC me on the rest of the series. How am I supposed
to know if appending to enum is the right thing to do?

Ditto the other binding.

Thanks,
Conor.

> ---
> Cc: dri-devel@lists.freedesktop.org
> Cc: devicetree@vger.kernel.org
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Sandy Huang <hjc@rock-chips.com>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> 
>  .../devicetree/bindings/display/rockchip/rockchip-vop.yaml       | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
> index df61cb5f5c54..b339b7e708c6 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
> @@ -31,6 +31,7 @@ properties:
>        - rockchip,rk3368-vop
>        - rockchip,rk3399-vop-big
>        - rockchip,rk3399-vop-lit
> +      - rockchip,rv1126-vop
>  
>    reg:
>      minItems: 1
> -- 
> 2.25.1
> 

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Re: [PATCH 05/14] dt-bindings: display: rockchip-vop: Document rv1126 vop

[Jagan Teki]

On Wed, 2 Aug 2023 at 02:37, Conor Dooley <conor@kernel.org> wrote:
>
> On Mon, Jul 31, 2023 at 04:30:03PM +0530, Jagan Teki wrote:
> > Document the VOP for Rockchip RV1126.
> >
> > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>
> There's no commentary here about compatibility with other, existing,
> devices nor did you CC me on the rest of the series. How am I supposed
> to know if appending to enum is the right thing to do?

I had past comments not to add all people in the entire series and add
one relevant developer on respective patches. On that note, I tried to
CC the developers only involved in the respective areas. But, you are
CCed to the DT patch that affected this binding.
"[PATCH 10/14] ARM: dts: rockchip: rv1126: Add VOP_LITE support"

Please let me know if I missed anything.

Thanks,
Jagan.

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Re: [PATCH 05/14] dt-bindings: display: rockchip-vop: Document rv1126 vop

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1302 bytes --]

On Wed, Aug 02, 2023 at 08:07:55PM +0530, Jagan Teki wrote:
> On Wed, 2 Aug 2023 at 02:37, Conor Dooley <conor@kernel.org> wrote:
> >
> > On Mon, Jul 31, 2023 at 04:30:03PM +0530, Jagan Teki wrote:
> > > Document the VOP for Rockchip RV1126.
> > >
> > > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >
> > There's no commentary here about compatibility with other, existing,
> > devices nor did you CC me on the rest of the series. How am I supposed
> > to know if appending to enum is the right thing to do?
> 
> I had past comments not to add all people in the entire series and add
> one relevant developer on respective patches. On that note, I tried to
> CC the developers only involved in the respective areas. But, you are
> CCed to the DT patch that affected this binding.
> "[PATCH 10/14] ARM: dts: rockchip: rv1126: Add VOP_LITE support"

> Please let me know if I missed anything.

I suppose you missed saying in the commit message that this is
incompatible with existing vop implementations? Don't need to CC me on
all patches (although it is useful), but please let the patches explain
themselves if you don't.

Anyway, I went on lore and had a look, so with an improved commit
message,
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.


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Re: (subset) [PATCH 00/14] drm: rockchip: Add RV1126 Display (MIPI DSI) support

[Heiko Stuebner]

On Mon, 31 Jul 2023 16:29:58 +0530, Jagan Teki wrote:
> Rockchip RV1126 has VOP_LITE Display engine which can route
> RGB and MIPI DSI display interfaces.
> 
> This patchset adds MIPI-DSI pipeline support for RV1126.
> 
> Any inputs?
> Jagan.
> 
> [...]

Applied, thanks!

[05/14] dt-bindings: display: rockchip-vop: Document rv1126 vop
        commit: aadbaac84fc95efa800e4c73ae86fefb8c86288b
[06/14] drm/rockchip: vop: Add rv1126 vop_lite support
        commit: 3c3cfcb93f6e6e1cede0cdfe3ec24f16ee108929
[07/14] dt-bindings: display: rockchip-dw-mipi-dsi: Document rv1126 DSI
        commit: 9610f9fdf9a01ddab0479a4d5959d93ce5a4b2d4
[08/14] drm/rockchip: dsi: Add rv1126 MIPI DSI support
        commit: 11fdb231f4127bf60839a63a8c7ed640ebe4751a

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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Re: (subset) [PATCH 00/14] drm: rockchip: Add RV1126 Display (MIPI DSI) support

[Heiko Stuebner]

On Mon, 31 Jul 2023 16:29:58 +0530, Jagan Teki wrote:
> Rockchip RV1126 has VOP_LITE Display engine which can route
> RGB and MIPI DSI display interfaces.
> 
> This patchset adds MIPI-DSI pipeline support for RV1126.
> 
> Any inputs?
> Jagan.
> 
> [...]

Applied, thanks!

[02/14] clk: rockchip: rv1126: Add PD_VO clock tree
        commit: 5c7a71fd82350c2f5828a66a1f2f38306d61cbc7

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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Re: [PATCH 03/14] dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126

[Rob Herring]

On Mon, 31 Jul 2023 16:30:01 +0530, Jagan Teki wrote:
> Document a compatible string for the rv1126 dsi-dphy.
> 
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Cc: linux-phy@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: Kishon Vijay Abraham I <kishon@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> 
>  .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml          | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>


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Re: (subset) [PATCH 00/14] drm: rockchip: Add RV1126 Display (MIPI DSI) support

[Heiko Stuebner]

On Mon, 31 Jul 2023 16:29:58 +0530, Jagan Teki wrote:
> Rockchip RV1126 has VOP_LITE Display engine which can route
> RGB and MIPI DSI display interfaces.
> 
> This patchset adds MIPI-DSI pipeline support for RV1126.
> 
> Any inputs?
> Jagan.
> 
> [...]

Applied, thanks!

[01/14] genpd: rockchip: Add PD_VO entry for rv1126
        commit: 45c5edd7d2728d2614cf84b3d50fa192516881d5

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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Re: [PATCH 01/14] genpd: rockchip: Add PD_VO entry for rv1126

[Heiko Stübner]

Am Montag, 31. Juli 2023, 22:48:45 CEST schrieb Heiko Stübner:
> Am Montag, 31. Juli 2023, 12:59:59 CEST schrieb Jagan Teki:
> > PD_VO power-domain entry in RV1126 are connected to
> > - BIU_VO
> > - VOP
> > - RGA
> > - IEP
> > - DSIHOST
> > 
> > Add an entry for it.
> > 
> > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> 
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> 
> @Ulf: now that we have a genpd subsystem, I assume you're going
> to pick up this patch, right?

Looking at other soc trees, it looks like genpd changes right now are
often still going through these ... so I've gone forward, merged the
genpd shared tag and applied this patch on top in my rockchip drivers
branch.



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Re: (subset) [PATCH 00/14] drm: rockchip: Add RV1126 Display (MIPI DSI) support

[Heiko Stuebner]

On Mon, 31 Jul 2023 16:29:58 +0530, Jagan Teki wrote:
> Rockchip RV1126 has VOP_LITE Display engine which can route
> RGB and MIPI DSI display interfaces.
> 
> This patchset adds MIPI-DSI pipeline support for RV1126.
> 
> Any inputs?
> Jagan.
> 
> [...]

Applied, thanks!

[09/14] ARM: dts: rockchip: rv1126: Add PD_VO entry
        commit: 4fafaed5afcc3a58e982629dbc0471ba9ba8678f
[10/14] ARM: dts: rockchip: rv1126: Add VOP_LITE support
        commit: 1bf0dcb1e2a987a9281ae91f94e10c0de52c4952

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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Re: [PATCH 01/14] genpd: rockchip: Add PD_VO entry for rv1126

[Ulf Hansson]

On Sat, 12 Aug 2023 at 14:57, Heiko Stübner <heiko@sntech.de> wrote:
>
> Am Montag, 31. Juli 2023, 22:48:45 CEST schrieb Heiko Stübner:
> > Am Montag, 31. Juli 2023, 12:59:59 CEST schrieb Jagan Teki:
> > > PD_VO power-domain entry in RV1126 are connected to
> > > - BIU_VO
> > > - VOP
> > > - RGA
> > > - IEP
> > > - DSIHOST
> > >
> > > Add an entry for it.
> > >
> > > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >
> > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> >
> > @Ulf: now that we have a genpd subsystem, I assume you're going
> > to pick up this patch, right?

Yes, that's the intent. At least after v6.6-rc1.

>
> Looking at other soc trees, it looks like genpd changes right now are
> often still going through these ... so I've gone forward, merged the
> genpd shared tag and applied this patch on top in my rockchip drivers
> branch.

That's fine. We are in an intermediate phase, so things are being
queued both via the soc trees and the genpd tree.

I am planning to send a pull-request to Linus for v6.6-rc1 to make
sure the delta that hasn't already been pulled by Arnd gets included
too. If you merge the immutable branch, you should have the necessary
parts.

Kind regards
Uffe

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