From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E67FFC2D0A8 for ; Wed, 23 Sep 2020 15:46:55 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6AAE82223E for ; Wed, 23 Sep 2020 15:46:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Ah480pLE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6AAE82223E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Epd1ja32+ZUPnAUOXMoXVoDfUfXDiheKl/3UFOajB4U=; b=Ah480pLEbbD1zisf8cqi16fo7 ueZz5L/qnSB0M5LnAC8sCHS8X6PVQZMiLXFjnmcZyGINON6b/ZJsRysyREd9AnVEBtEyINtGPBqcZ oi19/eb6q8z75Ge3l0Yv3UE4o68Vlg0035JZc2WLEamTTrSNbn3BsiyB0NAImgyG6xzeoW056RYXJ m4zcekz6DYux70aEOKaZ6bSdbw9lQsKfjPgMQGlzvEp6fISMc1r++sJD7Lui8rQINPCm43krzwnXR RmYrE0C0G3ATeS6NMwYXHXW2rWgm6HzAMsT21yxV5LHDBnSrVKOQ8Ru07JXrXBJlUD/MBrFqUCmmt 1mI/jyWUw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kL6x8-0006Cw-QF; Wed, 23 Sep 2020 15:45:06 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kL6x5-0006Bs-OR for linux-arm-kernel@lists.infradead.org; Wed, 23 Sep 2020 15:45:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5854F113E; Wed, 23 Sep 2020 08:45:02 -0700 (PDT) Received: from [192.168.0.110] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E76AA3F718; Wed, 23 Sep 2020 08:45:00 -0700 (PDT) Subject: Re: [PATCH v6 6/7] arm_pmu: Introduce pmu_irq_ops To: Will Deacon References: <20200819133419.526889-1-alexandru.elisei@arm.com> <20200819133419.526889-7-alexandru.elisei@arm.com> <20200921135510.GM2139@willie-the-truck> From: Alexandru Elisei Message-ID: <48af8175-3908-8de3-783f-c61522e9c6fc@arm.com> Date: Wed, 23 Sep 2020 16:46:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20200921135510.GM2139@willie-the-truck> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200923_114503_910212_2CA2A50F X-CRM114-Status: GOOD ( 22.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, sumit.garg@linaro.org, Julien Thierry , maz@kernel.org, Will Deacon , linux-kernel@vger.kernel.org, swboyd@chromium.org, Julien Thierry , catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On 9/21/20 2:55 PM, Will Deacon wrote: > On Wed, Aug 19, 2020 at 02:34:18PM +0100, Alexandru Elisei wrote: >> From: Julien Thierry >> >> Currently the PMU interrupt can either be a normal irq or a percpu irq. >> Supporting NMI will introduce two cases for each existing one. It becomes >> a mess of 'if's when managing the interrupt. >> >> Define sets of callbacks for operations commonly done on the interrupt. The >> appropriate set of callbacks is selected at interrupt request time and >> simplifies interrupt enabling/disabling and freeing. >> >> Cc: Julien Thierry >> Cc: Will Deacon >> Cc: Mark Rutland >> Signed-off-by: Julien Thierry >> Signed-off-by: Alexandru Elisei >> --- >> drivers/perf/arm_pmu.c | 86 ++++++++++++++++++++++++++++++++++-------- >> 1 file changed, 70 insertions(+), 16 deletions(-) >> >> diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c >> index df352b334ea7..17e5952d21e4 100644 >> --- a/drivers/perf/arm_pmu.c >> +++ b/drivers/perf/arm_pmu.c >> @@ -26,8 +26,46 @@ >> >> #include >> >> +static int armpmu_count_irq_users(const int irq); >> + >> +struct pmu_irq_ops { >> + void (*enable_pmuirq)(unsigned int irq); >> + void (*disable_pmuirq)(unsigned int irq); >> + void (*free_pmuirq)(unsigned int irq, int cpu, void __percpu *devid); >> +}; >> + >> +static void armpmu_free_pmuirq(unsigned int irq, int cpu, void __percpu *devid) >> +{ >> + free_irq(irq, per_cpu_ptr(devid, cpu)); >> +} >> + >> +static const struct pmu_irq_ops pmuirq_ops = { >> + .enable_pmuirq = enable_irq, >> + .disable_pmuirq = disable_irq_nosync, >> + .free_pmuirq = armpmu_free_pmuirq >> +}; >> + >> +static void armpmu_enable_percpu_pmuirq(unsigned int irq) >> +{ >> + enable_percpu_irq(irq, IRQ_TYPE_NONE); >> +} >> + >> +static void armpmu_free_percpu_pmuirq(unsigned int irq, int cpu, >> + void __percpu *devid) >> +{ >> + if (armpmu_count_irq_users(irq) == 1) >> + free_percpu_irq(irq, devid); >> +} >> + >> +static const struct pmu_irq_ops percpu_pmuirq_ops = { >> + .enable_pmuirq = armpmu_enable_percpu_pmuirq, >> + .disable_pmuirq = disable_percpu_irq, >> + .free_pmuirq = armpmu_free_percpu_pmuirq >> +}; >> + >> static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu); >> static DEFINE_PER_CPU(int, cpu_irq); >> +static DEFINE_PER_CPU(const struct pmu_irq_ops *, cpu_irq_ops); > Would it make sense to put this in a structure alongside the irq? It doesn't really work, because we need the irq number to be percpu for armpmu_free_irq() to work correctly. If we have a percpu pointer to a struct, the first cpu that frees the irq will set it to 0, and all subsequent CPUs that share the same struct will read 0 as the irq number, which will trigger the WARN_ON and then return early. > >> >> static inline u64 arm_pmu_event_max_period(struct perf_event *event) >> { >> @@ -544,6 +582,19 @@ static int armpmu_count_irq_users(const int irq) >> return count; >> } >> >> +static const struct pmu_irq_ops *armpmu_find_irq_ops(int irq) >> +{ >> + int cpu; >> + >> + for_each_possible_cpu(cpu) { >> + if (per_cpu(cpu_irq, cpu) == irq >> + && per_cpu(cpu_irq_ops, cpu)) >> + return per_cpu(cpu_irq_ops, cpu); >> + } > nit, but you could make this a bit more readable: > > struct pmu_irq_ops *ops = NULL; > > for_each_possible_cpu(cpu) { > if (per_cpu(cpu_irq, cpu) != irq) > continue; > > ops = per_cpu(cpu_irq_ops, cpu); > if (ops) > break; > } > > return ops; That looks better, I will change it. Thanks, Alex _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel