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From: "Heiko Stübner" <heiko@sntech.de>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Yao Zi <ziyao@disroot.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	Yao Zi <ziyao@disroot.org>
Subject: Re: [PATCH v3 1/5] dt-bindings: clock: Document clock and reset unit of RK3528
Date: Mon, 24 Feb 2025 10:09:29 +0100	[thread overview]
Message-ID: <49730692.MN2xkq1pzW@diego> (raw)
In-Reply-To: <20250217061142.38480-6-ziyao@disroot.org>

Am Montag, 17. Februar 2025, 07:11:42 MEZ schrieb Yao Zi:
> There are two types of clocks in RK3528 SoC, CRU-managed and
> SCMI-managed. Independent IDs are assigned to them.
> 
> For the reset part, differing from previous Rockchip SoCs and
> downstream bindings which embeds register offsets into the IDs, gapless
> numbers starting from zero are used.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  .../bindings/clock/rockchip,rk3528-cru.yaml   |  64 +++
>  .../dt-bindings/clock/rockchip,rk3528-cru.h   | 453 ++++++++++++++++++
>  .../dt-bindings/reset/rockchip,rk3528-cru.h   | 241 ++++++++++
>  3 files changed, 758 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml
>  create mode 100644 include/dt-bindings/clock/rockchip,rk3528-cru.h
>  create mode 100644 include/dt-bindings/reset/rockchip,rk3528-cru.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml
> new file mode 100644
> index 000000000000..5a3ec902351c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip RK3528 Clock and Reset Controller
> +
> +maintainers:
> +  - Yao Zi <ziyao@disroot.org>
> +
> +description: |
> +  The RK3528 clock controller generates the clock and also implements a reset
> +  controller for SoC peripherals. For example, it provides SCLK_UART0 and
> +  PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
> +  module.
> +  Each clock is assigned an identifier, consumer nodes can use it to specify
> +  the clock. All available clock and reset IDs are defined in dt-binding
> +  headers.
> +
> +properties:
> +  compatible:
> +    const: rockchip,rk3528-cru
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:

I do think this needs a
    minItems: 1
    maxItems: 2
or similar.

xin24m is the main oscillator everything else is supplied from, so is
absolutely required, but that gmac0 supply comes from an (probably)
optional clock supply from a mac phy?

So is possibly not available on a system without ethernet hardware?


Heiko




  parent reply	other threads:[~2025-02-24  9:31 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-17  6:11 [PATCH v3 0/5] Support clock and reset unit of Rockchip RK3528 Yao Zi
2025-02-17  6:11 ` [PATCH v3 1/5] dt-bindings: clock: Document clock and reset unit of RK3528 Yao Zi
2025-02-17 11:16   ` Krzysztof Kozlowski
2025-02-24  9:09   ` Heiko Stübner [this message]
2025-02-24 17:35     ` Yao Zi
2025-02-17  6:11 ` [PATCH v3 2/5] clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE Yao Zi
2025-02-17  6:11 ` [PATCH v3 3/5] clk: rockchip: Add clock controller driver for RK3528 SoC Yao Zi
2025-02-17  6:11 ` [PATCH v3 4/5] arm64: dts: rockchip: Add clock generators " Yao Zi
2025-02-17  6:11 ` [PATCH v3 5/5] arm64: dts: rockchip: Add UART clocks " Yao Zi
2025-02-26 19:49 ` [PATCH v3 0/5] Support clock and reset unit of Rockchip RK3528 Heiko Stuebner

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