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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b02d684dsm24494145e9.16.2025.02.21.10.10.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 10:10:34 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Ulf Hansson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: David Airlie , Simona Vetter , Boris Brezillon , Steven Price , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-pm@vger.kernel.org Subject: Re: [PATCH 2/5] pmdomain: sunxi: add H6 PRCM PPU driver Date: Fri, 21 Feb 2025 19:10:33 +0100 Message-ID: <4987742.31r3eYUQgx@jernej-laptop> In-Reply-To: <20250221005802.11001-3-andre.przywara@arm.com> References: <20250221005802.11001-1-andre.przywara@arm.com> <20250221005802.11001-3-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_101037_113589_8E44985F X-CRM114-Status: GOOD ( 37.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dne petek, 21. februar 2025 ob 01:57:59 Srednjeevropski standardni =C4=8Das= je Andre Przywara napisal(a): > The Allwinner Power Reset Clock Management (RPCM) block contains a few > bits that control some power domains. The most prominent one is the one > for the Mali GPU. On the Allwinner H6 this domain is enabled at reset, so > we didn't care about it so far, but the H616 defaults to it being disable= d. >=20 > Add a power domain driver for those bits. Some BSP code snippets and > some spare documentation describe three bits, slightly different between > the H6 and H616, so add three power domains for each SoC, connected to > their compatible string. >=20 > Signed-off-by: Andre Przywara > --- > drivers/pmdomain/sunxi/Kconfig | 10 + > drivers/pmdomain/sunxi/Makefile | 1 + > drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c | 191 ++++++++++++++++++++ > 3 files changed, 202 insertions(+) > create mode 100644 drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c >=20 > diff --git a/drivers/pmdomain/sunxi/Kconfig b/drivers/pmdomain/sunxi/Kcon= fig > index 17781bf8d86d7..43eecb3ea9819 100644 > --- a/drivers/pmdomain/sunxi/Kconfig > +++ b/drivers/pmdomain/sunxi/Kconfig > @@ -8,3 +8,13 @@ config SUN20I_PPU > help > Say y to enable the PPU power domain driver. This saves power > when certain peripherals, such as the video engine, are idle. > + > +config SUN50I_H6_PRCM_PPU > + tristate "Allwinner H6 PRCM power domain driver" > + depends on ARCH_SUNXI || COMPILE_TEST > + depends on PM > + select PM_GENERIC_DOMAINS > + help > + Say y to enable the Allwinner H6/H616 PRCM power domain driver. > + This is required to enable the Mali GPU in the H616 SoC, it is > + optional for the H6. > diff --git a/drivers/pmdomain/sunxi/Makefile b/drivers/pmdomain/sunxi/Mak= efile > index ec1d7a2fb21db..c1343e1237599 100644 > --- a/drivers/pmdomain/sunxi/Makefile > +++ b/drivers/pmdomain/sunxi/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0-only > obj-$(CONFIG_SUN20I_PPU) +=3D sun20i-ppu.o > +obj-$(CONFIG_SUN50I_H6_PRCM_PPU) +=3D sun50i-h6-prcm-ppu.o > diff --git a/drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c b/drivers/pmdoma= in/sunxi/sun50i-h6-prcm-ppu.c > new file mode 100644 > index 0000000000000..1c6b0c78b222d > --- /dev/null > +++ b/drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c > @@ -0,0 +1,191 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) Arm Ltd. 2024 > + * > + * Allwinner H6/H616 PRCM power domain driver. > + * This covers a few registers inside the PRCM (Power Reset Clock Manage= ment) > + * block that control some power rails, most prominently for the Mali GP= U. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* > + * The PRCM block covers multiple devices, starting with some clocks, > + * then followed by the power rails. > + * The clocks are covered by a different driver, so this driver's MMIO r= ange > + * starts later in the PRCM MMIO frame, not at the beginning of it. > + * To keep the register offsets consistent with other PRCM documentation, > + * express the registers relative to the beginning of the whole PRCM, and > + * subtract the PPU offset this driver is bound to. > + */ > +#define PD_H6_PPU_OFFSET 0x250 > +#define PD_H6_VDD_SYS_REG 0x250 > +#define PD_H616_ANA_VDD_GATE BIT(4) > +#define PD_H6_CPUS_VDD_GATE BIT(3) > +#define PD_H6_AVCC_VDD_GATE BIT(2) > +#define PD_H6_GPU_REG 0x254 > +#define PD_H6_GPU_GATE BIT(0) > + > +struct sun50i_h6_ppu_pd { > + struct generic_pm_domain genpd; > + void __iomem *reg; > + u32 gate_mask; > + bool negated; > +}; > + > +#define FLAG_PPU_ALWAYS_ON BIT(0) > +#define FLAG_PPU_NEGATED BIT(1) > + > +struct sun50i_h6_ppu_desc { > + const char *name; > + u32 offset; > + u32 mask; > + unsigned int flags; > +}; > + > +struct sun50i_h6_ppu_desc sun50i_h6_ppus[] =3D { > + { "AVCC", PD_H6_VDD_SYS_REG, PD_H6_AVCC_VDD_GATE }, > + { "CPUS", PD_H6_VDD_SYS_REG, PD_H6_CPUS_VDD_GATE }, > + { "GPU", PD_H6_GPU_REG, PD_H6_GPU_GATE }, > + {} > +}; > + > +struct sun50i_h6_ppu_desc sun50i_h616_ppus[] =3D { > + { "PLL", PD_H6_VDD_SYS_REG, PD_H6_AVCC_VDD_GATE, > + FLAG_PPU_ALWAYS_ON | FLAG_PPU_NEGATED }, > + { "ANA", PD_H6_VDD_SYS_REG, PD_H616_ANA_VDD_GATE, FLAG_PPU_ALWAYS_ON }, > + { "GPU", PD_H6_GPU_REG, PD_H6_GPU_GATE, FLAG_PPU_NEGATED }, > + {} > +}; > +#define to_sun50i_h6_ppu_pd(_genpd) \ > + container_of(_genpd, struct sun50i_h6_ppu_pd, genpd) > + > +static bool sun50i_h6_ppu_power_status(const struct sun50i_h6_ppu_pd *pd) > +{ > + bool bit =3D readl(pd->reg) & pd->gate_mask; > + > + return bit ^ pd->negated; > +} > + > +static int sun50i_h6_ppu_pd_set_power(const struct sun50i_h6_ppu_pd *pd, > + bool set_bit) > +{ > + u32 reg =3D readl(pd->reg); > + > + if (set_bit) > + writel(reg | pd->gate_mask, pd->reg); > + else > + writel(reg & ~pd->gate_mask, pd->reg); > + > + return 0; > +} > + > +static int sun50i_h6_ppu_pd_power_on(struct generic_pm_domain *genpd) > +{ > + const struct sun50i_h6_ppu_pd *pd =3D to_sun50i_h6_ppu_pd(genpd); > + > + return sun50i_h6_ppu_pd_set_power(pd, !pd->negated); > +} > + > +static int sun50i_h6_ppu_pd_power_off(struct generic_pm_domain *genpd) > +{ > + const struct sun50i_h6_ppu_pd *pd =3D to_sun50i_h6_ppu_pd(genpd); > + > + return sun50i_h6_ppu_pd_set_power(pd, pd->negated); > +} > + > +static int sun50i_h6_ppu_probe(struct platform_device *pdev) > +{ > + struct device *dev =3D &pdev->dev; > + struct genpd_onecell_data *ppu; > + struct sun50i_h6_ppu_pd *pds; > + const struct sun50i_h6_ppu_desc *desc; > + void __iomem *base; > + int ret, i, count; > + > + desc =3D of_device_get_match_data(dev); > + if (!desc) > + return -EINVAL; > + > + for (count =3D 0; desc[count].name; count++) > + ; > + > + pds =3D devm_kcalloc(dev, count, sizeof(*pds), GFP_KERNEL); > + if (!pds) > + return -ENOMEM; > + > + ppu =3D devm_kzalloc(dev, sizeof(*ppu), GFP_KERNEL); > + if (!ppu) > + return -ENOMEM; > + > + ppu->num_domains =3D count; > + ppu->domains =3D devm_kcalloc(dev, count, sizeof(*ppu->domains), > + GFP_KERNEL); > + if (!ppu->domains) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, ppu); > + > + base =3D devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + for (i =3D 0; i < count; i++) { > + struct sun50i_h6_ppu_pd *pd =3D &pds[i]; > + > + pd->genpd.name =3D desc[i].name; > + pd->genpd.power_off =3D sun50i_h6_ppu_pd_power_off; > + pd->genpd.power_on =3D sun50i_h6_ppu_pd_power_on; > + if (desc[i].flags & FLAG_PPU_ALWAYS_ON) > + pd->genpd.flags =3D GENPD_FLAG_ALWAYS_ON; > + pd->negated =3D !!(desc[i].flags & FLAG_PPU_NEGATED); > + pd->reg =3D base + desc[i].offset - PD_H6_PPU_OFFSET; > + pd->gate_mask =3D desc[i].mask; > + > + ret =3D pm_genpd_init(&pd->genpd, NULL, > + !sun50i_h6_ppu_power_status(pd)); > + if (ret) { > + dev_warn(dev, "Failed to add GPU power domain: %d\n", ret); I suppose you want to replace "GPU" with desc[i].name. Otherwise it looks good to me, but I'd like to hear a comment from genpd ma= intainers. Best regards, Jernej > + return ret; > + } > + ppu->domains[i] =3D &pd->genpd; > + } > + > + ret =3D of_genpd_add_provider_onecell(dev->of_node, ppu); > + if (ret) > + dev_warn(dev, "Failed to add provider: %d\n", ret); > + > + return 0; > +} > + > +static const struct of_device_id sun50i_h6_ppu_of_match[] =3D { > + { .compatible =3D "allwinner,sun50i-h6-prcm-ppu", > + .data =3D &sun50i_h6_ppus }, > + { .compatible =3D "allwinner,sun50i-h616-prcm-ppu", > + .data =3D &sun50i_h616_ppus }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, sun50i_h6_ppu_of_match); > + > +static struct platform_driver sun50i_h6_ppu_driver =3D { > + .probe =3D sun50i_h6_ppu_probe, > + .driver =3D { > + .name =3D "sun50i-h6-prcm-ppu", > + .of_match_table =3D sun50i_h6_ppu_of_match, > + /* Power domains cannot be removed while they are in use. */ > + .suppress_bind_attrs =3D true, > + }, > +}; > +module_platform_driver(sun50i_h6_ppu_driver); > + > +MODULE_AUTHOR("Andre Przywara "); > +MODULE_DESCRIPTION("Allwinner H6 PRCM power domain driver"); > +MODULE_LICENSE("GPL"); >=20