[PATCH] ep93xx: introduce clk parent

[ryan@bluewatersys.com (Ryan Mallon)]

H Hartley Sweeten wrote:
> The clock generation system in the ep93xx uses two external oscillator's
> and two internal PLLs to derive all the internal clocks.  Many of these
> internal clocks can be stopped to save power.
> 
> This introduces a "parent" hierarchy for the clocks so that the users
> count can be correctly tracked for power management.
> 
> The "parent" for the video clock can either be one of the PLL outputs
> or the external oscillator.  In order to correctly track the "parent"
> for the video clock calc_clk_div() needed to be modified.  It now
> returns an error code if the desired rate cannot be generated.
> 
> Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
> Cc: Ryan Mallon <ryan@bluewatersys.com>
> 
> ---
> 

Acked-by: Ryan Mallon <ryan@bluewatersys.com>

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