[RFC PATCH 06/12] arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.

[RFC PATCH 06/12] arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.

[Daniel Walker]

From: Larry Bassel <lbassel@quicinc.com>

This change improves the following LMBench benchmarks
by over 15%:

System Call Latency
Signal Handling Latency
Fault Latency
Inter-process Communication Latency
Inter-process Communication Bandwidth
Random Number Generation Latency

Acked-by: Steve Muckle <smuckle@quicinc.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shilimkar, Santosh <santosh.shilimkar@ti.com>
Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Bohan, Michael <mbohan@quicinc.com>
Signed-off-by: Larry Bassel <lbassel@quicinc.com>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
---
 arch/arm/mm/proc-v7.S |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a..3ca5d29 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -2,6 +2,7 @@
  *  linux/arch/arm/mm/proc-v7.S
  *
  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *  Copyright (c) 2009, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -242,6 +243,10 @@ __v7_setup:
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
+#ifdef CONFIG_ARCH_MSM_SCORPION
+	mov     r0, #0x77
+	mcr     p15, 3, r0, c15, c0, 3          @ set L2CR1
+#endif
 	/*
 	 * Memory region attributes with SCTLR.TRE=1
 	 *
-- 
1.6.3.3

[RFC PATCH 06/12] arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.

[Nicolas Pitre]

On Thu, 28 Jan 2010, Daniel Walker wrote:

> From: Larry Bassel <lbassel@quicinc.com>
> 
> This change improves the following LMBench benchmarks
> by over 15%:
> 
> System Call Latency
> Signal Handling Latency
> Fault Latency
> Inter-process Communication Latency
> Inter-process Communication Bandwidth
> Random Number Generation Latency
> 
> Acked-by: Steve Muckle <smuckle@quicinc.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Shilimkar, Santosh <santosh.shilimkar@ti.com>
> Cc: Nicolas Pitre <nico@fluxnic.net>
> Cc: Bohan, Michael <mbohan@quicinc.com>
> Signed-off-by: Larry Bassel <lbassel@quicinc.com>
> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
> ---
>  arch/arm/mm/proc-v7.S |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 7aaf88a..3ca5d29 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -2,6 +2,7 @@
>   *  linux/arch/arm/mm/proc-v7.S
>   *
>   *  Copyright (C) 2001 Deep Blue Solutions Ltd.
> + *  Copyright (c) 2009, Code Aurora Forum. All rights reserved.

Do you really think the addition of only 4 lines in a file that contains 
348 lines justifies the addition of such copyright notice?  What would 
the kernel source looks like if everyone adding/modifying 4 lines in 
every random files did the same?

Just a thought.

>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
> @@ -242,6 +243,10 @@ __v7_setup:
>  	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
>  	mov	r10, #0x1f			@ domains 0, 1 = manager
>  	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
> +#ifdef CONFIG_ARCH_MSM_SCORPION
> +	mov     r0, #0x77
> +	mcr     p15, 3, r0, c15, c0, 3          @ set L2CR1
> +#endif
>  	/*
>  	 * Memory region attributes with SCTLR.TRE=1
>  	 *
> -- 
> 1.6.3.3
> 

[RFC PATCH 06/12] arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.

[Daniel Walker]

On Thu, 2010-01-28 at 20:06 -0500, Nicolas Pitre wrote:

> Do you really think the addition of only 4 lines in a file that contains 
> 348 lines justifies the addition of such copyright notice?  What would 
> the kernel source looks like if everyone adding/modifying 4 lines in 
> every random files did the same?
> 
> Just a thought.
> 

I don't disagree with you. It's actually a legal policy .. I can ask
some questions regard it tho ..

Daniel

[RFC PATCH 06/12] arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.

[Nicolas Pitre]

On Thu, 28 Jan 2010, Daniel Walker wrote:

> On Thu, 2010-01-28 at 20:06 -0500, Nicolas Pitre wrote:
> 
> > Do you really think the addition of only 4 lines in a file that contains 
> > 348 lines justifies the addition of such copyright notice?  What would 
> > the kernel source looks like if everyone adding/modifying 4 lines in 
> > every random files did the same?
> > 
> > Just a thought.
> > 
> 
> I don't disagree with you. It's actually a legal policy .. I can ask
> some questions regard it tho ..

The legalese is usually satisfied by the attribution and the meaning 
attached to the SOB carried in the commit message.


Nicolas

[RFC PATCH 06/12] arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.

[Bryan Huntsman]

> I don't disagree with you. It's actually a legal policy .. I can ask
> some questions regard it tho ..
> 
> Daniel

It's fine to remove the Code Aurora copyright from this patch.  As 
Nicolas noted, it shouldn't have been in there in the first place.

- Bryan

[RFC PATCH 06/12] arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.

[Pavel Machek]

Hi!

> From: Larry Bassel <lbassel@quicinc.com>
> 
> This change improves the following LMBench benchmarks
> by over 15%:

But what does this change do?

> @@ -242,6 +243,10 @@ __v7_setup:
>  	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
>  	mov	r10, #0x1f			@ domains 0, 1 = manager
>  	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
> +#ifdef CONFIG_ARCH_MSM_SCORPION
> +	mov     r0, #0x77
> +	mcr     p15, 3, r0, c15, c0, 3          @ set L2CR1
> +#endif

...probably should be explained here...

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[RFC PATCH 06/12] arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.

[Catalin Marinas]

On Thu, 2010-01-28 at 22:59 +0000, Daniel Walker wrote:
> @@ -242,6 +243,10 @@ __v7_setup:
>         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
>         mov     r10, #0x1f                      @ domains 0, 1 = manager
>         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
> +#ifdef CONFIG_ARCH_MSM_SCORPION
> +       mov     r0, #0x77
> +       mcr     p15, 3, r0, c15, c0, 3          @ set L2CR1
> +#endif

I thought we want to move these out of the kernel into the boot loader
(or boot monitor or bios or whatever it's called).

-- 
Catalin

[RFC PATCH 06/12] arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.

[Daniel Walker]

On Fri, 2010-01-29 at 10:59 +0000, Catalin Marinas wrote:
> On Thu, 2010-01-28 at 22:59 +0000, Daniel Walker wrote:
> > @@ -242,6 +243,10 @@ __v7_setup:
> >         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
> >         mov     r10, #0x1f                      @ domains 0, 1 = manager
> >         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
> > +#ifdef CONFIG_ARCH_MSM_SCORPION
> > +       mov     r0, #0x77
> > +       mcr     p15, 3, r0, c15, c0, 3          @ set L2CR1
> > +#endif
> 
> I thought we want to move these out of the kernel into the boot loader
> (or boot monitor or bios or whatever it's called).

I left it in cause it still felt like an open question the last time I
submitted it ..

Honestly, I feel like we should keep as much control in Linux as
possible.. Having it in Linux is just one place for it to get screwed
up, vs. having it in many different boot loaders.

Daniel