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From: gilles.chanteperdrix@xenomai.org (Gilles Chanteperdrix)
To: linux-arm-kernel@lists.infradead.org
Subject: Some benchmarks on ARM
Date: Sun, 04 Jul 2010 11:47:34 +0200	[thread overview]
Message-ID: <4C3058B6.1060103@xenomai.org> (raw)
In-Reply-To: <20100703202845.GA23954@n2100.arm.linux.org.uk>

Russell King - ARM Linux wrote:
> On Sat, Jul 03, 2010 at 10:08:29PM +0200, Gilles Chanteperdrix wrote:
>> Robert Schwebel wrote:
>>> Hi,
>>>
>>> We have recently made some benchmarks, in order to get a little bit
>>> better fealing about where ARM cpus are today, especially when it comes
>>> to the "recent" ones, and in comparism to the Atom. So we collected a
>>> few benchmarks (most from lmbench) and did some actual measurements.
>>>
>>> Here is a little article:
>>> http://www.pengutronix.de/development/kernel/arm-benchmarks-20100702_en.html
>>>
>>> I'm pretty sure that there are quite a few things where people on ALKML
>>> have good ideas where the effects come from or how to improve the
>>> methodology - so I'd be glad to get some feedback from the community!
>>>
>>> All measurements have been done on 2.6.34.
>> The context switch time for PXA270 looks really suspicious. The worst
>> case context switch time of an AT91RM9200, an armv4 running at 180MHz,
>> is less than 300us, so, I doubt that the context switch time of a PXA
>> can be that worse.
> 
> The measurement is of the thread and MM switch time, which'll involve
> cache flushes on <= ARMv5.
> 
> On PXA, we have to 'read' (via means of D cache line allocations) 32K
> of data into the cache in order to cause the existing data to be written
> out.  These are done from a range of addresses which don't exist in the
> page tables, and so should not cause any bus activity other than the
> write-outs.  However, the cache still has to interact with the MMU to
> try to fetch the requested data - which probably consumes some cycles.
> 
> ARM920 on the other hand can walk through every cache line and clean+
> invalidate it.  It has 64 lines in each segment, and 8 segments, each
> line 32 bytes long, which gives a cache size of 16K.
> 
> I'd therefore expect ARM920's cache flushing to be quicker (in terms
> of cycles consumed) than PXA.

Ok. But, the cache flush only accounts for only around 70us on the 290us
of context switch time of the AT91RM9200. Lokks like the cache flush on
PXA would have to be a lot longer.

-- 
					    Gilles.

  reply	other threads:[~2010-07-04  9:47 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-07-02 18:02 Some benchmarks on ARM Robert Schwebel
2010-07-02 20:34 ` Magnus Lilja
2010-07-05 12:24   ` Marc Kleine-Budde
2010-07-05 14:00     ` Russell King - ARM Linux
2010-07-05 15:14       ` Måns Rullgård
2010-07-03  5:44 ` Nicolas Pitre
2010-07-05 13:04   ` Maurus Cuelenaere
2010-07-05 13:23     ` Robert Schwebel
2010-07-05 13:31       ` Mike Rapoport
2010-07-05 13:42         ` Robert Schwebel
2010-07-05 14:15           ` Nicolas Pitre
2010-07-06  5:36             ` Mike Rapoport
2010-07-05 13:53         ` Marek Vasut
2010-07-06 14:02       ` Pavel Machek
2010-07-03 19:48 ` Baruch Siach
2010-07-03 20:08 ` Gilles Chanteperdrix
2010-07-03 20:28   ` Russell King - ARM Linux
2010-07-04  9:47     ` Gilles Chanteperdrix [this message]
2010-07-05  8:51 ` Colin Tuckley
2010-07-05 12:29   ` Marc Kleine-Budde
2010-07-05 12:41   ` Marc Kleine-Budde
2010-07-05 12:45     ` Marc Kleine-Budde
2010-07-29 16:54 ` Robert Schwebel
2010-07-30 10:19   ` Richard Cochran
2010-07-30 11:40     ` Gilles Chanteperdrix
2010-08-19  5:36 ` shiraz hashim
2010-08-19  6:28   ` Robert Schwebel
2010-08-19  7:10     ` shiraz hashim
  -- strict thread matches above, loose matches on Subject: below --
2010-07-30 14:47 Tomasz Stanislawski

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