[PATCH V2 0/3] ARM: S5PV310: Add EINT support

[PATCH V2 0/3] ARM: S5PV310: Add EINT support

[Jongsun Han]

This is a sencond version of patches adding EINT for S5PV310/C210

Changes since v1:
- Replace some functions with macro define
- Add register definition and macro

[PATCH 1/2] ARM: S5PV310: Add the definition for external interrupt
[PATCH 2/2] ARM: S5PV310: Add external interrupt support

[PATCH 1/2] ARM: S5PV310: Add the definition for external interrupt

[Jongsun Han]

This patch adds the definition for both IRQs and GPIO registers for
external interrupts.

Signed-off-by: Jongsun Han <jongsun.han@samsung.com>
---
 arch/arm/mach-s5pv310/include/mach/irqs.h      |   16 +++++++++
 arch/arm/mach-s5pv310/include/mach/regs-gpio.h |   42 ++++++++++++++++++++++++
 2 files changed, 58 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv310/include/mach/regs-gpio.h

diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index fa7a8a3..99e7dad 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -85,6 +85,22 @@
 
 #define IRQ_ONENAND_AUDI	COMBINER_IRQ(34, 0)
 
+#define IRQ_EINT4		COMBINER_IRQ(37, 0)
+#define IRQ_EINT5		COMBINER_IRQ(37, 1)
+#define IRQ_EINT6		COMBINER_IRQ(37, 2)
+#define IRQ_EINT7		COMBINER_IRQ(37, 3)
+#define IRQ_EINT8		COMBINER_IRQ(38, 0)
+
+#define IRQ_EINT9		COMBINER_IRQ(38, 1)
+#define IRQ_EINT10		COMBINER_IRQ(38, 2)
+#define IRQ_EINT11		COMBINER_IRQ(38, 3)
+#define IRQ_EINT12		COMBINER_IRQ(38, 4)
+#define IRQ_EINT13		COMBINER_IRQ(38, 5)
+#define IRQ_EINT14		COMBINER_IRQ(38, 6)
+#define IRQ_EINT15		COMBINER_IRQ(38, 7)
+
+#define IRQ_EINT16_31		COMBINER_IRQ(39, 0)
+
 #define MAX_COMBINER_NR		40
 
 #define S5P_IRQ_EINT_BASE	COMBINER_IRQ(MAX_COMBINER_NR, 0)
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
new file mode 100644
index 0000000..82e9e0c
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * S5PV310 - GPIO (including EINT) register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#define S5PV310_EINT40CON		(S5P_VA_GPIO2 + 0xE00)
+#define S5P_EINT_CON(x)			(S5PV310_EINT40CON + ((x) * 0x4))
+
+#define S5PV310_EINT40FLTCON0		(S5P_VA_GPIO2 + 0xE80)
+#define S5P_EINT_FLTCON(x)		(S5PV310_EINT40FLTCON0 + ((x) * 0x4))
+
+#define S5PV310_EINT40MASK		(S5P_VA_GPIO2 + 0xF00)
+#define S5P_EINT_MASK(x)		(S5PV310_EINT40MASK + ((x) * 0x4))
+
+#define S5PV310_EINT40PEND		(S5P_VA_GPIO2 + 0xF40)
+#define S5P_EINT_PEND(x)		(S5PV310_EINT40PEND + ((x) * 0x4))
+
+#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
+
+#define eint_irq_to_bit(irq)		(1 << (EINT_OFFSET(irq) & 0x7))
+
+#define EINT_MODE			S3C_GPIO_SFN(0xf)
+
+#define EINT_GPIO_0(x)			S5PV310_GPX0(x)
+#define EINT_GPIO_1(x)			S5PV310_GPX1(x)
+#define EINT_GPIO_2(x)			S5PV310_GPX2(x)
+#define EINT_GPIO_3(x)			S5PV310_GPX3(x)
+
+#endif /* __ASM_ARCH_REGS_GPIO_H */
-- 
1.6.3.3

[PATCH 2/2] ARM: S5PV310: Add external interrupt support

[Jongsun Han]

All external interrupts are transferred to GIC through interrupt combiner.

Signed-off-by: Jongsun Han <jongsun.han@samsung.com>
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
---
 arch/arm/mach-s5pv310/Makefile   |    2 +-
 arch/arm/mach-s5pv310/irq-eint.c |  228 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 229 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-s5pv310/irq-eint.c

diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index 97aba6d..6a8a1ef 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -13,7 +13,7 @@ obj-				:=
 # Core support for S5PV310 system
 
 obj-$(CONFIG_CPU_S5PV310)	+= cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_S5PV310)	+= setup-i2c0.o time.o gpiolib.o
+obj-$(CONFIG_CPU_S5PV310)	+= setup-i2c0.o time.o gpiolib.o irq-eint.o
 obj-$(CONFIG_CPU_FREQ)		+= cpufreq.o
 
 obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c
new file mode 100644
index 0000000..ac955df
--- /dev/null
+++ b/arch/arm/mach-s5pv310/irq-eint.c
@@ -0,0 +1,228 @@
+/* linux/arch/arm/mach-s5pv310/irq-eint.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * S5PV310 - IRQ EINT support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/gpio.h>
+
+#include <plat/pm.h>
+#include <plat/cpu.h>
+#include <plat/gpio-cfg.h>
+
+#include <mach/regs-gpio.h>
+
+static DEFINE_SPINLOCK(eint_lock);
+
+static unsigned int s5pv310_get_irq_nr(unsigned int number)
+{
+	u32 ret = 0;
+
+	switch (number) {
+	case 0 ... 3:
+		ret = (number + IRQ_EINT0);
+		break;
+	case 4 ... 7:
+		ret = (number + (IRQ_EINT4 - 4));
+		break;
+	case 8 ... 15:
+		ret = (number + (IRQ_EINT8 - 8));
+		break;
+	default:
+		printk(KERN_ERR "number available : %d\n", number);
+	}
+
+	return ret;
+}
+
+static inline void s5pv310_irq_eint_mask(unsigned int irq)
+{
+	u32 mask;
+
+	spin_lock(&eint_lock);
+	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
+	mask |= eint_irq_to_bit(irq);
+	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+	spin_unlock(&eint_lock);
+}
+
+static void s5pv310_irq_eint_unmask(unsigned int irq)
+{
+	u32 mask;
+
+	spin_lock(&eint_lock);
+	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
+	mask &= ~(eint_irq_to_bit(irq));
+	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+	spin_unlock(&eint_lock);
+}
+
+static inline void s5pv310_irq_eint_ack(unsigned int irq)
+{
+	spin_lock(&eint_lock);
+	__raw_writel(eint_irq_to_bit(irq),
+		     S5P_EINT_PEND(EINT_REG_NR(irq)));
+	spin_unlock(&eint_lock);
+}
+
+static void s5pv310_irq_eint_maskack(unsigned int irq)
+{
+	s5pv310_irq_eint_mask(irq);
+	s5pv310_irq_eint_ack(irq);
+}
+
+static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
+{
+	int offs = EINT_OFFSET(irq);
+	int shift;
+	u32 ctrl, mask;
+	u32 newvalue = 0;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		newvalue = S5P_IRQ_TYPE_EDGE_RISING;
+		break;
+
+	case IRQ_TYPE_EDGE_FALLING:
+		newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
+		break;
+
+	case IRQ_TYPE_EDGE_BOTH:
+		newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
+		break;
+
+	case IRQ_TYPE_LEVEL_LOW:
+		newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
+		break;
+
+	case IRQ_TYPE_LEVEL_HIGH:
+		newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
+		break;
+
+	default:
+		printk(KERN_ERR "No such irq type %d", type);
+		return -EINVAL;
+	}
+
+	shift = (offs & 0x7) * 4;
+	mask = 0x7 << shift;
+
+	spin_lock(&eint_lock);
+	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
+	ctrl &= ~mask;
+	ctrl |= newvalue << shift;
+	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
+	spin_unlock(&eint_lock);
+
+	if ((0 <= offs) && (offs < 8))
+		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+
+	else if ((8 <= offs) && (offs < 16))
+		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+
+	else if ((16 <= offs) && (offs < 24))
+		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+
+	else if ((24 <= offs) && (offs < 32))
+		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+
+	else
+		printk(KERN_ERR "No such irq number %d", offs);
+
+	return 0;
+}
+
+static struct irq_chip s5pv310_irq_eint = {
+	.name		= "s5pv310-eint",
+	.mask		= s5pv310_irq_eint_mask,
+	.unmask		= s5pv310_irq_eint_unmask,
+	.mask_ack	= s5pv310_irq_eint_maskack,
+	.ack		= s5pv310_irq_eint_ack,
+	.set_type	= s5pv310_irq_eint_set_type,
+#ifdef CONFIG_PM
+	.set_wake	= s3c_irqext_wake,
+#endif
+};
+
+/* s5pv310_irq_demux_eint
+ *
+ * This function demuxes the IRQ from from EINTs 16 to 31.
+ * It is designed to be inlined into the specific handler
+ * s5p_irq_demux_eintX_Y.
+ *
+ * Each EINT pend/mask registers handle eight of them.
+ */
+static inline void s5pv310_irq_demux_eint(unsigned int start)
+{
+	unsigned int irq;
+
+	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+
+	status &= ~mask;
+	status &= 0xff;
+
+	while (status) {
+		irq = fls(status) - 1;
+		generic_handle_irq(irq + start);
+		status &= ~(1 << irq);
+	}
+}
+
+static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+	s5pv310_irq_demux_eint(IRQ_EINT(16));
+	s5pv310_irq_demux_eint(IRQ_EINT(24));
+}
+
+static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+{
+	u32 i;
+	struct irq_chip *chip = get_irq_chip(irq);
+
+	chip->mask(irq);
+
+	if (chip->ack)
+		chip->ack(irq);
+
+	for (i = 0 ; i <= 15 ; i++) {
+		if (irq == s5pv310_get_irq_nr(i)) {
+			generic_handle_irq(IRQ_EINT(i));
+			break;
+		}
+	}
+
+	chip->unmask(irq);
+}
+
+int __init s5pv310_init_irq_eint(void)
+{
+	int irq;
+
+	for (irq = 0 ; irq <= 31 ; irq++) {
+		set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
+		set_irq_handler(IRQ_EINT(irq), handle_level_irq);
+		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+	}
+
+	set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
+
+	for (irq = 0 ; irq <= 15 ; irq++)
+		set_irq_chained_handler(s5pv310_get_irq_nr(irq),
+					s5pv310_irq_eint0_15);
+
+	return 0;
+}
+
+arch_initcall(s5pv310_init_irq_eint);
-- 
1.6.3.3

[PATCH 2/2] ARM: S5PV310: Add external interrupt support

[Ben Dooks]

On 18/10/10 06:06, Jongsun Han wrote:
> All external interrupts are transferred to GIC through interrupt combiner.
> 
> Signed-off-by: Jongsun Han <jongsun.han@samsung.com>
> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
> ---
>  arch/arm/mach-s5pv310/Makefile   |    2 +-
>  arch/arm/mach-s5pv310/irq-eint.c |  228 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 229 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-s5pv310/irq-eint.c
> 
> diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
> index 97aba6d..6a8a1ef 100644
> --- a/arch/arm/mach-s5pv310/Makefile
> +++ b/arch/arm/mach-s5pv310/Makefile
> @@ -13,7 +13,7 @@ obj-				:=
>  # Core support for S5PV310 system
>  
>  obj-$(CONFIG_CPU_S5PV310)	+= cpu.o init.o clock.o irq-combiner.o
> -obj-$(CONFIG_CPU_S5PV310)	+= setup-i2c0.o time.o gpiolib.o
> +obj-$(CONFIG_CPU_S5PV310)	+= setup-i2c0.o time.o gpiolib.o irq-eint.o
>  obj-$(CONFIG_CPU_FREQ)		+= cpufreq.o
>  
>  obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
> diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c

> +static unsigned int s5pv310_get_irq_nr(unsigned int number)
> +{
> +	u32 ret = 0;
> +
> +	switch (number) {
> +	case 0 ... 3:
> +		ret = (number + IRQ_EINT0);
> +		break;
> +	case 4 ... 7:
> +		ret = (number + (IRQ_EINT4 - 4));
> +		break;
> +	case 8 ... 15:
> +		ret = (number + (IRQ_EINT8 - 8));
> +		break;
> +	default:
> +		printk(KERN_ERR "number available : %d\n", number);
> +	}
> +
> +	return ret;
> +}

> +static inline void s5pv310_irq_eint_ack(unsigned int irq)
> +{
> +	spin_lock(&eint_lock);
> +	__raw_writel(eint_irq_to_bit(irq),
> +		     S5P_EINT_PEND(EINT_REG_NR(irq)));
> +	spin_unlock(&eint_lock);
> +}

do you really need a spinlock around a single write?

> +static void s5pv310_irq_eint_maskack(unsigned int irq)
> +{
> +	s5pv310_irq_eint_mask(irq);
> +	s5pv310_irq_eint_ack(irq);
> +}
> +
> +static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
> +{
> +	int offs = EINT_OFFSET(irq);
> +	int shift;
> +	u32 ctrl, mask;
> +	u32 newvalue = 0;
> +
> +	switch (type) {
> +	case IRQ_TYPE_EDGE_RISING:
> +		newvalue = S5P_IRQ_TYPE_EDGE_RISING;
> +		break;
> +
> +	case IRQ_TYPE_EDGE_FALLING:
> +		newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
> +		break;
> +
> +	case IRQ_TYPE_EDGE_BOTH:
> +		newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
> +		break;
> +
> +	case IRQ_TYPE_LEVEL_LOW:
> +		newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
> +		break;
> +
> +	case IRQ_TYPE_LEVEL_HIGH:
> +		newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
> +		break;
> +
> +	default:
> +		printk(KERN_ERR "No such irq type %d", type);
> +		return -EINVAL;
> +	}
> +
> +	shift = (offs & 0x7) * 4;
> +	mask = 0x7 << shift;
> +
> +	spin_lock(&eint_lock);
> +	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
> +	ctrl &= ~mask;
> +	ctrl |= newvalue << shift;
> +	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
> +	spin_unlock(&eint_lock);
> +
> +	if ((0 <= offs) && (offs < 8))

a switch on (offs >> 3) would have been more efficient.

> +		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
> +
> +	else if ((8 <= offs) && (offs < 16))
> +		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
> +
> +	else if ((16 <= offs) && (offs < 24))
> +		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
> +
> +	else if ((24 <= offs) && (offs < 32))
> +		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
> +
> +	else
> +		printk(KERN_ERR "No such irq number %d", offs);
> +
> +	return 0;
> +}


> +
> +static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
> +{
> +	u32 i;
> +	struct irq_chip *chip = get_irq_chip(irq);
> +
> +	chip->mask(irq);
> +
> +	if (chip->ack)
> +		chip->ack(irq);
> +
> +	for (i = 0 ; i <= 15 ; i++) {
> +		if (irq == s5pv310_get_irq_nr(i)) {
> +			generic_handle_irq(IRQ_EINT(i));
> +			break;
> +		}
> +	}
> +
> +	chip->unmask(irq);
> +}

I would say that keeping the information about the irq => IRQ_EINT
mapping around in the irq_desc information to save the time taken
to process the for() loop in the above function.

> +int __init s5pv310_init_irq_eint(void)
> +{
> +	int irq;
> +
> +	for (irq = 0 ; irq <= 31 ; irq++) {
> +		set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
> +		set_irq_handler(IRQ_EINT(irq), handle_level_irq);
> +		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
> +	}
> +
> +	set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
> +
> +	for (irq = 0 ; irq <= 15 ; irq++)
> +		set_irq_chained_handler(s5pv310_get_irq_nr(irq),
> +					s5pv310_irq_eint0_15);
> +
> +	return 0;
> +}
> +
> +arch_initcall(s5pv310_init_irq_eint);