[PATCH v5 0/5] OMAP4: Smartreflex and Voltage layer support

[PATCH v5 0/5] OMAP4: Smartreflex and Voltage layer support

[Thara Gopinath]

This patch series adds support for OMAP4 support in the
smartreflex and voltage layer. The series involves extensions
to voltage layer and smartreflex layer for supporting OMAP4.

This series in based against kernel.org  2.6.37-rc3 and is
dependent on the "OMAP3: Adding Smartreflex and Voltage driver support"
series.

All these patches are also available at
        http://dev.omapzoom.org/?p=thara/omap-dvfs.git;a=summary
        head: kevin-pm-sr

This patch series has been tested on OMAP4430 SDP with omap2plus_defconfig
with the following menuconfig options enabled
        System type -> TI OMAP Implementations -> Smartreflex Support
        System type -> TI OMAP Implementations ->
                Class 3 mode of Smartreflex Implementation

Benoit Cousson (1):
  OMAP4: hwmod: Add inital data for smartreflex modules.

Thara Gopinath (4):
  OMAP4: Register voltage PMIC parameters with the voltage layer
  OMAP4: Adding voltage driver support
  OMAP4: PM: Program correct init voltages for scalable VDDs
  OMAP4: Smartreflex framework extensions

 arch/arm/mach-omap2/Makefile               |    2 +-
 arch/arm/mach-omap2/control.h              |   12 ++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  168 +++++++++++++++++
 arch/arm/mach-omap2/omap_twl.c             |  166 +++++++++++++++++
 arch/arm/mach-omap2/pm.c                   |   12 ++
 arch/arm/mach-omap2/pm.h                   |    5 +
 arch/arm/mach-omap2/smartreflex.c          |    8 +-
 arch/arm/mach-omap2/sr_device.c            |   17 ++-
 arch/arm/mach-omap2/voltage.c              |  279 ++++++++++++++++++++++++++++
 arch/arm/plat-omap/Kconfig                 |    2 +-
 arch/arm/plat-omap/include/plat/voltage.h  |   12 ++
 11 files changed, 678 insertions(+), 5 deletions(-)

[PATCH v5 1/5] OMAP4: Register voltage PMIC parameters with the voltage layer

[Thara Gopinath]

TWL6030 is the power IC used along with OMAP4 in OMAP4 SDPs,
blaze boards and panda boards. This patch registers the OMAP4
PMIC specific information with the voltage layer.
This also involves implementing a different formula for
voltage to vsel and vsel to voltage calculations from
TWL4030.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/omap_twl.c |  166 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/pm.c       |    1 +
 arch/arm/mach-omap2/pm.h       |    5 +
 3 files changed, 172 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index b8f0874..15f8c6c 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -16,6 +16,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/i2c/twl.h>
 
 #include <plat/voltage.h>
 
@@ -37,6 +38,28 @@
 #define OMAP3630_VP2_VLIMITTO_VDDMIN	0x18
 #define OMAP3630_VP2_VLIMITTO_VDDMAX	0x30
 
+#define OMAP4_SRI2C_SLAVE_ADDR		0x12
+#define OMAP4_VDD_MPU_SR_VOLT_REG	0x55
+#define OMAP4_VDD_IVA_SR_VOLT_REG	0x5B
+#define OMAP4_VDD_CORE_SR_VOLT_REG	0x61
+
+#define OMAP4_VP_CONFIG_ERROROFFSET	0x00
+#define OMAP4_VP_VSTEPMIN_VSTEPMIN	0x01
+#define OMAP4_VP_VSTEPMAX_VSTEPMAX	0x04
+#define OMAP4_VP_VLIMITTO_TIMEOUT_US	200
+
+#define OMAP4_VP_MPU_VLIMITTO_VDDMIN	0xA
+#define OMAP4_VP_MPU_VLIMITTO_VDDMAX	0x39
+#define OMAP4_VP_IVA_VLIMITTO_VDDMIN	0xA
+#define OMAP4_VP_IVA_VLIMITTO_VDDMAX	0x2D
+#define OMAP4_VP_CORE_VLIMITTO_VDDMIN	0xA
+#define OMAP4_VP_CORE_VLIMITTO_VDDMAX	0x28
+
+static bool is_offset_valid;
+static u8 smps_offset;
+
+#define REG_SMPS_OFFSET         0xE0
+
 unsigned long twl4030_vsel_to_uv(const u8 vsel)
 {
 	return (((vsel * 125) + 6000)) * 100;
@@ -47,6 +70,70 @@ u8 twl4030_uv_to_vsel(unsigned long uv)
 	return DIV_ROUND_UP(uv - 600000, 12500);
 }
 
+unsigned long twl6030_vsel_to_uv(const u8 vsel)
+{
+	/*
+	 * In TWL6030 depending on the value of SMPS_OFFSET
+	 * efuse register the voltage range supported in
+	 * standard mode can be either between 0.6V - 1.3V or
+	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+	 * is programmed to all 0's where as starting from
+	 * TWL6030 ES1.1 the efuse is programmed to 1
+	 */
+	if (!is_offset_valid) {
+		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
+				REG_SMPS_OFFSET);
+		is_offset_valid = true;
+	}
+
+	/*
+	 * There is no specific formula for voltage to vsel
+	 * conversion above 1.3V. There are special hardcoded
+	 * values for voltages above 1.3V. Currently we are
+	 * hardcoding only for 1.35 V which is used for 1GH OPP for
+	 * OMAP4430.
+	 */
+	if (vsel == 0x3A)
+		return 1350000;
+
+	if (smps_offset & 0x8)
+		return ((((vsel - 1) * 125) + 7000)) * 100;
+	else
+		return ((((vsel - 1) * 125) + 6000)) * 100;
+}
+
+u8 twl6030_uv_to_vsel(unsigned long uv)
+{
+	/*
+	 * In TWL6030 depending on the value of SMPS_OFFSET
+	 * efuse register the voltage range supported in
+	 * standard mode can be either between 0.6V - 1.3V or
+	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+	 * is programmed to all 0's where as starting from
+	 * TWL6030 ES1.1 the efuse is programmed to 1
+	 */
+	if (!is_offset_valid) {
+		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
+				REG_SMPS_OFFSET);
+		is_offset_valid = true;
+	}
+
+	/*
+	 * There is no specific formula for voltage to vsel
+	 * conversion above 1.3V. There are special hardcoded
+	 * values for voltages above 1.3V. Currently we are
+	 * hardcoding only for 1.35 V which is used for 1GH OPP for
+	 * OMAP4430.
+	 */
+	if (uv == 1350000)
+		return 0x3A;
+
+	if (smps_offset & 0x8)
+		return DIV_ROUND_UP(uv - 700000, 12500) + 1;
+	else
+		return DIV_ROUND_UP(uv - 600000, 12500) + 1;
+}
+
 static struct omap_volt_pmic_info omap3_mpu_volt_info = {
 	.slew_rate		= 4000,
 	.step_size		= 12500,
@@ -87,6 +174,85 @@ static struct omap_volt_pmic_info omap3_core_volt_info = {
 	.uv_to_vsel		= twl4030_uv_to_vsel,
 };
 
+static struct omap_volt_pmic_info omap4_mpu_volt_info = {
+	.slew_rate		= 4000,
+	.step_size		= 12500,
+	.on_volt		= 1350000,
+	.onlp_volt		= 1350000,
+	.ret_volt		= 837500,
+	.off_volt		= 600000,
+	.volt_setup_time	= 0,
+	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
+	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
+	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
+	.vp_vddmin		= OMAP4_VP_MPU_VLIMITTO_VDDMIN,
+	.vp_vddmax		= OMAP4_VP_MPU_VLIMITTO_VDDMAX,
+	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
+	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
+	.pmic_reg		= OMAP4_VDD_MPU_SR_VOLT_REG,
+	.vsel_to_uv		= twl6030_vsel_to_uv,
+	.uv_to_vsel		= twl6030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap4_iva_volt_info = {
+	.slew_rate		= 4000,
+	.step_size		= 12500,
+	.on_volt		= 1100000,
+	.onlp_volt		= 1100000,
+	.ret_volt		= 837500,
+	.off_volt		= 600000,
+	.volt_setup_time	= 0,
+	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
+	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
+	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
+	.vp_vddmin		= OMAP4_VP_IVA_VLIMITTO_VDDMIN,
+	.vp_vddmax		= OMAP4_VP_IVA_VLIMITTO_VDDMAX,
+	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
+	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
+	.pmic_reg		= OMAP4_VDD_IVA_SR_VOLT_REG,
+	.vsel_to_uv		= twl6030_vsel_to_uv,
+	.uv_to_vsel		= twl6030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap4_core_volt_info = {
+	.slew_rate		= 4000,
+	.step_size		= 12500,
+	.on_volt		= 1100000,
+	.onlp_volt		= 1100000,
+	.ret_volt		= 837500,
+	.off_volt		= 600000,
+	.volt_setup_time	= 0,
+	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
+	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
+	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
+	.vp_vddmin		= OMAP4_VP_CORE_VLIMITTO_VDDMIN,
+	.vp_vddmax		= OMAP4_VP_CORE_VLIMITTO_VDDMAX,
+	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
+	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
+	.pmic_reg		= OMAP4_VDD_CORE_SR_VOLT_REG,
+	.vsel_to_uv		= twl6030_vsel_to_uv,
+	.uv_to_vsel		= twl6030_uv_to_vsel,
+};
+
+int __init omap4_twl_init(void)
+{
+	struct voltagedomain *voltdm;
+
+	if (!cpu_is_omap44xx())
+		return -ENODEV;
+
+	voltdm = omap_voltage_domain_lookup("mpu");
+	omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);
+
+	voltdm = omap_voltage_domain_lookup("iva");
+	omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);
+
+	voltdm = omap_voltage_domain_lookup("core");
+	omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);
+
+	return 0;
+}
+
 int __init omap3_twl_init(void)
 {
 	struct voltagedomain *voltdm;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index cee86a5..8d0b03b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -222,6 +222,7 @@ static int __init omap2_common_pm_late_init(void)
 {
 	/* Init the OMAP TWL parameters */
 	omap3_twl_init();
+	omap4_twl_init();
 
 	/* Init the voltage layer */
 	omap_voltage_late_init();
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 619db1b..70d8fcc 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -115,11 +115,16 @@ static inline void omap_enable_smartreflex_on_init(void) {}
 
 #ifdef CONFIG_TWL4030_CORE
 extern int omap3_twl_init(void);
+extern int omap4_twl_init(void);
 #else
 static inline int omap3_twl_init(void)
 {
 	return -EINVAL;
 }
+static inline int omap4_twl_init(void)
+{
+	return -EINVAL;
+}
 #endif
 
 #endif
-- 
1.7.0.4

[PATCH v5 2/5] OMAP4: Adding voltage driver support

[Thara Gopinath]

OMAP4 has three scalable voltage domains vdd_mpu, vdd_iva
and vdd_core. This patch adds the voltage tables and other
configurable voltage processor and voltage controller
settings to control these three scalable domains in OMAP4.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
This patch has 9 checkpatch.pl above 80-chars warnings for
the definitions of omap44xx_vdd_mpu_volt_data, omap44xx_vdd_iva_volt_data
and omap44xx_vdd_core_volt_data.
IMHO splitting of the entries in these structures affects
readability and looks very ugly. Hence they are left as is.

 arch/arm/mach-omap2/Makefile              |    2 +-
 arch/arm/mach-omap2/control.h             |   12 ++
 arch/arm/mach-omap2/voltage.c             |  279 +++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/voltage.h |   12 ++
 4 files changed, 304 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ae29a00..9a73b82 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -61,7 +61,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o pm_bus.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o voltage.o \
 					   cpuidle34xx.o pm_bus.o
-obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o voltage.o pm_bus.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 9fe32dc..81940ef 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -181,6 +181,18 @@
 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
 
+/* OMAP44xx control efuse offsets */
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
+
 /* AM35XX only CONTROL_GENERAL register offsets */
 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
 #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index b27fa4f..ed6079c 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -29,6 +29,10 @@
 #include <plat/voltage.h>
 
 #include "prm-regbits-34xx.h"
+#include "prm-regbits-44xx.h"
+#include "prm44xx.h"
+#include "prcm44xx.h"
+#include "prminst44xx.h"
 #include "control.h"
 
 #define VP_IDLE_TIMEOUT		200
@@ -190,6 +194,51 @@ static struct omap_vdd_info omap3_vdd_info[] = {
 
 #define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info)
 
+/* OMAP4 VDD sturctures */
+static struct omap_vdd_info omap4_vdd_info[] = {
+	{
+		.vp_offs = {
+			.vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
+			.vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
+			.vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
+			.vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
+			.vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
+			.voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
+		},
+		.voltdm = {
+			.name = "mpu",
+		},
+	},
+	{
+		.vp_offs = {
+			.vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
+			.vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
+			.vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
+			.vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
+			.vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
+			.voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
+		},
+		.voltdm = {
+			.name = "iva",
+		},
+	},
+	{
+		.vp_offs = {
+			.vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
+			.vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
+			.vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
+			.vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
+			.vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
+			.voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
+		},
+		.voltdm = {
+			.name = "core",
+		},
+	},
+};
+
+#define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info)
+
 /*
  * Structures containing OMAP3430/OMAP3630 voltage supported and various
  * voltage dependent data for each VDD.
@@ -234,6 +283,31 @@ static struct omap_volt_data omap36xx_vddcore_volt_data[] = {
 	VOLT_DATA_DEFINE(0, 0, 0, 0),
 };
 
+/*
+ * Structures containing OMAP4430 voltage supported and various
+ * voltage dependent data for each VDD.
+ */
+static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+	VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
+	VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
+	VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
+	VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
+	VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+	VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
+	VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
+	VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
+	VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+static struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+	VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
+	VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
+	VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
 static struct dentry *voltage_dir;
 
 /* Init function pointers */
@@ -250,6 +324,17 @@ static void omap3_voltage_write_reg(u32 val, u16 mod, u8 offset)
 	omap2_prm_write_mod_reg(val, mod, offset);
 }
 
+static u32 omap4_voltage_read_reg(u16 mod, u8 offset)
+{
+	return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+					mod, offset);
+}
+
+static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
+{
+	omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
+}
+
 /* Voltage debugfs support */
 static int vp_volt_debug_get(void *data, u64 *val)
 {
@@ -841,6 +926,195 @@ static int __init omap3_vdd_data_configure(struct omap_vdd_info *vdd)
 	return 0;
 }
 
+/* OMAP4 specific voltage init functions */
+static void __init omap4_vc_init(struct omap_vdd_info *vdd)
+{
+	u32 vc_val;
+	u16 mod;
+	static bool is_initialized;
+
+	if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+		pr_err("%s: PMIC info requried to configure vc for"
+			"vdd_%s not populated.Hence cannot initialize vc\n",
+			__func__, vdd->voltdm.name);
+		return;
+	}
+
+	if (!vdd->read_reg || !vdd->write_reg) {
+		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+			__func__, vdd->voltdm.name);
+		return;
+	}
+
+	mod = vdd->vc_reg.prm_mod;
+
+	/* Set up the SMPS_SA(i2c slave address in VC */
+	vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
+	vc_val &= ~vdd->vc_reg.smps_sa_mask;
+	vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift;
+	vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
+
+	/* Setup the VOLRA(pmic reg addr) in VC */
+	vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg);
+	vc_val &= ~vdd->vc_reg.smps_volra_mask;
+	vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift;
+	vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
+
+	/* TODO: Configure setup times and CMD_VAL values*/
+
+	if (is_initialized)
+		return;
+
+	/* Generic VC parameters init */
+	vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
+		OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
+		OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
+	vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+
+	vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+	vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+
+	is_initialized = true;
+}
+
+/* Sets up all the VDD related info for OMAP4 */
+static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
+{
+	struct clk *sys_ck;
+	u32 sys_clk_speed, timeout_val, waittime;
+
+	if (!vdd->pmic_info) {
+		pr_err("%s: PMIC info requried to configure vdd_%s not"
+			"populated.Hence cannot initialize vdd_%s\n",
+			__func__, vdd->voltdm.name, vdd->voltdm.name);
+		return -EINVAL;
+	}
+
+	if (!strcmp(vdd->voltdm.name, "mpu")) {
+		vdd->volt_data = omap44xx_vdd_mpu_volt_data;
+		vdd->vp_reg.tranxdone_status =
+				OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
+		vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
+		vdd->vc_reg.smps_sa_shift =
+				OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT;
+		vdd->vc_reg.smps_sa_mask =
+				OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK;
+		vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT;
+		vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK;
+		vdd->vc_reg.voltsetup_reg =
+				OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET;
+		vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
+	} else if (!strcmp(vdd->voltdm.name, "core")) {
+		vdd->volt_data = omap44xx_vdd_core_volt_data;
+		vdd->vp_reg.tranxdone_status =
+				OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
+		vdd->vc_reg.cmdval_reg =
+				OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
+		vdd->vc_reg.smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT;
+		vdd->vc_reg.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK;
+		vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT;
+		vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK;
+		vdd->vc_reg.voltsetup_reg =
+				OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET;
+		vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
+	} else if (!strcmp(vdd->voltdm.name, "iva")) {
+		vdd->volt_data = omap44xx_vdd_iva_volt_data;
+		vdd->vp_reg.tranxdone_status =
+				OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
+		vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
+		vdd->vc_reg.smps_sa_shift =
+				OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT;
+		vdd->vc_reg.smps_sa_mask =
+				OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK;
+		vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT;
+		vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK;
+		vdd->vc_reg.voltsetup_reg =
+				OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET;
+		vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
+	} else {
+		pr_warning("%s: vdd_%s does not exisit in OMAP4\n",
+			__func__, vdd->voltdm.name);
+		return -EINVAL;
+	}
+
+	/*
+	 * Sys clk rate is require to calculate vp timeout value and
+	 * smpswaittimemin and smpswaittimemax.
+	 */
+	sys_ck = clk_get(NULL, "sys_clkin_ck");
+	if (IS_ERR(sys_ck)) {
+		pr_warning("%s: Could not get the sys clk to calculate"
+			"various vdd_%s params\n", __func__, vdd->voltdm.name);
+		return -EINVAL;
+	}
+	sys_clk_speed = clk_get_rate(sys_ck);
+	clk_put(sys_ck);
+	/* Divide to avoid overflow */
+	sys_clk_speed /= 1000;
+
+	/* Generic voltage parameters */
+	vdd->curr_volt = 1200000;
+	vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
+	vdd->read_reg = omap4_voltage_read_reg;
+	vdd->write_reg = omap4_voltage_write_reg;
+	vdd->volt_scale = vp_forceupdate_scale_voltage;
+	vdd->vp_enabled = false;
+
+	/* VC parameters */
+	vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
+	vdd->vc_reg.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET;
+	vdd->vc_reg.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET;
+	vdd->vc_reg.bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET;
+	vdd->vc_reg.data_shift = OMAP4430_DATA_SHIFT;
+	vdd->vc_reg.slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT;
+	vdd->vc_reg.regaddr_shift = OMAP4430_REGADDR_SHIFT;
+	vdd->vc_reg.valid = OMAP4430_VALID_MASK;
+	vdd->vc_reg.cmd_on_shift = OMAP4430_ON_SHIFT;
+	vdd->vc_reg.cmd_on_mask = OMAP4430_ON_MASK;
+	vdd->vc_reg.cmd_onlp_shift = OMAP4430_ONLP_SHIFT;
+	vdd->vc_reg.cmd_ret_shift = OMAP4430_RET_SHIFT;
+	vdd->vc_reg.cmd_off_shift = OMAP4430_OFF_SHIFT;
+
+	vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
+
+	/* VPCONFIG bit fields */
+	vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<
+				 OMAP4430_ERROROFFSET_SHIFT);
+	vdd->vp_reg.vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK;
+	vdd->vp_reg.vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT;
+	vdd->vp_reg.vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT;
+	vdd->vp_reg.vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK;
+	vdd->vp_reg.vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK;
+	vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK;
+	vdd->vp_reg.vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK;
+	vdd->vp_reg.vpconfig_vpenable = OMAP4430_VPENABLE_MASK;
+
+	/* VSTEPMIN VSTEPMAX bit fields */
+	waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
+				sys_clk_speed) / 1000;
+	vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
+	vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
+	vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
+	vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
+	vdd->vp_reg.vstepmin_smpswaittimemin_shift =
+			OMAP4430_SMPSWAITTIMEMIN_SHIFT;
+	vdd->vp_reg.vstepmax_smpswaittimemax_shift =
+			OMAP4430_SMPSWAITTIMEMAX_SHIFT;
+	vdd->vp_reg.vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT;
+	vdd->vp_reg.vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT;
+
+	/* VLIMITTO bit fields */
+	timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
+	vdd->vp_reg.vlimitto_timeout = timeout_val;
+	vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
+	vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
+	vdd->vp_reg.vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT;
+	vdd->vp_reg.vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT;
+	vdd->vp_reg.vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT;
+
+	return 0;
+}
+
 /* Public functions */
 /**
  * omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage
@@ -1283,6 +1557,11 @@ static int __init omap_voltage_early_init(void)
 		nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD;
 		vc_init = omap3_vc_init;
 		vdd_data_configure = omap3_vdd_data_configure;
+	} else if (cpu_is_omap44xx()) {
+		vdd_info = omap4_vdd_info;
+		nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD;
+		vc_init = omap4_vc_init;
+		vdd_data_configure = omap4_vdd_data_configure;
 	} else {
 		pr_warning("%s: voltage driver support not added\n", __func__);
 	}
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
index 2f4f59a..0ff1233 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -44,6 +44,18 @@
 #define OMAP3630_VDD_CORE_OPP50_UV		1000000
 #define OMAP3630_VDD_CORE_OPP100_UV		1200000
 
+#define OMAP4430_VDD_MPU_OPP50_UV		930000
+#define OMAP4430_VDD_MPU_OPP100_UV		1100000
+#define OMAP4430_VDD_MPU_OPPTURBO_UV		1260000
+#define OMAP4430_VDD_MPU_OPPNITRO_UV		1350000
+
+#define OMAP4430_VDD_IVA_OPP50_UV		930000
+#define OMAP4430_VDD_IVA_OPP100_UV		1100000
+#define OMAP4430_VDD_IVA_OPPTURBO_UV		1260000
+
+#define OMAP4430_VDD_CORE_OPP50_UV		930000
+#define OMAP4430_VDD_CORE_OPP100_UV		1100000
+
 /**
  * struct voltagedomain - omap voltage domain global structure.
  * @name:	Name of the voltage domain which can be used as a unique
-- 
1.7.0.4

[PATCH v5 3/5] OMAP4: PM: Program correct init voltages for scalable VDDs

[Thara Gopinath]

By default the system boots up at nominal voltage for every
voltage domain in the system. This patch puts vdd_mpu, vdd_iva
and vdd_core to the correct boot up voltage as per the opp tables
specified. This patch implements this by matching the rate of
the main clock of the voltage domain with the opp table and
picking up the correct voltage.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/pm.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 8d0b03b..2e80de8 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -209,6 +209,16 @@ static void __init omap3_init_voltages(void)
 	omap2_set_init_voltage("core", "l3_ick", l3_dev);
 }
 
+static void __init omap4_init_voltages(void)
+{
+	if (!cpu_is_omap44xx())
+		return;
+
+	omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
+	omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
+	omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
+}
+
 static int __init omap2_common_pm_init(void)
 {
 	omap2_init_processor_devices();
@@ -229,6 +239,7 @@ static int __init omap2_common_pm_late_init(void)
 
 	/* Initialize the voltages */
 	omap3_init_voltages();
+	omap4_init_voltages();
 
 	/* Smartreflex device init */
 	omap_devinit_smartreflex();
-- 
1.7.0.4

[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.

[Thara Gopinath]

From: Benoit Cousson <b-cousson@ti.com>

This patch adds the hwmod details for OMAP4 smartreflex modules.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  168 ++++++++++++++++++++++++++++
 1 files changed, 168 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7367648..0a6e674 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1740,6 +1740,169 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+/*
+ * 'smartreflex' class
+ * smartreflex module (monitor silicon performance and outputs a measure of
+ * performance error)
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+	.sidle_shift	= 24,
+	.enwkup_shift	= 26,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
+	.sysc_offs	= 0x0038,
+	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type_smartreflex,
+};
+
+static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
+	.name = "smartreflex",
+	.sysc = &omap44xx_smartreflex_sysc,
+	.rev  = 2,
+};
+
+/* smartreflex_core */
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
+	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+	{
+		.pa_start	= 0x4a0dd000,
+		.pa_end		= 0x4a0dd03f,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_smartreflex_core_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_smartreflex_core_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_core slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
+	&omap44xx_l4_cfg__smartreflex_core,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+	.name		= "smartreflex_core",
+	.class		= &omap44xx_smartreflex_hwmod_class,
+	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
+	.main_clk	= "smartreflex_core_fck",
+	.vdd_name	= "core",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_smartreflex_core_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_iva */
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
+	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+	{
+		.pa_start	= 0x4a0db000,
+		.pa_end		= 0x4a0db03f,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_cfg -> smartreflex_iva */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_smartreflex_iva_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_smartreflex_iva_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_iva slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
+	&omap44xx_l4_cfg__smartreflex_iva,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+	.name		= "smartreflex_iva",
+	.class		= &omap44xx_smartreflex_hwmod_class,
+	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
+	.main_clk	= "smartreflex_iva_fck",
+	.vdd_name	= "iva",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_smartreflex_iva_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_mpu */
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
+	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+	{
+		.pa_start	= 0x4a0d9000,
+		.pa_end		= 0x4a0d903f,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_smartreflex_mpu_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_smartreflex_mpu_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_mpu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
+	&omap44xx_l4_cfg__smartreflex_mpu,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+	.name		= "smartreflex_mpu",
+	.class		= &omap44xx_smartreflex_hwmod_class,
+	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
+	.main_clk	= "smartreflex_mpu_fck",
+	.vdd_name	= "mpu",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_smartreflex_mpu_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	/* dmm class */
 	&omap44xx_dmm_hwmod,
@@ -1798,6 +1961,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	&omap44xx_wd_timer2_hwmod,
 	&omap44xx_wd_timer3_hwmod,
 
+	/* smartreflex class */
+	&omap44xx_smartreflex_core_hwmod,
+	&omap44xx_smartreflex_iva_hwmod,
+	&omap44xx_smartreflex_mpu_hwmod,
+
 	NULL,
 };
 
-- 
1.7.0.4

[PATCH v5 5/5] OMAP4: Smartreflex framework extensions

[Thara Gopinath]

This patch extends the smartreflex framework to support
OMAP4. The changes are minor like compiling smartreflex Kconfig
option for OMAP4 also, and a couple of OMAP4 checks in
the smartreflex framework.

The change in sr_device.c where new logic has to be introduced
for reading the efuse registers is due to the fact that in OMAP4
the efuse registers are 24 bit aligned. A __raw_readl will
fail for non-32 bit aligned address and hence the 8-bit read
and shift.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |    8 ++++++--
 arch/arm/mach-omap2/sr_device.c   |   17 ++++++++++++++++-
 arch/arm/plat-omap/Kconfig        |    2 +-
 3 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 52a05b3..77ecebf 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -153,7 +153,11 @@ static void sr_set_clk_length(struct omap_sr *sr)
 	struct clk *sys_ck;
 	u32 sys_clk_speed;
 
-	sys_ck = clk_get(NULL, "sys_ck");
+	if (cpu_is_omap34xx())
+		sys_ck = clk_get(NULL, "sys_ck");
+	else
+		sys_ck = clk_get(NULL, "sys_clkin_ck");
+
 	if (IS_ERR(sys_ck)) {
 		dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
 			__func__);
@@ -193,7 +197,7 @@ static void sr_set_regfields(struct omap_sr *sr)
 	 * file or pmic specific data structure. In that case these structure
 	 * fields will have to be populated using the pdata or pmic structure.
 	 */
-	if (cpu_is_omap34xx()) {
+	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
 		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
 		sr->accum_data = OMAP3430_SR_ACCUMDATA;
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 9a3538f..786d685 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -20,6 +20,7 @@
 
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <linux/io.h>
 
 #include <plat/omap_device.h>
 #include <plat/smartreflex.h>
@@ -51,7 +52,21 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 			GFP_KERNEL);
 
 	for (i = 0; i < count; i++) {
-		u32 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+		u32 v;
+		/*
+		 * In OMAP4 the efuse registers are 24 bit aligned.
+		 * A __raw_readl will fail for non-32 bit aligned address
+		 * and hence the 8-bit read and shift.
+		 */
+		if (cpu_is_omap44xx()) {
+			u16 offset = volt_data[i].sr_efuse_offs;
+
+			v = omap_ctrl_readb(offset) |
+				omap_ctrl_readb(offset + 1) << 8 |
+				omap_ctrl_readb(offset + 2) << 16;
+		} else {
+			 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+		}
 
 		nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
 		nvalue_table[i].nvalue = v;
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 4029e6a..88ff484 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -37,7 +37,7 @@ config OMAP_DEBUG_LEDS
 
 config OMAP_SMARTREFLEX
 	bool "SmartReflex support"
-	depends on ARCH_OMAP3 && PM
+	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
 	help
 	  Say Y if you want to enable SmartReflex.
 
-- 
1.7.0.4

[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.

[Cousson, Benoit]

Hi Thara,

On 12/20/2010 6:00 PM, Gopinath, Thara wrote:
> From: Benoit Cousson<b-cousson@ti.com>
> 
> This patch adds the hwmod details for OMAP4 smartreflex modules.
> 
> Signed-off-by: Benoit Cousson<b-cousson@ti.com>

You're s-o-b is missing, along with the changed you did to the patch.

> ---
>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  168 ++++++++++++++++++++++++++++
>   1 files changed, 168 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index 7367648..0a6e674 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -1740,6 +1740,169 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
>   	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
>   };
> 
> +/*
> + * 'smartreflex' class
> + * smartreflex module (monitor silicon performance and outputs a measure of
> + * performance error)
> + */
> +
> +/* The IP is not compliant to type1 / type2 scheme */
> +static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
> +	.sidle_shift	= 24,
> +	.enwkup_shift	= 26,
> +};
> +
> +static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
> +	.sysc_offs	= 0x0038,
> +	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
> +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

The newly added SIDLE_SMART_WKUP flag is missing. 

> +	.sysc_fields	=&omap_hwmod_sysc_type_smartreflex,
> +};
> +
> +static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
> +	.name = "smartreflex",
> +	.sysc =&omap44xx_smartreflex_sysc,
> +	.rev  = 2,
> +};
> +
> +/* smartreflex_core */
> +static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
> +static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
> +	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
> +};
> +
> +static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
> +	{
> +		.pa_start	= 0x4a0dd000,
> +		.pa_end		= 0x4a0dd03f,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_cfg ->  smartreflex_core */
> +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
> +	.master		=&omap44xx_l4_cfg_hwmod,
> +	.slave		=&omap44xx_smartreflex_core_hwmod,
> +	.clk		= "l4_div_ck",
> +	.addr		= omap44xx_smartreflex_core_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* smartreflex_core slave ports */
> +static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
> +	&omap44xx_l4_cfg__smartreflex_core,
> +};
> +
> +static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
> +	.name		= "smartreflex_core",
> +	.class		=&omap44xx_smartreflex_hwmod_class,
> +	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
> +	.main_clk	= "smartreflex_core_fck",
> +	.vdd_name	= "core",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
> +		},
> +	},
> +	.slaves		= omap44xx_smartreflex_core_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> +};
> +
> +/* smartreflex_iva */
> +static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
> +static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
> +	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
> +};
> +
> +static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
> +	{
> +		.pa_start	= 0x4a0db000,
> +		.pa_end		= 0x4a0db03f,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_cfg ->  smartreflex_iva */
> +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
> +	.master		=&omap44xx_l4_cfg_hwmod,
> +	.slave		=&omap44xx_smartreflex_iva_hwmod,
> +	.clk		= "l4_div_ck",
> +	.addr		= omap44xx_smartreflex_iva_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* smartreflex_iva slave ports */
> +static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
> +	&omap44xx_l4_cfg__smartreflex_iva,
> +};
> +
> +static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
> +	.name		= "smartreflex_iva",
> +	.class		=&omap44xx_smartreflex_hwmod_class,
> +	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
> +	.main_clk	= "smartreflex_iva_fck",
> +	.vdd_name	= "iva",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
> +		},
> +	},
> +	.slaves		= omap44xx_smartreflex_iva_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> +};
> +
> +/* smartreflex_mpu */
> +static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
> +static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
> +	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
> +};
> +
> +static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
> +	{
> +		.pa_start	= 0x4a0d9000,
> +		.pa_end		= 0x4a0d903f,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +};
> +
> +/* l4_cfg ->  smartreflex_mpu */
> +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
> +	.master		=&omap44xx_l4_cfg_hwmod,
> +	.slave		=&omap44xx_smartreflex_mpu_hwmod,
> +	.clk		= "l4_div_ck",
> +	.addr		= omap44xx_smartreflex_mpu_addrs,
> +	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* smartreflex_mpu slave ports */
> +static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
> +	&omap44xx_l4_cfg__smartreflex_mpu,
> +};
> +
> +static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
> +	.name		= "smartreflex_mpu",
> +	.class		=&omap44xx_smartreflex_hwmod_class,
> +	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
> +	.main_clk	= "smartreflex_mpu_fck",
> +	.vdd_name	= "mpu",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
> +		},
> +	},
> +	.slaves		= omap44xx_smartreflex_mpu_slaves,
> +	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
> +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> +};
> +
>   static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
>   	/* dmm class */
>   	&omap44xx_dmm_hwmod,
> @@ -1798,6 +1961,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
>   	&omap44xx_wd_timer2_hwmod,
>   	&omap44xx_wd_timer3_hwmod,
> 
> +	/* smartreflex class */
> +	&omap44xx_smartreflex_core_hwmod,
> +	&omap44xx_smartreflex_iva_hwmod,
> +	&omap44xx_smartreflex_mpu_hwmod,
> +

The alphabetical order is not respected. Smartreflex should be before wd_timer.

Since Tony already pull that from Kevin's tree, I'll send a patch to Tony to fix these issues.

Please note the following log when enabling SR in Class 3 on an OMAP4430/sdp:

[    2.362182] omap2_set_init_voltage: unable to find boot up OPP for vdd_mpu
[    2.369384] omap2_set_init_voltage: Unable to put vdd_mpu to its init voltage
[    2.369384]
[    2.378875] omap2_set_init_voltage: unable to find boot up OPP for vdd_iva
[    2.386108] omap2_set_init_voltage: Unable to put vdd_iva to its init voltage
[    2.386108]
[    2.396484] Power Management for TI OMAP4.
[    2.401031] sr_init: No PMIC hook to init smartreflex
[    2.406494] smartreflex smartreflex.0: omap_sr_probe: SmartReflex driver initialized
[    2.414825] smartreflex smartreflex.1: omap_sr_probe: SmartReflex driver initialized
[    2.423187] smartreflex smartreflex.2: omap_sr_probe: SmartReflex driver initialized
[    2.431732] SmartReflex Class3 initialized

Is it expected? 
Why do we have that blank line in-between?

Regards,
Benoit

[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.

[Menon, Nishanth]

On Thu, Dec 23, 2010 at 06:07, Cousson, Benoit <b-cousson@ti.com> wrote:

>
> Please note the following log when enabling SR in Class 3 on an OMAP4430/sdp:
>
> [ ? ?2.362182] omap2_set_init_voltage: unable to find boot up OPP for vdd_mpu
> [ ? ?2.369384] omap2_set_init_voltage: Unable to put vdd_mpu to its init voltage
> [ ? ?2.369384]
> [ ? ?2.378875] omap2_set_init_voltage: unable to find boot up OPP for vdd_iva
> [ ? ?2.386108] omap2_set_init_voltage: Unable to put vdd_iva to its init voltage
> [ ? ?2.386108]
> [ ? ?2.396484] Power Management for TI OMAP4.
> [ ? ?2.401031] sr_init: No PMIC hook to init smartreflex
> [ ? ?2.406494] smartreflex smartreflex.0: omap_sr_probe: SmartReflex driver initialized
> [ ? ?2.414825] smartreflex smartreflex.1: omap_sr_probe: SmartReflex driver initialized
> [ ? ?2.423187] smartreflex smartreflex.2: omap_sr_probe: SmartReflex driver initialized
> [ ? ?2.431732] SmartReflex Class3 initialized
>
Dumb question: how are you testing this? just boot log? or additional
patch for DVFS?


Regards,
Nishanth Menon

[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.

[Cousson, Benoit]

On 12/23/2010 2:25 PM, Menon, Nishanth wrote:
> On Thu, Dec 23, 2010 at 06:07, Cousson, Benoit<b-cousson@ti.com>  wrote:
>
>>
>> Please note the following log when enabling SR in Class 3 on an OMAP4430/sdp:
>>
>> [    2.362182] omap2_set_init_voltage: unable to find boot up OPP for vdd_mpu
>> [    2.369384] omap2_set_init_voltage: Unable to put vdd_mpu to its init voltage
>> [    2.369384]
>> [    2.378875] omap2_set_init_voltage: unable to find boot up OPP for vdd_iva
>> [    2.386108] omap2_set_init_voltage: Unable to put vdd_iva to its init voltage
>> [    2.386108]
>> [    2.396484] Power Management for TI OMAP4.
>> [    2.401031] sr_init: No PMIC hook to init smartreflex
>> [    2.406494] smartreflex smartreflex.0: omap_sr_probe: SmartReflex driver initialized
>> [    2.414825] smartreflex smartreflex.1: omap_sr_probe: SmartReflex driver initialized
>> [    2.423187] smartreflex smartreflex.2: omap_sr_probe: SmartReflex driver initialized
>> [    2.431732] SmartReflex Class3 initialized
>>
> Dumb question: how are you testing this? just boot log? or additional
> patch for DVFS?

Unfortunately, it is just a boot log since I do not have any DVFS code 
on top of it :-(

That's why I was not expecting any errors at that time.

Benoit

[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.

[Vishwanath Sripathy]

Benoit,

> -----Original Message-----
> From: Cousson, Benoit [mailto:b-cousson at ti.com]
> Sent: Thursday, December 23, 2010 5:37 PM
> To: Gopinath, Thara
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> khilman at deeprootsystems.com; paul at pwsan.com; Sripathy,
> Vishwanath; Sawant, Anand; Menon, Nishanth
> Subject: Re: [PATCH v5 4/5] OMAP4: hwmod: Add inital data for
> smartreflex modules.
>
> Hi Thara,
>
> On 12/20/2010 6:00 PM, Gopinath, Thara wrote:
> > From: Benoit Cousson<b-cousson@ti.com>
> >
> > This patch adds the hwmod details for OMAP4 smartreflex modules.
> >
> > Signed-off-by: Benoit Cousson<b-cousson@ti.com>
>
> You're s-o-b is missing, along with the changed you did to the patch.
>
> > ---
> >   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  168
> ++++++++++++++++++++++++++++
> >   1 files changed, 168 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> > index 7367648..0a6e674 100644
> > --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> > +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> > @@ -1740,6 +1740,169 @@ static struct omap_hwmod
> omap44xx_wd_timer3_hwmod = {
> >   	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> >   };
> >
> > +/*
> > + * 'smartreflex' class
> > + * smartreflex module (monitor silicon performance and outputs a
> measure of
> > + * performance error)
> > + */
> > +
> > +/* The IP is not compliant to type1 / type2 scheme */
> > +static struct omap_hwmod_sysc_fields
> omap_hwmod_sysc_type_smartreflex = {
> > +	.sidle_shift	= 24,
> > +	.enwkup_shift	= 26,
> > +};
> > +
> > +static struct omap_hwmod_class_sysconfig
> omap44xx_smartreflex_sysc = {
> > +	.sysc_offs	= 0x0038,
> > +	.sysc_flags	= (SYSC_HAS_ENAWAKEUP |
> SYSC_HAS_SIDLEMODE),
> > +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
>
> The newly added SIDLE_SMART_WKUP flag is missing.
>
> > +	.sysc_fields	=&omap_hwmod_sysc_type_smartreflex,
> > +};
> > +
> > +static struct omap_hwmod_class
> omap44xx_smartreflex_hwmod_class = {
> > +	.name = "smartreflex",
> > +	.sysc =&omap44xx_smartreflex_sysc,
> > +	.rev  = 2,
> > +};
> > +
> > +/* smartreflex_core */
> > +static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
> > +static struct omap_hwmod_irq_info
> omap44xx_smartreflex_core_irqs[] = {
> > +	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
> > +};
> > +
> > +static struct omap_hwmod_addr_space
> omap44xx_smartreflex_core_addrs[] = {
> > +	{
> > +		.pa_start	= 0x4a0dd000,
> > +		.pa_end		= 0x4a0dd03f,
> > +		.flags		= ADDR_TYPE_RT
> > +	},
> > +};
> > +
> > +/* l4_cfg ->  smartreflex_core */
> > +static struct omap_hwmod_ocp_if
> omap44xx_l4_cfg__smartreflex_core = {
> > +	.master		=&omap44xx_l4_cfg_hwmod,
> > +	.slave		=&omap44xx_smartreflex_core_hwmod,
> > +	.clk		= "l4_div_ck",
> > +	.addr		= omap44xx_smartreflex_core_addrs,
> > +	.addr_cnt	=
> ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
> > +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> > +};
> > +
> > +/* smartreflex_core slave ports */
> > +static struct omap_hwmod_ocp_if
> *omap44xx_smartreflex_core_slaves[] = {
> > +	&omap44xx_l4_cfg__smartreflex_core,
> > +};
> > +
> > +static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
> > +	.name		= "smartreflex_core",
> > +	.class		=&omap44xx_smartreflex_hwmod_class,
> > +	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
> > +	.mpu_irqs_cnt	=
> ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
> > +	.main_clk	= "smartreflex_core_fck",
> > +	.vdd_name	= "core",
> > +	.prcm = {
> > +		.omap4 = {
> > +			.clkctrl_reg =
> OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
> > +		},
> > +	},
> > +	.slaves		= omap44xx_smartreflex_core_slaves,
> > +	.slaves_cnt	=
> ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
> > +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> > +};
> > +
> > +/* smartreflex_iva */
> > +static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
> > +static struct omap_hwmod_irq_info
> omap44xx_smartreflex_iva_irqs[] = {
> > +	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
> > +};
> > +
> > +static struct omap_hwmod_addr_space
> omap44xx_smartreflex_iva_addrs[] = {
> > +	{
> > +		.pa_start	= 0x4a0db000,
> > +		.pa_end		= 0x4a0db03f,
> > +		.flags		= ADDR_TYPE_RT
> > +	},
> > +};
> > +
> > +/* l4_cfg ->  smartreflex_iva */
> > +static struct omap_hwmod_ocp_if
> omap44xx_l4_cfg__smartreflex_iva = {
> > +	.master		=&omap44xx_l4_cfg_hwmod,
> > +	.slave		=&omap44xx_smartreflex_iva_hwmod,
> > +	.clk		= "l4_div_ck",
> > +	.addr		= omap44xx_smartreflex_iva_addrs,
> > +	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
> > +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> > +};
> > +
> > +/* smartreflex_iva slave ports */
> > +static struct omap_hwmod_ocp_if
> *omap44xx_smartreflex_iva_slaves[] = {
> > +	&omap44xx_l4_cfg__smartreflex_iva,
> > +};
> > +
> > +static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
> > +	.name		= "smartreflex_iva",
> > +	.class		=&omap44xx_smartreflex_hwmod_class,
> > +	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
> > +	.mpu_irqs_cnt	=
> ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
> > +	.main_clk	= "smartreflex_iva_fck",
> > +	.vdd_name	= "iva",
> > +	.prcm = {
> > +		.omap4 = {
> > +			.clkctrl_reg =
> OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
> > +		},
> > +	},
> > +	.slaves		= omap44xx_smartreflex_iva_slaves,
> > +	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
> > +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> > +};
> > +
> > +/* smartreflex_mpu */
> > +static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
> > +static struct omap_hwmod_irq_info
> omap44xx_smartreflex_mpu_irqs[] = {
> > +	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
> > +};
> > +
> > +static struct omap_hwmod_addr_space
> omap44xx_smartreflex_mpu_addrs[] = {
> > +	{
> > +		.pa_start	= 0x4a0d9000,
> > +		.pa_end		= 0x4a0d903f,
> > +		.flags		= ADDR_TYPE_RT
> > +	},
> > +};
> > +
> > +/* l4_cfg ->  smartreflex_mpu */
> > +static struct omap_hwmod_ocp_if
> omap44xx_l4_cfg__smartreflex_mpu = {
> > +	.master		=&omap44xx_l4_cfg_hwmod,
> > +	.slave		=&omap44xx_smartreflex_mpu_hwmod,
> > +	.clk		= "l4_div_ck",
> > +	.addr		= omap44xx_smartreflex_mpu_addrs,
> > +	.addr_cnt	=
> ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
> > +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> > +};
> > +
> > +/* smartreflex_mpu slave ports */
> > +static struct omap_hwmod_ocp_if
> *omap44xx_smartreflex_mpu_slaves[] = {
> > +	&omap44xx_l4_cfg__smartreflex_mpu,
> > +};
> > +
> > +static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
> > +	.name		= "smartreflex_mpu",
> > +	.class		=&omap44xx_smartreflex_hwmod_class,
> > +	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
> > +	.mpu_irqs_cnt	=
> ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
> > +	.main_clk	= "smartreflex_mpu_fck",
> > +	.vdd_name	= "mpu",
> > +	.prcm = {
> > +		.omap4 = {
> > +			.clkctrl_reg =
> OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
> > +		},
> > +	},
> > +	.slaves		= omap44xx_smartreflex_mpu_slaves,
> > +	.slaves_cnt	=
> ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
> > +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> > +};
> > +
> >   static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
> >   	/* dmm class */
> >   	&omap44xx_dmm_hwmod,
> > @@ -1798,6 +1961,11 @@ static __initdata struct omap_hwmod
> *omap44xx_hwmods[] = {
> >   	&omap44xx_wd_timer2_hwmod,
> >   	&omap44xx_wd_timer3_hwmod,
> >
> > +	/* smartreflex class */
> > +	&omap44xx_smartreflex_core_hwmod,
> > +	&omap44xx_smartreflex_iva_hwmod,
> > +	&omap44xx_smartreflex_mpu_hwmod,
> > +
>
> The alphabetical order is not respected. Smartreflex should be before
> wd_timer.
>
> Since Tony already pull that from Kevin's tree, I'll send a patch to
Tony
> to fix these issues.
>
> Please note the following log when enabling SR in Class 3 on an
> OMAP4430/sdp:
>
> [    2.362182] omap2_set_init_voltage: unable to find boot up OPP for
> vdd_mpu
> [    2.369384] omap2_set_init_voltage: Unable to put vdd_mpu to its init
> voltage
> [    2.369384]
> [    2.378875] omap2_set_init_voltage: unable to find boot up OPP for
> vdd_iva
> [    2.386108] omap2_set_init_voltage: Unable to put vdd_iva to its init
> voltage
> [    2.386108]
> [    2.396484] Power Management for TI OMAP4.
> [    2.401031] sr_init: No PMIC hook to init smartreflex
> [    2.406494] smartreflex smartreflex.0: omap_sr_probe: SmartReflex
> driver initialized
> [    2.414825] smartreflex smartreflex.1: omap_sr_probe: SmartReflex
> driver initialized
> [    2.423187] smartreflex smartreflex.2: omap_sr_probe: SmartReflex
> driver initialized
> [    2.431732] SmartReflex Class3 initialized
>
> Is it expected?
> Why do we have that blank line in-between?

I think turbo OPPs are disabled by default in OPP table where as uboot is
setting mpu and iva to turbo OPP. That's why you are getting this error.
You should not get this error if you enable turbo opps in opp table.

Regarding blank line, it's because of this print (note \n\n)
printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n",

Vishwa
>
> Regards,
> Benoit
>
>

[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.

[Kevin Hilman]

Vishwanath Sripathy <vishwanath.bs@ti.com> writes:

[...]

>>
>> Please note the following log when enabling SR in Class 3 on an
>> OMAP4430/sdp:
>>
>> [    2.362182] omap2_set_init_voltage: unable to find boot up OPP for
>> vdd_mpu
>> [    2.369384] omap2_set_init_voltage: Unable to put vdd_mpu to its init
>> voltage
>> [    2.369384]
>> [    2.378875] omap2_set_init_voltage: unable to find boot up OPP for
>> vdd_iva
>> [    2.386108] omap2_set_init_voltage: Unable to put vdd_iva to its init
>> voltage
>> [    2.386108]
>> [    2.396484] Power Management for TI OMAP4.
>> [    2.401031] sr_init: No PMIC hook to init smartreflex
>> [    2.406494] smartreflex smartreflex.0: omap_sr_probe: SmartReflex
>> driver initialized
>> [    2.414825] smartreflex smartreflex.1: omap_sr_probe: SmartReflex
>> driver initialized
>> [    2.423187] smartreflex smartreflex.2: omap_sr_probe: SmartReflex
>> driver initialized
>> [    2.431732] SmartReflex Class3 initialized
>>
>> Is it expected?
>> Why do we have that blank line in-between?
>
> I think turbo OPPs are disabled by default in OPP table where as uboot is
> setting mpu and iva to turbo OPP. That's why you are getting this error.

That explains the MPU OPPs, but only raises more questions.  On what
platforms was this tested?  with *and* without turbo OPPs enabled?  Does
the voltage layer properly initialized if the boot up OPP is not found,
and the initial voltage is not set?

> You should not get this error if you enable turbo opps in opp table.

You would still get missing boot up OPP for IVA, as there are currenly
no OMAP4 OPPs for IVA.  Again, begging the question... how was this
tested.

Kevin

[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.

[Nishanth Menon]

Kevin Hilman had written, on 12/23/2010 11:15 AM, the following:
> Vishwanath Sripathy <vishwanath.bs@ti.com> writes:
> 
> [...]
> 
>>> Please note the following log when enabling SR in Class 3 on an
>>> OMAP4430/sdp:
>>>
>>> [    2.362182] omap2_set_init_voltage: unable to find boot up OPP for
>>> vdd_mpu
>>> [    2.369384] omap2_set_init_voltage: Unable to put vdd_mpu to its init
>>> voltage
>>> [    2.369384]
>>> [    2.378875] omap2_set_init_voltage: unable to find boot up OPP for
>>> vdd_iva
>>> [    2.386108] omap2_set_init_voltage: Unable to put vdd_iva to its init
>>> voltage
>>> [    2.386108]
>>> [    2.396484] Power Management for TI OMAP4.
>>> [    2.401031] sr_init: No PMIC hook to init smartreflex
>>> [    2.406494] smartreflex smartreflex.0: omap_sr_probe: SmartReflex
>>> driver initialized
>>> [    2.414825] smartreflex smartreflex.1: omap_sr_probe: SmartReflex
>>> driver initialized
>>> [    2.423187] smartreflex smartreflex.2: omap_sr_probe: SmartReflex
>>> driver initialized
>>> [    2.431732] SmartReflex Class3 initialized
>>>
>>> Is it expected?
>>> Why do we have that blank line in-between?
>> I think turbo OPPs are disabled by default in OPP table where as uboot is
>> setting mpu and iva to turbo OPP. That's why you are getting this error.
> That explains the MPU OPPs, but only raises more questions.  On what
> platforms was this tested?  with *and* without turbo OPPs enabled?  Does
> the voltage layer properly initialized if the boot up OPP is not found,
> and the initial voltage is not set?
> 
>> You should not get this error if you enable turbo opps in opp table.
If the platform SDP4430 is capable of booting up in higher (turbo) OPP, 
that OPP should have been enabled in the board file! I have'nt seen a 
patch for that yet

> You would still get missing boot up OPP for IVA, as there are currenly
> no OMAP4 OPPs for IVA.  Again, begging the question... how was this
> tested.
Further, why is SR enabled by default on this platform if it does not 
have all domains available to be enabled (e.x. we dont have it on 
PandaBoard even though it is OMAP4 rt?)

-- 
Regards,
Nishanth Menon

[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.

[Vishwanath Sripathy]

Nishant,

> -----Original Message-----
> From: Nishanth Menon [mailto:nm at ti.com]
> Sent: Thursday, December 23, 2010 10:55 PM
> To: Kevin Hilman
> Cc: Vishwanath Sripathy; Benoit Cousson; Thara Gopinath; linux-
> omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> paul at pwsan.com; Anand Sawant
> Subject: Re: [PATCH v5 4/5] OMAP4: hwmod: Add inital data for
> smartreflex modules.
>
> Kevin Hilman had written, on 12/23/2010 11:15 AM, the following:
> > Vishwanath Sripathy <vishwanath.bs@ti.com> writes:
> >
> > [...]
> >
> >>> Please note the following log when enabling SR in Class 3 on an
> >>> OMAP4430/sdp:
> >>>
> >>> [    2.362182] omap2_set_init_voltage: unable to find boot up OPP
> for
> >>> vdd_mpu
> >>> [    2.369384] omap2_set_init_voltage: Unable to put vdd_mpu to
> its init
> >>> voltage
> >>> [    2.369384]
> >>> [    2.378875] omap2_set_init_voltage: unable to find boot up OPP
> for
> >>> vdd_iva
> >>> [    2.386108] omap2_set_init_voltage: Unable to put vdd_iva to its
> init
> >>> voltage
> >>> [    2.386108]
> >>> [    2.396484] Power Management for TI OMAP4.
> >>> [    2.401031] sr_init: No PMIC hook to init smartreflex
> >>> [    2.406494] smartreflex smartreflex.0: omap_sr_probe:
> SmartReflex
> >>> driver initialized
> >>> [    2.414825] smartreflex smartreflex.1: omap_sr_probe:
> SmartReflex
> >>> driver initialized
> >>> [    2.423187] smartreflex smartreflex.2: omap_sr_probe:
> SmartReflex
> >>> driver initialized
> >>> [    2.431732] SmartReflex Class3 initialized
> >>>
> >>> Is it expected?
> >>> Why do we have that blank line in-between?
> >> I think turbo OPPs are disabled by default in OPP table where as
> uboot is
> >> setting mpu and iva to turbo OPP. That's why you are getting this
> error.
> > That explains the MPU OPPs, but only raises more questions.  On what
> > platforms was this tested?  with *and* without turbo OPPs enabled?
> Does
> > the voltage layer properly initialized if the boot up OPP is not
found,
> > and the initial voltage is not set?
> >
> >> You should not get this error if you enable turbo opps in opp table.
> If the platform SDP4430 is capable of booting up in higher (turbo) OPP,
> that OPP should have been enabled in the board file! I have'nt seen a
> patch for that yet
>
> > You would still get missing boot up OPP for IVA, as there are currenly
> > no OMAP4 OPPs for IVA.  Again, begging the question... how was this
> > tested.
> Further, why is SR enabled by default on this platform if it does not
> have all domains available to be enabled (e.x. we dont have it on
> PandaBoard even though it is OMAP4 rt?)
Why do you think SR is enabled by default? The above log says that SR
Module is initialized. However sr auto compensation is not started by
default.

Vishwa
>
> --
> Regards,
> Nishanth Menon

[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.

[Nishanth Menon]

Vishwanath Sripathy had written, on 12/23/2010 11:36 AM, the following:
[..]
>> Further, why is SR enabled by default on this platform if it does not
>> have all domains available to be enabled (e.x. we dont have it on
>> PandaBoard even though it is OMAP4 rt?)
> Why do you think SR is enabled by default? The above log says that SR
> Module is initialized. However sr auto compensation is not started by
> default.
oops.. my bad. Apologies, I missed that this is part of probe path not 
part of sr_classX_init path. looking at the code, I will refrain from 
commenting further on probe function at this point.

-- 
Regards,
Nishanth Menon

[PATCH v5 2/5] OMAP4: Adding voltage driver support

[Anand Sawant]

Thara,

> -----Original Message-----
> From: Thara Gopinath [mailto:thara at ti.com]
> Sent: Monday, December 20, 2010 10:31 PM
> To: linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org
> Cc: khilman at deeprootsystems.com; paul at pwsan.com; b-
> cousson at ti.com; vishwanath.bs at ti.com; sawant at ti.com;
> nm at ti.com; Thara Gopinath
> Subject: [PATCH v5 2/5] OMAP4: Adding voltage driver support
>
> OMAP4 has three scalable voltage domains vdd_mpu, vdd_iva
> and vdd_core. This patch adds the voltage tables and other
> configurable voltage processor and voltage controller
> settings to control these three scalable domains in OMAP4.
>
> Signed-off-by: Thara Gopinath <thara@ti.com>
> ---
> This patch has 9 checkpatch.pl above 80-chars warnings for
> the definitions of omap44xx_vdd_mpu_volt_data,
> omap44xx_vdd_iva_volt_data
> and omap44xx_vdd_core_volt_data.
> IMHO splitting of the entries in these structures affects
> readability and looks very ugly. Hence they are left as is.
>
>  arch/arm/mach-omap2/Makefile              |    2 +-
>  arch/arm/mach-omap2/control.h             |   12 ++
>  arch/arm/mach-omap2/voltage.c             |  279
> +++++++++++++++++++++++++++++
>  arch/arm/plat-omap/include/plat/voltage.h |   12 ++
>  4 files changed, 304 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-
> omap2/Makefile
> index ae29a00..9a73b82 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -61,7 +61,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+=
> pm24xx.o
>  obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o pm_bus.o
>  obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o
> voltage.o \
>  					   cpuidle34xx.o pm_bus.o
> -obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o
> +obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o voltage.o
> pm_bus.o
>  obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
>  obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o
> smartreflex.o
>  obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-
> class3.o
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-
> omap2/control.h
> index 9fe32dc..81940ef 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -181,6 +181,18 @@
>  #define OMAP3630_CONTROL_FUSE_OPP50_VDD2
> (OMAP2_CONTROL_GENERAL + 0x0128)
>  #define OMAP3630_CONTROL_FUSE_OPP100_VDD2
> (OMAP2_CONTROL_GENERAL + 0x012C)
>
> +/* OMAP44xx control efuse offsets */
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
> +#define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
> +#define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
> +
>  /* AM35XX only CONTROL_GENERAL register offsets */
>  #define AM35XX_CONTROL_MSUSPENDMUX_6
> (OMAP2_CONTROL_GENERAL + 0x0038)
>  #define AM35XX_CONTROL_DEVCONF2
> (OMAP2_CONTROL_GENERAL + 0x0310)
> diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-
> omap2/voltage.c
> index b27fa4f..ed6079c 100644
> --- a/arch/arm/mach-omap2/voltage.c
> +++ b/arch/arm/mach-omap2/voltage.c
> @@ -29,6 +29,10 @@
>  #include <plat/voltage.h>
>
>  #include "prm-regbits-34xx.h"
> +#include "prm-regbits-44xx.h"
> +#include "prm44xx.h"
> +#include "prcm44xx.h"
> +#include "prminst44xx.h"
>  #include "control.h"
>
>  #define VP_IDLE_TIMEOUT		200
> @@ -190,6 +194,51 @@ static struct omap_vdd_info
> omap3_vdd_info[] = {
>
>  #define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info)
>

My comments on the patch

[PATCH v6 01/10] OMAP3: PM: Adding voltage driver support

are applicable here. Please refer to

http://marc.info/?l=linux-omap&m=129355306112127&w=2

for more details.

Best Regards,

Anand S Sawant

> +/* OMAP4 VDD sturctures */
> +static struct omap_vdd_info omap4_vdd_info[] = {
> +	{
> +		.vp_offs = {
> +			.vpconfig =
> OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
> +			.vstepmin =
> OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
> +			.vstepmax =
> OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
> +			.vlimitto =
> OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
> +			.vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
> +			.voltage =
> OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
> +		},
> +		.voltdm = {
> +			.name = "mpu",
> +		},
> +	},
> +	{
> +		.vp_offs = {
> +			.vpconfig =
> OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
> +			.vstepmin =
> OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
> +			.vstepmax =
> OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
> +			.vlimitto =
> OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
> +			.vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
> +			.voltage =
> OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
> +		},
> +		.voltdm = {
> +			.name = "iva",
> +		},
> +	},
> +	{
> +		.vp_offs = {
> +			.vpconfig =
> OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
> +			.vstepmin =
> OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
> +			.vstepmax =
> OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
> +			.vlimitto =
> OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
> +			.vstatus =
> OMAP4_PRM_VP_CORE_STATUS_OFFSET,
> +			.voltage =
> OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
> +		},
> +		.voltdm = {
> +			.name = "core",
> +		},
> +	},
> +};
> +
> +#define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info)
> +
>  /*
>   * Structures containing OMAP3430/OMAP3630 voltage
> supported and various
>   * voltage dependent data for each VDD.
> @@ -234,6 +283,31 @@ static struct omap_volt_data
> omap36xx_vddcore_volt_data[] = {
>  	VOLT_DATA_DEFINE(0, 0, 0, 0),
>  };
>
> +/*
> + * Structures containing OMAP4430 voltage supported and
> various
> + * voltage dependent data for each VDD.
> + */
> +static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] =
> {
> +	VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV,
> OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
> +	VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV,
> OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
> +	VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV,
> OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
> +	VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV,
> OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
> +	VOLT_DATA_DEFINE(0, 0, 0, 0),
> +};
> +
> +static struct omap_volt_data omap44xx_vdd_iva_volt_data[] =
> {
> +	VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV,
> OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
> +	VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV,
> OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
> +	VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV,
> OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
> +	VOLT_DATA_DEFINE(0, 0, 0, 0),
> +};
> +
> +static struct omap_volt_data omap44xx_vdd_core_volt_data[]
> = {
> +	VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV,
> OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
> +	VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV,
> OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
> +	VOLT_DATA_DEFINE(0, 0, 0, 0),
> +};
> +
>  static struct dentry *voltage_dir;
>
>  /* Init function pointers */
> @@ -250,6 +324,17 @@ static void omap3_voltage_write_reg(u32
> val, u16 mod, u8 offset)
>  	omap2_prm_write_mod_reg(val, mod, offset);
>  }
>
> +static u32 omap4_voltage_read_reg(u16 mod, u8 offset)
> +{
> +	return
> omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
> +					mod, offset);
> +}
> +
> +static void omap4_voltage_write_reg(u32 val, u16 mod, u8
> offset)
> +{
> +	omap4_prminst_write_inst_reg(val,
> OMAP4430_PRM_PARTITION, mod, offset);
> +}
> +
>  /* Voltage debugfs support */
>  static int vp_volt_debug_get(void *data, u64 *val)
>  {
> @@ -841,6 +926,195 @@ static int __init
> omap3_vdd_data_configure(struct omap_vdd_info *vdd)
>  	return 0;
>  }
>
> +/* OMAP4 specific voltage init functions */
> +static void __init omap4_vc_init(struct omap_vdd_info *vdd)
> +{
> +	u32 vc_val;
> +	u16 mod;
> +	static bool is_initialized;
> +
> +	if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
> +		pr_err("%s: PMIC info requried to configure vc
> for"
> +			"vdd_%s not populated.Hence cannot
> initialize vc\n",
> +			__func__, vdd->voltdm.name);
> +		return;
> +	}
> +
> +	if (!vdd->read_reg || !vdd->write_reg) {
> +		pr_err("%s: No read/write API for accessing
> vdd_%s regs\n",
> +			__func__, vdd->voltdm.name);
> +		return;
> +	}
> +
> +	mod = vdd->vc_reg.prm_mod;
> +
> +	/* Set up the SMPS_SA(i2c slave address in VC */
> +	vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
> +	vc_val &= ~vdd->vc_reg.smps_sa_mask;
> +	vc_val |= vdd->pmic_info->i2c_slave_addr << vdd-
> >vc_reg.smps_sa_shift;
> +	vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
> +
> +	/* Setup the VOLRA(pmic reg addr) in VC */
> +	vc_val = vdd->read_reg(mod, vdd-
> >vc_reg.smps_volra_reg);
> +	vc_val &= ~vdd->vc_reg.smps_volra_mask;
> +	vc_val |= vdd->pmic_info->pmic_reg << vdd-
> >vc_reg.smps_volra_shift;
> +	vdd->write_reg(vc_val, mod, vdd-
> >vc_reg.smps_volra_reg);
> +
> +	/* TODO: Configure setup times and CMD_VAL values*/
> +
> +	if (is_initialized)
> +		return;
> +
> +	/* Generic VC parameters init */
> +	vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK |
> OMAP4430_CMD_VDD_MPU_L_MASK |
> +		OMAP4430_RAV_VDD_IVA_L_MASK |
> OMAP4430_CMD_VDD_IVA_L_MASK |
> +		OMAP4430_RAV_VDD_CORE_L_MASK |
> OMAP4430_CMD_VDD_CORE_L_MASK);
> +	vdd->write_reg(vc_val, mod,
> OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
> +
> +	vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 <<
> OMAP4430_SCLH_SHIFT);
> +	vdd->write_reg(vc_val, mod,
> OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
> +
> +	is_initialized = true;
> +}
> +
> +/* Sets up all the VDD related info for OMAP4 */
> +static int __init omap4_vdd_data_configure(struct
> omap_vdd_info *vdd)
> +{
> +	struct clk *sys_ck;
> +	u32 sys_clk_speed, timeout_val, waittime;
> +
> +	if (!vdd->pmic_info) {
> +		pr_err("%s: PMIC info requried to configure
> vdd_%s not"
> +			"populated.Hence cannot initialize
> vdd_%s\n",
> +			__func__, vdd->voltdm.name, vdd-
> >voltdm.name);
> +		return -EINVAL;
> +	}
> +
> +	if (!strcmp(vdd->voltdm.name, "mpu")) {
> +		vdd->volt_data = omap44xx_vdd_mpu_volt_data;
> +		vdd->vp_reg.tranxdone_status =
> +				OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
> +		vdd->vc_reg.cmdval_reg =
> OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
> +		vdd->vc_reg.smps_sa_shift =
> +
> 	OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT;
> +		vdd->vc_reg.smps_sa_mask =
> +
> 	OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK;
> +		vdd->vc_reg.smps_volra_shift =
> OMAP4430_VOLRA_VDD_MPU_L_SHIFT;
> +		vdd->vc_reg.smps_volra_mask =
> OMAP4430_VOLRA_VDD_MPU_L_MASK;
> +		vdd->vc_reg.voltsetup_reg =
> +
> 	OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET;
> +		vdd->prm_irqst_reg =
> OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
> +	} else if (!strcmp(vdd->voltdm.name, "core")) {
> +		vdd->volt_data = omap44xx_vdd_core_volt_data;
> +		vdd->vp_reg.tranxdone_status =
> +				OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
> +		vdd->vc_reg.cmdval_reg =
> +
> 	OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
> +		vdd->vc_reg.smps_sa_shift =
> OMAP4430_SA_VDD_CORE_L_0_6_SHIFT;
> +		vdd->vc_reg.smps_sa_mask =
> OMAP4430_SA_VDD_CORE_L_0_6_MASK;
> +		vdd->vc_reg.smps_volra_shift =
> OMAP4430_VOLRA_VDD_CORE_L_SHIFT;
> +		vdd->vc_reg.smps_volra_mask =
> OMAP4430_VOLRA_VDD_CORE_L_MASK;
> +		vdd->vc_reg.voltsetup_reg =
> +
> 	OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET;
> +		vdd->prm_irqst_reg =
> OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
> +	} else if (!strcmp(vdd->voltdm.name, "iva")) {
> +		vdd->volt_data = omap44xx_vdd_iva_volt_data;
> +		vdd->vp_reg.tranxdone_status =
> +				OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
> +		vdd->vc_reg.cmdval_reg =
> OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
> +		vdd->vc_reg.smps_sa_shift =
> +
> 	OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT;
> +		vdd->vc_reg.smps_sa_mask =
> +
> 	OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK;
> +		vdd->vc_reg.smps_volra_shift =
> OMAP4430_VOLRA_VDD_IVA_L_SHIFT;
> +		vdd->vc_reg.smps_volra_mask =
> OMAP4430_VOLRA_VDD_IVA_L_MASK;
> +		vdd->vc_reg.voltsetup_reg =
> +
> 	OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET;
> +		vdd->prm_irqst_reg =
> OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
> +	} else {
> +		pr_warning("%s: vdd_%s does not exisit in
> OMAP4\n",
> +			__func__, vdd->voltdm.name);
> +		return -EINVAL;
> +	}
> +
> +	/*
> +	 * Sys clk rate is require to calculate vp timeout
> value and
> +	 * smpswaittimemin and smpswaittimemax.
> +	 */
> +	sys_ck = clk_get(NULL, "sys_clkin_ck");
> +	if (IS_ERR(sys_ck)) {
> +		pr_warning("%s: Could not get the sys clk to
> calculate"
> +			"various vdd_%s params\n", __func__, vdd-
> >voltdm.name);
> +		return -EINVAL;
> +	}
> +	sys_clk_speed = clk_get_rate(sys_ck);
> +	clk_put(sys_ck);
> +	/* Divide to avoid overflow */
> +	sys_clk_speed /= 1000;
> +
> +	/* Generic voltage parameters */
> +	vdd->curr_volt = 1200000;
> +	vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
> +	vdd->read_reg = omap4_voltage_read_reg;
> +	vdd->write_reg = omap4_voltage_write_reg;
> +	vdd->volt_scale = vp_forceupdate_scale_voltage;
> +	vdd->vp_enabled = false;
> +
> +	/* VC parameters */
> +	vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
> +	vdd->vc_reg.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET;
> +	vdd->vc_reg.smps_volra_reg =
> OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET;
> +	vdd->vc_reg.bypass_val_reg =
> OMAP4_PRM_VC_VAL_BYPASS_OFFSET;
> +	vdd->vc_reg.data_shift = OMAP4430_DATA_SHIFT;
> +	vdd->vc_reg.slaveaddr_shift =
> OMAP4430_SLAVEADDR_SHIFT;
> +	vdd->vc_reg.regaddr_shift = OMAP4430_REGADDR_SHIFT;
> +	vdd->vc_reg.valid = OMAP4430_VALID_MASK;
> +	vdd->vc_reg.cmd_on_shift = OMAP4430_ON_SHIFT;
> +	vdd->vc_reg.cmd_on_mask = OMAP4430_ON_MASK;
> +	vdd->vc_reg.cmd_onlp_shift = OMAP4430_ONLP_SHIFT;
> +	vdd->vc_reg.cmd_ret_shift = OMAP4430_RET_SHIFT;
> +	vdd->vc_reg.cmd_off_shift = OMAP4430_OFF_SHIFT;
> +
> +	vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
> +
> +	/* VPCONFIG bit fields */
> +	vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info-
> >vp_erroroffset <<
> +				 OMAP4430_ERROROFFSET_SHIFT);
> +	vdd->vp_reg.vpconfig_errorgain_mask =
> OMAP4430_ERRORGAIN_MASK;
> +	vdd->vp_reg.vpconfig_errorgain_shift =
> OMAP4430_ERRORGAIN_SHIFT;
> +	vdd->vp_reg.vpconfig_initvoltage_shift =
> OMAP4430_INITVOLTAGE_SHIFT;
> +	vdd->vp_reg.vpconfig_initvoltage_mask =
> OMAP4430_INITVOLTAGE_MASK;
> +	vdd->vp_reg.vpconfig_timeouten =
> OMAP4430_TIMEOUTEN_MASK;
> +	vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK;
> +	vdd->vp_reg.vpconfig_forceupdate =
> OMAP4430_FORCEUPDATE_MASK;
> +	vdd->vp_reg.vpconfig_vpenable =
> OMAP4430_VPENABLE_MASK;
> +
> +	/* VSTEPMIN VSTEPMAX bit fields */
> +	waittime = ((vdd->pmic_info->step_size / vdd-
> >pmic_info->slew_rate) *
> +				sys_clk_speed) / 1000;
> +	vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
> +	vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
> +	vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info-
> >vp_vstepmin;
> +	vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info-
> >vp_vstepmax;
> +	vdd->vp_reg.vstepmin_smpswaittimemin_shift =
> +			OMAP4430_SMPSWAITTIMEMIN_SHIFT;
> +	vdd->vp_reg.vstepmax_smpswaittimemax_shift =
> +			OMAP4430_SMPSWAITTIMEMAX_SHIFT;
> +	vdd->vp_reg.vstepmin_stepmin_shift =
> OMAP4430_VSTEPMIN_SHIFT;
> +	vdd->vp_reg.vstepmax_stepmax_shift =
> OMAP4430_VSTEPMAX_SHIFT;
> +
> +	/* VLIMITTO bit fields */
> +	timeout_val = (sys_clk_speed * vdd->pmic_info-
> >vp_timeout_us) / 1000;
> +	vdd->vp_reg.vlimitto_timeout = timeout_val;
> +	vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info-
> >vp_vddmin;
> +	vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info-
> >vp_vddmax;
> +	vdd->vp_reg.vlimitto_vddmin_shift =
> OMAP4430_VDDMIN_SHIFT;
> +	vdd->vp_reg.vlimitto_vddmax_shift =
> OMAP4430_VDDMAX_SHIFT;
> +	vdd->vp_reg.vlimitto_timeout_shift =
> OMAP4430_TIMEOUT_SHIFT;
> +
> +	return 0;
> +}
> +
>  /* Public functions */
>  /**
>   * omap_voltage_get_nom_volt() - Gets the current non-auto-
> compensated voltage
> @@ -1283,6 +1557,11 @@ static int __init
> omap_voltage_early_init(void)
>  		nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD;
>  		vc_init = omap3_vc_init;
>  		vdd_data_configure = omap3_vdd_data_configure;
> +	} else if (cpu_is_omap44xx()) {
> +		vdd_info = omap4_vdd_info;
> +		nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD;
> +		vc_init = omap4_vc_init;
> +		vdd_data_configure = omap4_vdd_data_configure;
>  	} else {
>  		pr_warning("%s: voltage driver support not
> added\n", __func__);
>  	}
> diff --git a/arch/arm/plat-omap/include/plat/voltage.h
> b/arch/arm/plat-omap/include/plat/voltage.h
> index 2f4f59a..0ff1233 100644
> --- a/arch/arm/plat-omap/include/plat/voltage.h
> +++ b/arch/arm/plat-omap/include/plat/voltage.h
> @@ -44,6 +44,18 @@
>  #define OMAP3630_VDD_CORE_OPP50_UV		1000000
>  #define OMAP3630_VDD_CORE_OPP100_UV		1200000
>
> +#define OMAP4430_VDD_MPU_OPP50_UV		930000
> +#define OMAP4430_VDD_MPU_OPP100_UV		1100000
> +#define OMAP4430_VDD_MPU_OPPTURBO_UV		1260000
> +#define OMAP4430_VDD_MPU_OPPNITRO_UV		1350000
> +
> +#define OMAP4430_VDD_IVA_OPP50_UV		930000
> +#define OMAP4430_VDD_IVA_OPP100_UV		1100000
> +#define OMAP4430_VDD_IVA_OPPTURBO_UV		1260000
> +
> +#define OMAP4430_VDD_CORE_OPP50_UV		930000
> +#define OMAP4430_VDD_CORE_OPP100_UV		1100000
> +
>  /**
>   * struct voltagedomain - omap voltage domain global
> structure.
>   * @name:	Name of the voltage domain which can be used as
> a unique
> --
> 1.7.0.4