From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/4] msm: scm: Fix improper register assignment
Date: Fri, 25 Feb 2011 11:22:03 -0800 [thread overview]
Message-ID: <4D68015B.1050409@codeaurora.org> (raw)
In-Reply-To: <1298640219.958.74.camel@e102144-lin.cambridge.arm.com>
On 02/25/2011 05:23 AM, Will Deacon wrote:
> On Thu, 2011-02-24 at 18:44 +0000, Stephen Boyd wrote:
>> Assign the registers used in the inline assembly immediately
>> before the inline assembly block. This ensures the compiler
>> doesn't optimize away dead register assignments when it
>> shouldn't.
>>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>> arch/arm/mach-msm/scm.c | 7 +++++--
>> 1 files changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c
>> index ba57b5a..5eddf54 100644
>> --- a/arch/arm/mach-msm/scm.c
>> +++ b/arch/arm/mach-msm/scm.c
>> @@ -264,13 +264,16 @@ u32 scm_get_version(void)
>> {
>> int context_id;
>> static u32 version = -1;
>> - register u32 r0 asm("r0") = 0x1 << 8;
>> - register u32 r1 asm("r1") = (u32)&context_id;
>> + register u32 r0 asm("r0");
>> + register u32 r1 asm("r1");
>>
>> if (version != -1)
>> return version;
>>
>> mutex_lock(&scm_lock);
>> +
>> + r0 = 0x1 << 8;
>> + r1 = (u32)&context_id;
>> asm volatile(
>> __asmeq("%0", "r1")
>> __asmeq("%1", "r0")
>
>
> Whoa, have you seen the compiler `optimise' the original assignments
> away? Since there is a use in the asm block, the definition shouldn't
> be omitted. What toolchain are you using
Yes I've seen the r0 and r1 assignments get optimized away. I'm
suspecting it's because the mutex_lock() is between the assignments and
usage. I'm guessing the assignment to r0 and r1 are actually generated,
but then they're optimized away because the mutex_lock() isn't inlined
and thus r0 and r1 assigned to something that isn't &scm_lock can be
"safely" removed (dead register assignments). I can't confirm any of
this since I don't know what gcc is doing internally or even how to
probe what it's doing (yeah I know I could go read gcc sources).
Suggestions?
I've seen it with two different compilers so far:
gcc (Sourcery G++ Lite 2010.09-50) 4.5.1
arm-eabi-gcc (GCC) 4.4.0
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2011-02-25 19:22 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-24 18:44 [PATCH 0/4] SCM fixes and updates Stephen Boyd
2011-02-24 18:44 ` [PATCH 1/4] msm: scm: Mark inline asm as volatile Stephen Boyd
2011-02-25 11:56 ` Will Deacon
2011-02-25 19:05 ` Stephen Boyd
2011-02-26 18:12 ` David Brown
2011-02-26 19:43 ` Nicolas Pitre
2011-02-27 17:41 ` David Brown
2011-02-28 2:21 ` Nicolas Pitre
2011-02-27 11:10 ` Will Deacon
2011-02-27 17:38 ` David Brown
2011-03-01 10:30 ` Will Deacon
2011-02-24 18:44 ` [PATCH 2/4] msm: scm: Fix improper register assignment Stephen Boyd
2011-02-25 13:23 ` Will Deacon
2011-02-25 19:22 ` Stephen Boyd [this message]
2011-02-26 5:09 ` Saravana Kannan
2011-02-26 8:47 ` Russell King - ARM Linux
2011-02-26 17:58 ` David Brown
2011-02-26 20:04 ` Nicolas Pitre
2011-03-01 10:37 ` Will Deacon
2011-03-01 21:29 ` Saravana Kannan
2011-03-02 0:02 ` Nicolas Pitre
2011-03-01 13:54 ` Will Deacon
2011-02-24 18:44 ` [PATCH 3/4] msm: scm: Check for interruption immediately Stephen Boyd
2011-02-24 18:44 ` [PATCH 4/4] msm: scm: Get cacheline size from CTR Stephen Boyd
2011-02-24 19:01 ` Thomas Gleixner
2011-02-24 19:44 ` Stephen Boyd
2011-02-24 19:56 ` Thomas Gleixner
2011-03-01 4:21 ` Stephen Boyd
2011-02-24 19:32 ` Sergei Shtylyov
2011-02-24 19:50 ` Stephen Boyd
2011-02-24 19:55 ` Russell King - ARM Linux
2011-03-09 19:29 ` [PATCH 0/4] SCM fixes and updates Stephen Boyd
2011-03-10 20:06 ` David Brown
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