* [PATCH v2 1/4] OMAP3: hwmod data: add mmu data for iva and isp
2011-03-07 7:53 [PATCH v2 0/4] OMAP: iommu: hwmod support and runtime PM Omar Ramirez Luna
@ 2011-03-07 7:53 ` Omar Ramirez Luna
2011-03-07 7:53 ` [PATCH v2 2/4] OMAP4: hwmod data: add mmu hwmod for ipu and dsp Omar Ramirez Luna
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Omar Ramirez Luna @ 2011-03-07 7:53 UTC (permalink / raw)
To: linux-arm-kernel
Add mmu hwmod data for iva and isp.
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 135 ++++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/iommu.h | 10 ++
2 files changed, 145 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index e2792cf..90eebee 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -27,6 +27,7 @@
#include <plat/mcbsp.h>
#include <plat/mcspi.h>
#include <plat/dmtimer.h>
+#include <plat/iommu.h>
#include "omap_hwmod_common_data.h"
@@ -3332,6 +3333,134 @@ static struct omap_hwmod omap34xx_mcspi4 = {
};
/*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
+ .name = "mmu",
+ .sysc = &mmu_sysc,
+};
+
+/* isp mmu */
+
+static struct omap_mmu_dev_attr isp_mmu_dev_attr = {
+ .da_start = 0x0,
+ .da_end = 0xfffff000,
+ .nr_tlb_entries = 8,
+};
+
+static struct omap_hwmod omap3xxx_isp_mmu_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_isp_mmu_irqs[] = {
+ { .irq = 24 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_isp_mmu_addrs[] = {
+ {
+ .pa_start = 0x480bd400,
+ .pa_end = 0x480bd47f,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core -> isp mmu */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__isp_mmu = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_isp_mmu_hwmod,
+ .addr = omap3xxx_isp_mmu_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_isp_mmu_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* isp mmu slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_isp_mmu_slaves[] = {
+ &omap3xxx_l4_core__isp_mmu,
+};
+
+static struct omap_hwmod omap3xxx_isp_mmu_hwmod = {
+ .name = "isp_mmu",
+ .class = &omap3xxx_mmu_hwmod_class,
+ .mpu_irqs = omap3xxx_isp_mmu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_isp_mmu_irqs),
+ .main_clk = "cam_ick",
+ .dev_attr = &isp_mmu_dev_attr,
+ .slaves = omap3xxx_isp_mmu_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_isp_mmu_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ .flags = HWMOD_NO_IDLEST,
+};
+
+/* iva mmu */
+
+static struct omap_mmu_dev_attr iva_mmu_dev_attr = {
+ .da_start = 0x11000000,
+ .da_end = 0xfffff000,
+ .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap3xxx_iva_mmu_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_iva_mmu_irqs[] = {
+ { .irq = 28 },
+};
+
+static struct omap_hwmod_rst_info omap3xxx_iva_mmu_resets[] = {
+ { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_iva_mmu_addrs[] = {
+ {
+ .pa_start = 0x5d000000,
+ .pa_end = 0x5d00007f,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l3_main -> iva mmu */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__iva_mmu = {
+ .master = &omap3xxx_l3_main_hwmod,
+ .slave = &omap3xxx_iva_mmu_hwmod,
+ .addr = omap3xxx_iva_mmu_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_iva_mmu_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iva mmu slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_iva_mmu_slaves[] = {
+ &omap3xxx_l3_main__iva_mmu,
+};
+
+static struct omap_hwmod omap3xxx_iva_mmu_hwmod = {
+ .name = "iva_mmu",
+ .class = &omap3xxx_mmu_hwmod_class,
+ .mpu_irqs = omap3xxx_iva_mmu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_iva_mmu_irqs),
+ .rst_lines = omap3xxx_iva_mmu_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_mmu_resets),
+ .main_clk = "iva2_ck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = OMAP3430_IVA2_MOD,
+ },
+ },
+ .dev_attr = &iva_mmu_dev_attr,
+ .slaves = omap3xxx_iva_mmu_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_iva_mmu_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ .flags = HWMOD_NO_IDLEST | HWMOD_INIT_NO_RESET,
+};
+
+/*
* usbhsotg
*/
static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
@@ -3643,6 +3772,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap34xx_mcspi3,
&omap34xx_mcspi4,
+ /* mmu class */
+ &omap3xxx_isp_mmu_hwmod,
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+ &omap3xxx_iva_mmu_hwmod,
+#endif
+
/* usbotg class */
&omap3xxx_usbhsotg_hwmod,
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 174f1b9..b0d43ce 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -102,6 +102,16 @@ struct iommu_functions {
ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
};
+/* omap_mmu_dev_attr - OMAP mmu device attributes for omap_hwmod
+ * @nr_tlb_entries: number of entries supported by the translation look-aside
+ * buffer (TLB).
+ */
+struct omap_mmu_dev_attr {
+ u32 da_start;
+ u32 da_end;
+ int nr_tlb_entries;
+};
+
struct iommu_platform_data {
const char *name;
const char *clk_name;
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 2/4] OMAP4: hwmod data: add mmu hwmod for ipu and dsp
2011-03-07 7:53 [PATCH v2 0/4] OMAP: iommu: hwmod support and runtime PM Omar Ramirez Luna
2011-03-07 7:53 ` [PATCH v2 1/4] OMAP3: hwmod data: add mmu data for iva and isp Omar Ramirez Luna
@ 2011-03-07 7:53 ` Omar Ramirez Luna
2011-03-07 12:55 ` Cousson, Benoit
2011-03-07 7:53 ` [PATCH v2 3/4] OMAP3/4: iommu: migrate to hwmod framework Omar Ramirez Luna
2011-03-07 7:53 ` [PATCH v2 4/4] OMAP3/4: iommu: adapt to runtime pm Omar Ramirez Luna
3 siblings, 1 reply; 9+ messages in thread
From: Omar Ramirez Luna @ 2011-03-07 7:53 UTC (permalink / raw)
To: linux-arm-kernel
Add mmu hwmod data for ipu and dsp.
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 156 +++++++++++++++++++++++++--
1 files changed, 144 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7dbcdf7..149d694 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -27,6 +27,7 @@
#include <plat/mcspi.h>
#include <plat/mcbsp.h>
#include <plat/mmc.h>
+#include <plat/iommu.h>
#include "omap_hwmod_common_data.h"
@@ -990,10 +991,6 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
};
-static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
- { .name = "mmu_cache", .rst_shift = 1 },
-};
-
static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
{ .name = "dsp", .rst_shift = 0 },
};
@@ -1045,8 +1042,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
.class = &omap44xx_dsp_hwmod_class,
.mpu_irqs = omap44xx_dsp_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
- .rst_lines = omap44xx_dsp_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
.main_clk = "dsp_fck",
.prcm = {
.omap4 = {
@@ -2323,10 +2318,6 @@ static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
{ .name = "cpu1", .rst_shift = 1 },
};
-static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
- { .name = "mmu_cache", .rst_shift = 2 },
-};
-
/* ipu master ports */
static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
&omap44xx_ipu__l3_main_2,
@@ -2380,8 +2371,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
.class = &omap44xx_ipu_hwmod_class,
.mpu_irqs = omap44xx_ipu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
- .rst_lines = omap44xx_ipu_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
.main_clk = "ipu_fck",
.prcm = {
.omap4 = {
@@ -3711,6 +3700,145 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
};
/*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
+ .name = "mmu",
+ .sysc = &mmu_sysc,
+};
+
+/* ipu mmu */
+
+static struct omap_mmu_dev_attr ipu_mmu_dev_attr = {
+ .da_start = 0x0,
+ .da_end = 0xfffff000,
+ .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_ipu_mmu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_ipu_mmu_irqs[] = {
+ { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
+};
+
+static struct omap_hwmod_rst_info omap44xx_ipu_mmu_resets[] = {
+ { .name = "mmu_cache", .rst_shift = 2 },
+};
+
+static struct omap_hwmod_addr_space omap44xx_ipu_mmu_addrs[] = {
+ {
+ .pa_start = 0x55082000,
+ .pa_end = 0x550820ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l3_main_1 -> ipu mmu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__ipu_mmu = {
+ .master = &omap44xx_l3_main_1_hwmod,
+ .slave = &omap44xx_ipu_mmu_hwmod,
+ .addr = omap44xx_ipu_mmu_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_ipu_mmu_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ipu mmu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_ipu_mmu_slaves[] = {
+ &omap44xx_l3_main_1__ipu_mmu,
+};
+
+static struct omap_hwmod omap44xx_ipu_mmu_hwmod = {
+ .name = "ipu_mmu",
+ .class = &omap44xx_mmu_hwmod_class,
+ .mpu_irqs = omap44xx_ipu_mmu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_mmu_irqs),
+ .rst_lines = omap44xx_ipu_mmu_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_mmu_resets),
+ .main_clk = "ipu_fck",
+ .prcm = {
+ .omap4 = {
+ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+ },
+ },
+ .slaves = omap44xx_ipu_mmu_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_mmu_slaves),
+ .dev_attr = &ipu_mmu_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .flags = HWMOD_INIT_NO_RESET,
+};
+
+/* dsp mmu */
+
+static struct omap_mmu_dev_attr dsp_mmu_dev_attr = {
+ .da_start = 0x0,
+ .da_end = 0xfffff000,
+ .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_dsp_mmu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dsp_mmu_irqs[] = {
+ { .irq = 28 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_rst_info omap44xx_dsp_mmu_resets[] = {
+ { .name = "mmu_cache", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dsp_mmu_addrs[] = {
+ {
+ .pa_start = 0x4a066000,
+ .pa_end = 0x4a0660ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l3_main_1 -> dsp mmu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dsp_mmu = {
+ .master = &omap44xx_l3_main_1_hwmod,
+ .slave = &omap44xx_dsp_mmu_hwmod,
+ .addr = omap44xx_dsp_mmu_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dsp_mmu_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dsp mmu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dsp_mmu_slaves[] = {
+ &omap44xx_l3_main_1__dsp_mmu,
+};
+
+static struct omap_hwmod omap44xx_dsp_mmu_hwmod = {
+ .name = "dsp_mmu",
+ .class = &omap44xx_mmu_hwmod_class,
+ .mpu_irqs = omap44xx_dsp_mmu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_mmu_irqs),
+ .rst_lines = omap44xx_dsp_mmu_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_mmu_resets),
+ .main_clk = "dsp_fck",
+ .prcm = {
+ .omap4 = {
+ .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+ },
+ },
+ .slaves = omap44xx_dsp_mmu_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_mmu_slaves),
+ .dev_attr = &dsp_mmu_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .flags = HWMOD_INIT_NO_RESET,
+};
+
+/*
* 'smartreflex' class
* smartreflex module (monitor silicon performance and outputs a measure of
* performance error)
@@ -5102,6 +5230,10 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* mpu class */
&omap44xx_mpu_hwmod,
+ /* mmu class */
+ &omap44xx_ipu_mmu_hwmod,
+ &omap44xx_dsp_mmu_hwmod,
+
/* smartreflex class */
&omap44xx_smartreflex_core_hwmod,
&omap44xx_smartreflex_iva_hwmod,
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 2/4] OMAP4: hwmod data: add mmu hwmod for ipu and dsp
2011-03-07 7:53 ` [PATCH v2 2/4] OMAP4: hwmod data: add mmu hwmod for ipu and dsp Omar Ramirez Luna
@ 2011-03-07 12:55 ` Cousson, Benoit
2011-03-07 19:01 ` Ramirez Luna, Omar
0 siblings, 1 reply; 9+ messages in thread
From: Cousson, Benoit @ 2011-03-07 12:55 UTC (permalink / raw)
To: linux-arm-kernel
Hi Omar,
I have some concern about the introduction of a hwmod that does not
match the actual HW capability. MMU does exist, but there is no SW
control for it. In fact the only control available is for mmu + cache +
logic, and that's why the MMU is handle today under the main DSP/IPU hwmod.
Here you are just duplicating dsp_hwmod and ipu_hwmod with dsp_mmu_hwmod
/ ipu_mmu_hwmod and adding some memory space for the mmu part.
In that case, you can still use the previous name and add the missing
entries in it.
The only advantage I can see is the usage of a common class that will
allow you to handle both DSP and IPU using the same "MMU" driver.
So, what are you going to do with the remaining entries for dsp_hwmod
and ipu_hwmod?
If these two become useless and only the mmu part is useful, we can
potentially rename them like you did, but without keeping the original.
On 3/7/2011 8:53 AM, Ramirez Luna, Omar wrote:
> Add mmu hwmod data for ipu and dsp.
>
> Signed-off-by: Omar Ramirez Luna<omar.ramirez@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 156 +++++++++++++++++++++++++--
> 1 files changed, 144 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index 7dbcdf7..149d694 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -27,6 +27,7 @@
> #include<plat/mcspi.h>
> #include<plat/mcbsp.h>
> #include<plat/mmc.h>
> +#include<plat/iommu.h>
>
> #include "omap_hwmod_common_data.h"
>
> @@ -990,10 +991,6 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
> { .irq = 28 + OMAP44XX_IRQ_GIC_START },
> };
>
> -static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
> - { .name = "mmu_cache", .rst_shift = 1 },
> -};
> -
> static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
> { .name = "dsp", .rst_shift = 0 },
> };
> @@ -1045,8 +1042,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
> .class =&omap44xx_dsp_hwmod_class,
> .mpu_irqs = omap44xx_dsp_irqs,
> .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
> - .rst_lines = omap44xx_dsp_resets,
> - .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
> .main_clk = "dsp_fck",
> .prcm = {
> .omap4 = {
> @@ -2323,10 +2318,6 @@ static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
> { .name = "cpu1", .rst_shift = 1 },
> };
>
> -static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
> - { .name = "mmu_cache", .rst_shift = 2 },
> -};
> -
> /* ipu master ports */
> static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
> &omap44xx_ipu__l3_main_2,
> @@ -2380,8 +2371,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
> .class =&omap44xx_ipu_hwmod_class,
> .mpu_irqs = omap44xx_ipu_irqs,
> .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
> - .rst_lines = omap44xx_ipu_resets,
> - .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
> .main_clk = "ipu_fck",
> .prcm = {
> .omap4 = {
> @@ -3711,6 +3700,145 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
> };
>
> /*
> + * 'mmu' class
> + * The memory management unit performs virtual to physical address translation
> + * for its requestors.
> + */
> +
> +static struct omap_hwmod_class_sysconfig mmu_sysc = {
> + .rev_offs = 0x000,
> + .sysc_offs = 0x010,
> + .syss_offs = 0x014,
> + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
> + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> + .sysc_fields =&omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
> + .name = "mmu",
> + .sysc =&mmu_sysc,
> +};
> +
> +/* ipu mmu */
> +
> +static struct omap_mmu_dev_attr ipu_mmu_dev_attr = {
> + .da_start = 0x0,
> + .da_end = 0xfffff000,
> + .nr_tlb_entries = 32,
> +};
> +
> +static struct omap_hwmod omap44xx_ipu_mmu_hwmod;
Minor comment, but if we want to focus on the MMU as the main class,
then ipu and dsp will become just instance qualifiers, and thus the name
should be mmu_ipu and mmu_dsp.
Regards,
Benoit
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 2/4] OMAP4: hwmod data: add mmu hwmod for ipu and dsp
2011-03-07 12:55 ` Cousson, Benoit
@ 2011-03-07 19:01 ` Ramirez Luna, Omar
2011-03-08 21:29 ` Cousson, Benoit
0 siblings, 1 reply; 9+ messages in thread
From: Ramirez Luna, Omar @ 2011-03-07 19:01 UTC (permalink / raw)
To: linux-arm-kernel
Hi Benoit,
On Mon, Mar 7, 2011 at 6:55 AM, Cousson, Benoit <b-cousson@ti.com> wrote:
> Hi Omar,
>
> I have some concern about the introduction of a hwmod that does not match
> the actual HW capability. MMU does exist, but there is no SW control for it.
Maybe I'm missing something, but iommu (driver) is meant to control
isp, iva, ipu and dsp MMUs; even with a simple driver interfaced with
iommu, that had nothing to do with the modules mentioned, you could
still deassert the reset, enable the clocks, create your tables and
add entries, and so on... not that it would be useful for anybody
other than the real HW containing the MMU subsystem.
> In fact the only control available is for mmu + cache + logic, and that's
> why the MMU is handle today under the main DSP/IPU hwmod.
AFAIK, sysc configuration is missing from the old hwmods, I thought
separate hwmods gave:
- flexibility: so the system wouldn't dump_stack trying to read mmu
registers, because the user doesn't know ipu/dsp code should handle
the reset first.
- clarity: so iommu handles its own mmu hwmods instead of hard coding
the names of the pseudo hwmods containing the mmu.
> Here you are just duplicating dsp_hwmod and ipu_hwmod with dsp_mmu_hwmod /
> ipu_mmu_hwmod and adding some memory space for the mmu part.
>
> In that case, you can still use the previous name and add the missing
> entries in it.
>
> The only advantage I can see is the usage of a common class that will allow
> you to handle both DSP and IPU using the same "MMU" driver.
>
> So, what are you going to do with the remaining entries for dsp_hwmod and
> ipu_hwmod?
I think these can be removed, and iommu code can handle its own
hwmods; but if you want to update the old ones, that can be done too,
the tradeoff would be that iommu needs to know the name of the hwmods
with mmu data.
Regards,
Omar
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/4] OMAP4: hwmod data: add mmu hwmod for ipu and dsp
2011-03-07 19:01 ` Ramirez Luna, Omar
@ 2011-03-08 21:29 ` Cousson, Benoit
2011-03-08 23:21 ` Ramirez Luna, Omar
0 siblings, 1 reply; 9+ messages in thread
From: Cousson, Benoit @ 2011-03-08 21:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi Omar,
On 3/7/2011 8:01 PM, Ramirez Luna, Omar wrote:
> Hi Benoit,
>
> On Mon, Mar 7, 2011 at 6:55 AM, Cousson, Benoit<b-cousson@ti.com> wrote:
>> Hi Omar,
>>
>> I have some concern about the introduction of a hwmod that does not match
>> the actual HW capability. MMU does exist, but there is no SW control for it.
>
> Maybe I'm missing something, but iommu (driver) is meant to control
> isp, iva, ipu and dsp MMUs; even with a simple driver interfaced with
> iommu, that had nothing to do with the modules mentioned, you could
> still deassert the reset, enable the clocks, create your tables and
> add entries, and so on... not that it would be useful for anybody
> other than the real HW containing the MMU subsystem.
Yes, you are missing something... But to be honest I was not really
clear in my reply :-)
What I meant is that the mmu does not have any explicit PRCM module
enable control. The PRCM does control only the DSP as a whole. Since
hwmods are generated with a PRCM granularity, any sub module will not be
exposed by default.
The DSP core or Cortex M3 cores were exposed just because there is a
PRCM reset control line to control them.
Hence the current structures:
IPU for the main PRCM control (including MMU + UNICACHE)
IPU_C0 for Cortex M3 #1
IPU_C1 for Cortex M3 #2
>> In fact the only control available is for mmu + cache + logic, and that's
>> why the MMU is handle today under the main DSP/IPU hwmod.
>
> AFAIK, sysc configuration is missing from the old hwmods, I thought
> separate hwmods gave:
Yep, that one was missing because the hwmod was the ipu subsystem one.
But in fact the only ipu part that is accessible from the MPU is the MMU.
That's why I now think that renaming ipu with mmu_ipu is probably the
best thing to do.
> - flexibility: so the system wouldn't dump_stack trying to read mmu
> registers, because the user doesn't know ipu/dsp code should handle
> the reset first.
> - clarity: so iommu handles its own mmu hwmods instead of hard coding
> the names of the pseudo hwmods containing the mmu.
>
>> Here you are just duplicating dsp_hwmod and ipu_hwmod with dsp_mmu_hwmod /
>> ipu_mmu_hwmod and adding some memory space for the mmu part.
>>
>> In that case, you can still use the previous name and add the missing
>> entries in it.
>>
>> The only advantage I can see is the usage of a common class that will allow
>> you to handle both DSP and IPU using the same "MMU" driver.
>>
>> So, what are you going to do with the remaining entries for dsp_hwmod and
>> ipu_hwmod?
>
> I think these can be removed, and iommu code can handle its own
> hwmods; but if you want to update the old ones, that can be done too,
> the tradeoff would be that iommu needs to know the name of the hwmods
> with mmu data.
I've checked both IPU and DSP HW specs, and in the both cases, the mmu
IP is the only module with OCP port from the MPU in the relevant subsystem.
In that case, it is easier for me to remove that DSP and IPU hwmods and
move everything under the MMUs hwmods.
It will then highlight the re-use of the same IP in two different
subsystems.
I have now to modify the OMAP4 generator in order to provide the correct
data in the right format.
I'll try to do that before the end of this week. This will not have any
real impact for you except for the name change (mmu_ipu and mmu_dsp).
Is that OK for you?
Regards,
Benoit
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/4] OMAP4: hwmod data: add mmu hwmod for ipu and dsp
2011-03-08 21:29 ` Cousson, Benoit
@ 2011-03-08 23:21 ` Ramirez Luna, Omar
0 siblings, 0 replies; 9+ messages in thread
From: Ramirez Luna, Omar @ 2011-03-08 23:21 UTC (permalink / raw)
To: linux-arm-kernel
Hi Benoit,
On Tue, Mar 8, 2011 at 3:29 PM, Cousson, Benoit <b-cousson@ti.com> wrote:
> What I meant is that the mmu does not have any explicit PRCM module enable
> control. The PRCM does control only the DSP as a whole. Since hwmods are
> generated with a PRCM granularity, any sub module will not be exposed by
> default.
Ok, got it. Thanks for the reply.
> I've checked both IPU and DSP HW specs, and in the both cases, the mmu IP is
> the only module with OCP port from the MPU in the relevant subsystem.
> In that case, it is easier for me to remove that DSP and IPU hwmods and move
> everything under the MMUs hwmods.
> It will then highlight the re-use of the same IP in two different
> subsystems.
>
> I have now to modify the OMAP4 generator in order to provide the correct
> data in the right format.
>
> I'll try to do that before the end of this week. This will not have any real
> impact for you except for the name change (mmu_ipu and mmu_dsp).
>
> Is that OK for you?
No problem, once it is ready I'll update OMAP3 to mimic the name style.
Thanks,
Omar
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/4] OMAP3/4: iommu: migrate to hwmod framework
2011-03-07 7:53 [PATCH v2 0/4] OMAP: iommu: hwmod support and runtime PM Omar Ramirez Luna
2011-03-07 7:53 ` [PATCH v2 1/4] OMAP3: hwmod data: add mmu data for iva and isp Omar Ramirez Luna
2011-03-07 7:53 ` [PATCH v2 2/4] OMAP4: hwmod data: add mmu hwmod for ipu and dsp Omar Ramirez Luna
@ 2011-03-07 7:53 ` Omar Ramirez Luna
2011-03-07 7:53 ` [PATCH v2 4/4] OMAP3/4: iommu: adapt to runtime pm Omar Ramirez Luna
3 siblings, 0 replies; 9+ messages in thread
From: Omar Ramirez Luna @ 2011-03-07 7:53 UTC (permalink / raw)
To: linux-arm-kernel
Use hwmod data and device attributes to build and register an
omap device for iommu driver.
Now unused, remove platform device and resource data, handling
of sysconfig register for softreset purposes; and add device
latency in preparation for runtime PM.
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
arch/arm/mach-omap2/iommu2.c | 19 ----
arch/arm/mach-omap2/omap-iommu.c | 162 ++++++-------------------------
arch/arm/plat-omap/include/plat/iommu.h | 2 +-
3 files changed, 33 insertions(+), 150 deletions(-)
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index adb083e..a22d812 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -32,12 +32,8 @@
#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
-#define MMU_SYS_SOFTRESET (1 << 1)
#define MMU_SYS_AUTOIDLE 1
-/* SYSSTATUS */
-#define MMU_SYS_RESETDONE 1
-
/* IRQSTATUS & IRQENABLE */
#define MMU_IRQ_MULTIHITFAULT (1 << 4)
#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
@@ -88,7 +84,6 @@ static void __iommu_set_twl(struct iommu *obj, bool on)
static int omap2_iommu_enable(struct iommu *obj)
{
u32 l, pa;
- unsigned long timeout;
if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
return -EINVAL;
@@ -97,20 +92,6 @@ static int omap2_iommu_enable(struct iommu *obj)
if (!IS_ALIGNED(pa, SZ_16K))
return -EINVAL;
- iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
-
- timeout = jiffies + msecs_to_jiffies(20);
- do {
- l = iommu_read_reg(obj, MMU_SYSSTATUS);
- if (l & MMU_SYS_RESETDONE)
- break;
- } while (!time_after(jiffies, timeout));
-
- if (!(l & MMU_SYS_RESETDONE)) {
- dev_err(obj->dev, "can't take mmu out of reset\n");
- return -ENODEV;
- }
-
l = iommu_read_reg(obj, MMU_REVISION);
dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
(l >> 4) & 0xf, l & 0xf);
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 3fc5dc7..564a078 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -14,149 +14,51 @@
#include <plat/iommu.h>
#include <plat/irqs.h>
-
-struct iommu_device {
- resource_size_t base;
- int irq;
- struct iommu_platform_data pdata;
- struct resource res[2];
-};
-static struct iommu_device *devices;
-static int num_iommu_devices;
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct iommu_device omap3_devices[] = {
- {
- .base = 0x480bd400,
- .irq = 24,
- .pdata = {
- .name = "isp",
- .nr_tlb_entries = 8,
- .clk_name = "cam_ick",
- .da_start = 0x0,
- .da_end = 0xFFFFF000,
- },
- },
-#if defined(CONFIG_OMAP_IOMMU_IVA2)
- {
- .base = 0x5d000000,
- .irq = 28,
- .pdata = {
- .name = "iva2",
- .nr_tlb_entries = 32,
- .clk_name = "iva2_ck",
- .da_start = 0x11000000,
- .da_end = 0xFFFFF000,
- },
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+static struct omap_device_pm_latency iommu_latencies[] = {
+ [0] = {
+ .activate_func = omap_device_enable_hwmods,
+ .deactivate_func = omap_device_idle_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST
},
-#endif
};
-#define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices)
-static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
-#else
-#define omap3_devices NULL
-#define NR_OMAP3_IOMMU_DEVICES 0
-#define omap3_iommu_pdev NULL
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-static struct iommu_device omap4_devices[] = {
- {
- .base = OMAP4_MMU1_BASE,
- .irq = OMAP44XX_IRQ_DUCATI_MMU,
- .pdata = {
- .name = "ducati",
- .nr_tlb_entries = 32,
- .clk_name = "ducati_ick",
- .da_start = 0x0,
- .da_end = 0xFFFFF000,
- },
- },
-#if defined(CONFIG_MPU_TESLA_IOMMU)
- {
- .base = OMAP4_MMU2_BASE,
- .irq = INT_44XX_DSP_MMU,
- .pdata = {
- .name = "tesla",
- .nr_tlb_entries = 32,
- .clk_name = "tesla_ick",
- .da_start = 0x0,
- .da_end = 0xFFFFF000,
- },
- },
-#endif
-};
-#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
-static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
-#else
-#define omap4_devices NULL
-#define NR_OMAP4_IOMMU_DEVICES 0
-#define omap4_iommu_pdev NULL
-#endif
-
-static struct platform_device **omap_iommu_pdev;
-
-static int __init omap_iommu_init(void)
+static int omap_iommu_dev_init(struct omap_hwmod *oh, void *unused)
{
- int i, err;
- struct resource res[] = {
- { .flags = IORESOURCE_MEM },
- { .flags = IORESOURCE_IRQ },
- };
-
- if (cpu_is_omap34xx()) {
- devices = omap3_devices;
- omap_iommu_pdev = omap3_iommu_pdev;
- num_iommu_devices = NR_OMAP3_IOMMU_DEVICES;
- } else if (cpu_is_omap44xx()) {
- devices = omap4_devices;
- omap_iommu_pdev = omap4_iommu_pdev;
- num_iommu_devices = NR_OMAP4_IOMMU_DEVICES;
- } else
- return -ENODEV;
-
- for (i = 0; i < num_iommu_devices; i++) {
- struct platform_device *pdev;
- const struct iommu_device *d = &devices[i];
-
- pdev = platform_device_alloc("omap-iommu", i);
- if (!pdev) {
- err = -ENOMEM;
- goto err_out;
- }
+ struct omap_device *od;
+ struct iommu_platform_data pdata;
+ struct omap_mmu_dev_attr *a = (struct omap_mmu_dev_attr *)oh->dev_attr;
+ static int i;
+
+ pdata.name = oh->name;
+ pdata.clk_name = oh->main_clk;
+ pdata.nr_tlb_entries = a->nr_tlb_entries;
+ pdata.da_start = a->da_start;
+ pdata.da_end = a->da_end;
+
+ od = omap_device_build("omap-iommu", i, oh, &pdata, sizeof(pdata),
+ iommu_latencies, ARRAY_SIZE(iommu_latencies), 0);
+ if (IS_ERR(od)) {
+ pr_err("%s: device build error: %ld\n", __func__, PTR_ERR(od));
+ return PTR_ERR(od);
+ }
- res[0].start = d->base;
- res[0].end = d->base + MMU_REG_SIZE - 1;
- res[1].start = res[1].end = d->irq;
+ i++;
- err = platform_device_add_resources(pdev, res,
- ARRAY_SIZE(res));
- if (err)
- goto err_out;
- err = platform_device_add_data(pdev, &d->pdata,
- sizeof(d->pdata));
- if (err)
- goto err_out;
- err = platform_device_add(pdev);
- if (err)
- goto err_out;
- omap_iommu_pdev[i] = pdev;
- }
return 0;
+}
-err_out:
- while (i--)
- platform_device_put(omap_iommu_pdev[i]);
- return err;
+static int __init omap_iommu_init(void)
+{
+ return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL);
}
module_init(omap_iommu_init);
static void __exit omap_iommu_exit(void)
{
- int i;
-
- for (i = 0; i < num_iommu_devices; i++)
- platform_device_unregister(omap_iommu_pdev[i]);
+ /* Do nothing */
}
module_exit(omap_iommu_exit);
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index b0d43ce..60f7c77 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -115,7 +115,7 @@ struct omap_mmu_dev_attr {
struct iommu_platform_data {
const char *name;
const char *clk_name;
- const int nr_tlb_entries;
+ int nr_tlb_entries;
u32 da_start;
u32 da_end;
};
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 4/4] OMAP3/4: iommu: adapt to runtime pm
2011-03-07 7:53 [PATCH v2 0/4] OMAP: iommu: hwmod support and runtime PM Omar Ramirez Luna
` (2 preceding siblings ...)
2011-03-07 7:53 ` [PATCH v2 3/4] OMAP3/4: iommu: migrate to hwmod framework Omar Ramirez Luna
@ 2011-03-07 7:53 ` Omar Ramirez Luna
3 siblings, 0 replies; 9+ messages in thread
From: Omar Ramirez Luna @ 2011-03-07 7:53 UTC (permalink / raw)
To: linux-arm-kernel
Use runtime PM functionality interfaced with hwmod enable/idle
functions, to replace direct clock operations, reset and sysconfig
handling.
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
arch/arm/mach-omap2/iommu2.c | 17 ----------
arch/arm/mach-omap2/omap-iommu.c | 1 -
arch/arm/plat-omap/include/plat/iommu.h | 2 -
arch/arm/plat-omap/include/plat/iommu2.h | 2 -
arch/arm/plat-omap/iommu.c | 50 ++++++++++++++----------------
5 files changed, 23 insertions(+), 49 deletions(-)
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index a22d812..89821d7 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -25,15 +25,6 @@
*/
#define IOMMU_ARCH_VERSION 0x00000011
-/* SYSCONF */
-#define MMU_SYS_IDLE_SHIFT 3
-#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
-#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
-#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
-#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
-
-#define MMU_SYS_AUTOIDLE 1
-
/* IRQSTATUS & IRQENABLE */
#define MMU_IRQ_MULTIHITFAULT (1 << 4)
#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
@@ -96,11 +87,6 @@ static int omap2_iommu_enable(struct iommu *obj)
dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
(l >> 4) & 0xf, l & 0xf);
- l = iommu_read_reg(obj, MMU_SYSCONFIG);
- l &= ~MMU_SYS_IDLE_MASK;
- l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
- iommu_write_reg(obj, l, MMU_SYSCONFIG);
-
iommu_write_reg(obj, pa, MMU_TTB);
__iommu_set_twl(obj, true);
@@ -114,7 +100,6 @@ static void omap2_iommu_disable(struct iommu *obj)
l &= ~MMU_CNTL_MASK;
iommu_write_reg(obj, l, MMU_CNTL);
- iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
}
@@ -240,8 +225,6 @@ static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len)
char *p = buf;
pr_reg(REVISION);
- pr_reg(SYSCONFIG);
- pr_reg(SYSSTATUS);
pr_reg(IRQSTATUS);
pr_reg(IRQENABLE);
pr_reg(WALKING_ST);
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 564a078..37a000c 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -33,7 +33,6 @@ static int omap_iommu_dev_init(struct omap_hwmod *oh, void *unused)
static int i;
pdata.name = oh->name;
- pdata.clk_name = oh->main_clk;
pdata.nr_tlb_entries = a->nr_tlb_entries;
pdata.da_start = a->da_start;
pdata.da_end = a->da_end;
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 60f7c77..1ee01a9 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -28,7 +28,6 @@ struct iotlb_entry {
struct iommu {
const char *name;
struct module *owner;
- struct clk *clk;
void __iomem *regbase;
struct device *dev;
void *isr_priv;
@@ -114,7 +113,6 @@ struct omap_mmu_dev_attr {
struct iommu_platform_data {
const char *name;
- const char *clk_name;
int nr_tlb_entries;
u32 da_start;
u32 da_end;
diff --git a/arch/arm/plat-omap/include/plat/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h
index 10ad05f..0cd475e 100644
--- a/arch/arm/plat-omap/include/plat/iommu2.h
+++ b/arch/arm/plat-omap/include/plat/iommu2.h
@@ -19,8 +19,6 @@
* MMU Register offsets
*/
#define MMU_REVISION 0x00
-#define MMU_SYSCONFIG 0x10
-#define MMU_SYSSTATUS 0x14
#define MMU_IRQSTATUS 0x18
#define MMU_IRQENABLE 0x1c
#define MMU_WALKING_ST 0x40
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index e3eb038..510b5bb 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -16,8 +16,8 @@
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
-#include <linux/clk.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <asm/cacheflush.h>
@@ -107,11 +107,13 @@ static int iommu_enable(struct iommu *obj)
if (!arch_iommu)
return -ENODEV;
- clk_enable(obj->clk);
+ pm_runtime_enable(obj->dev);
+ pm_runtime_get_sync(obj->dev);
err = arch_iommu->enable(obj);
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
+
return err;
}
@@ -120,11 +122,12 @@ static void iommu_disable(struct iommu *obj)
if (!obj)
return;
- clk_enable(obj->clk);
+ pm_runtime_get_sync(obj->dev);
arch_iommu->disable(obj);
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
+ pm_runtime_disable(obj->dev);
}
/*
@@ -247,7 +250,7 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
if (!obj || !obj->nr_tlb_entries || !e)
return -EINVAL;
- clk_enable(obj->clk);
+ pm_runtime_get_sync(obj->dev);
iotlb_lock_get(obj, &l);
if (l.base == obj->nr_tlb_entries) {
@@ -277,7 +280,7 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
cr = iotlb_alloc_cr(obj, e);
if (IS_ERR(cr)) {
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
return PTR_ERR(cr);
}
@@ -291,7 +294,7 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
l.vict = l.base;
iotlb_lock_set(obj, &l);
out:
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
return err;
}
EXPORT_SYMBOL_GPL(load_iotlb_entry);
@@ -308,7 +311,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
int i;
struct cr_regs cr;
- clk_enable(obj->clk);
+ pm_runtime_get_sync(obj->dev);
for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
u32 start;
@@ -327,7 +330,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
}
}
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
if (i == obj->nr_tlb_entries)
dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
@@ -362,7 +365,7 @@ void flush_iotlb_all(struct iommu *obj)
{
struct iotlb_lock l;
- clk_enable(obj->clk);
+ pm_runtime_get_sync(obj->dev);
l.base = 0;
l.vict = 0;
@@ -370,7 +373,7 @@ void flush_iotlb_all(struct iommu *obj)
iommu_write_reg(obj, 1, MMU_GFLUSH);
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
}
EXPORT_SYMBOL_GPL(flush_iotlb_all);
@@ -385,9 +388,9 @@ EXPORT_SYMBOL_GPL(flush_iotlb_all);
*/
void iommu_set_twl(struct iommu *obj, bool on)
{
- clk_enable(obj->clk);
+ pm_runtime_get_sync(obj->dev);
arch_iommu->set_twl(obj, on);
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
}
EXPORT_SYMBOL_GPL(iommu_set_twl);
@@ -398,11 +401,11 @@ ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
if (!obj || !buf)
return -EINVAL;
- clk_enable(obj->clk);
+ pm_runtime_get_sync(obj->dev);
bytes = arch_iommu->dump_ctx(obj, buf, bytes);
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
return bytes;
}
@@ -415,7 +418,7 @@ static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num)
struct cr_regs tmp;
struct cr_regs *p = crs;
- clk_enable(obj->clk);
+ pm_runtime_get_sync(obj->dev);
iotlb_lock_get(obj, &saved);
for_each_iotlb_cr(obj, num, i, tmp) {
@@ -425,7 +428,7 @@ static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num)
}
iotlb_lock_set(obj, &saved);
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
return p - crs;
}
@@ -790,9 +793,9 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
if (!obj->refcount)
return IRQ_NONE;
- clk_enable(obj->clk);
+ pm_runtime_get_sync(obj->dev);
errs = iommu_report_fault(obj, &da);
- clk_disable(obj->clk);
+ pm_runtime_put_sync(obj->dev);
/* Fault callback or TLB/PTE Dynamic loading */
if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv))
@@ -961,10 +964,6 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
if (!obj)
return -ENOMEM;
- obj->clk = clk_get(&pdev->dev, pdata->clk_name);
- if (IS_ERR(obj->clk))
- goto err_clk;
-
obj->nr_tlb_entries = pdata->nr_tlb_entries;
obj->name = pdata->name;
obj->dev = &pdev->dev;
@@ -1026,8 +1025,6 @@ err_irq:
release_mem_region(res->start, resource_size(res));
iounmap(obj->regbase);
err_mem:
- clk_put(obj->clk);
-err_clk:
kfree(obj);
return err;
}
@@ -1049,7 +1046,6 @@ static int __devexit omap_iommu_remove(struct platform_device *pdev)
release_mem_region(res->start, resource_size(res));
iounmap(obj->regbase);
- clk_put(obj->clk);
dev_info(&pdev->dev, "%s removed\n", obj->name);
kfree(obj);
return 0;
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread