* [PATCH V6 01/10] ST SPEAr13xx: Adding machine specific header files
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
@ 2011-03-01 11:27 ` Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 02/10] ST SPEAr13xx: Adding machine specific src files Viresh Kumar
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/clkdev.h | 19 +
arch/arm/mach-spear13xx/include/mach/debug-macro.S | 14 +
arch/arm/mach-spear13xx/include/mach/entry-macro.S | 22 ++
arch/arm/mach-spear13xx/include/mach/generic.h | 50 +++
arch/arm/mach-spear13xx/include/mach/gpio.h | 19 +
arch/arm/mach-spear13xx/include/mach/hardware.h | 31 ++
arch/arm/mach-spear13xx/include/mach/io.h | 19 +
arch/arm/mach-spear13xx/include/mach/irqs.h | 91 +++++
arch/arm/mach-spear13xx/include/mach/memory.h | 19 +
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 386 ++++++++++++++++++++
arch/arm/mach-spear13xx/include/mach/smp.h | 25 ++
arch/arm/mach-spear13xx/include/mach/spear.h | 94 +++++
arch/arm/mach-spear13xx/include/mach/spear1300.h | 21 +
arch/arm/mach-spear13xx/include/mach/system.h | 35 ++
arch/arm/mach-spear13xx/include/mach/timex.h | 19 +
arch/arm/mach-spear13xx/include/mach/uncompress.h | 19 +
arch/arm/mach-spear13xx/include/mach/vmalloc.h | 18 +
17 files changed, 901 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/io.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/memory.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/smp.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1300.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/vmalloc.h
diff --git a/arch/arm/mach-spear13xx/include/mach/clkdev.h b/arch/arm/mach-spear13xx/include/mach/clkdev.h
new file mode 100644
index 0000000..effdb81
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/clkdev.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/clkdev.h
+ *
+ * Clock Dev framework definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+#include <plat/clkdev.h>
+
+#endif /* __MACH_CLKDEV_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
new file mode 100644
index 0000000..3933edc
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header spear13xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/entry-macro.S b/arch/arm/mach-spear13xx/include/mach/entry-macro.S
new file mode 100644
index 0000000..5257929
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/entry-macro.S
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * Copy of RealView platform implementation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/hardware/entry-macro-gic.S>
+#include <mach/hardware.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
new file mode 100644
index 0000000..95011a2
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/generic.h
+ *
+ * spear13xx machine family generic header file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GENERIC_H
+#define __MACH_GENERIC_H
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+/*
+ * Each GPT has 2 timer channels
+ * Following GPT channels will be used as clock source and clockevent
+ */
+#define SPEAR_GPT0_BASE SPEAR13XX_GPT0_BASE
+#define SPEAR_GPT0_CHAN0_IRQ IRQ_GPT0_TMR0
+#define SPEAR_GPT0_CHAN1_IRQ IRQ_GPT0_TMR1
+
+/* Add spear13xx family device structure declarations here */
+extern struct amba_device spear13xx_uart_device;
+extern struct sys_timer spear13xx_timer;
+
+/* Add spear13xx family function declarations here */
+void __init clk_init(void);
+void __init spear_setup_timer(void);
+void __init spear13xx_map_io(void);
+void __init spear13xx_init_irq(void);
+void __init spear13xx_init(void);
+void spear13xx_secondary_startup(void);
+
+/* spear1300 declarations */
+#ifdef CONFIG_MACH_SPEAR1300
+/* Add spear1300 machine function declarations here */
+void __init spear1300_init(void);
+
+#endif /* CONFIG_MACH_SPEAR1300 */
+
+#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
new file mode 100644
index 0000000..43fa541
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/gpio.h
+ *
+ * GPIO macros for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
new file mode 100644
index 0000000..fd8c2dc
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/hardware.h
+ *
+ * Hardware definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+#include <plat/hardware.h>
+#include <mach/spear.h>
+
+/* Vitual to physical translation of statically mapped space */
+/*
+ * if phy_addr is 0x8...,.... and above then map it to 0xF...,....
+ * else map it to 0xE...,....
+ */
+
+#define IO_ADDRESS(x) ((x) | ((((x) >> 31) << 28) | 0xE0000000))
+
+/* typesafe io address */
+#define __io_address(n) __io(IO_ADDRESS(n))
+
+#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/io.h b/arch/arm/mach-spear13xx/include/mach/io.h
new file mode 100644
index 0000000..2fe3503
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/io.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/io.h
+ *
+ * IO definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#include <plat/io.h>
+
+#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
new file mode 100644
index 0000000..d9fe051
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/irqs.h
+ *
+ * IRQ helper macros for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+/* IRQ definitions */
+/*
+ * SGI : ID0 - ID15
+ * PPI : ID16 - ID31
+ * SHPI : ID32 - ID224
+ */
+
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
+
+/* Shared Peripheral Interrupt (SHPI) */
+#define IRQ_SHPI_START 32
+
+#define IRQ_PLAY_I2S2 (IRQ_SHPI_START + 10)
+#define IRQ_REC_I2S2 (IRQ_SHPI_START + 11)
+#define IRQ_ADC (IRQ_SHPI_START + 12)
+#define IRQ_CLCD (IRQ_SHPI_START + 13)
+#define IRQ_DMAC0_FLAG_0 (IRQ_SHPI_START + 14)
+#define IRQ_DMAC0_FLAG_1 (IRQ_SHPI_START + 15)
+#define IRQ_DMAC0_FLAG_2 (IRQ_SHPI_START + 16)
+#define IRQ_DMAC0_FLAG_3 (IRQ_SHPI_START + 17)
+#define IRQ_DMAC0_FLAG_4 (IRQ_SHPI_START + 18)
+#define IRQ_DMAC0_COMBINED (IRQ_SHPI_START + 19)
+#define IRQ_FSMC0 (IRQ_SHPI_START + 20)
+#define IRQ_FSMC1 (IRQ_SHPI_START + 21)
+#define IRQ_FSMC2 (IRQ_SHPI_START + 22)
+#define IRQ_FSMC3 (IRQ_SHPI_START + 23)
+#define IRQ_GPIO0 (IRQ_SHPI_START + 24)
+#define IRQ_GPIO1 (IRQ_SHPI_START + 25)
+#define IRQ_PLAY_I2S1 (IRQ_SHPI_START + 26)
+#define IRQ_JPEG (IRQ_SHPI_START + 27)
+#define IRQ_SDHCI (IRQ_SHPI_START + 28)
+#define IRQ_CF (IRQ_SHPI_START + 29)
+#define IRQ_SMI (IRQ_SHPI_START + 30)
+#define IRQ_SSP (IRQ_SHPI_START + 31)
+#define IRQ_C3 (IRQ_SHPI_START + 32)
+#define IRQ_GMAC_1 (IRQ_SHPI_START + 33)
+#define IRQ_GMAC_2 (IRQ_SHPI_START + 34)
+#define IRQ_UART (IRQ_SHPI_START + 35)
+#define IRQ_RTC (IRQ_SHPI_START + 36)
+#define IRQ_GPT0_TMR0 (IRQ_SHPI_START + 37)
+#define IRQ_GPT0_TMR1 (IRQ_SHPI_START + 38)
+#define IRQ_GPT1_TMR0 (IRQ_SHPI_START + 39)
+#define IRQ_GPT1_TMR1 (IRQ_SHPI_START + 40)
+#define IRQ_I2C (IRQ_SHPI_START + 41)
+#define IRQ_GPT2_TMR0 (IRQ_SHPI_START + 42)
+#define IRQ_GPT2_TMR1 (IRQ_SHPI_START + 43)
+#define IRQ_GPT3_TMR0 (IRQ_SHPI_START + 44)
+#define IRQ_GPT3_TMR1 (IRQ_SHPI_START + 45)
+
+#define IRQ_JPEG_RME (IRQ_SHPI_START + 52)
+#define IRQ_KBD (IRQ_SHPI_START + 52)
+#define IRQ_REC_I2S1 (IRQ_SHPI_START + 53)
+#define IRQ_DMAC1_FLAG_0 (IRQ_SHPI_START + 54)
+#define IRQ_DMAC1_FLAG_1 (IRQ_SHPI_START + 55)
+#define IRQ_DMAC1_FLAG_2 (IRQ_SHPI_START + 56)
+#define IRQ_DMAC1_FLAG_3 (IRQ_SHPI_START + 57)
+#define IRQ_DMAC1_FLAG_4 (IRQ_SHPI_START + 58)
+#define IRQ_DMAC1_COMBINED (IRQ_SHPI_START + 59)
+
+#define IRQ_UDC (IRQ_SHPI_START + 62)
+#define IRQ_UPD (IRQ_SHPI_START + 63)
+#define IRQ_USBH_EHCI0 (IRQ_SHPI_START + 64)
+#define IRQ_USBH_OHCI0 (IRQ_SHPI_START + 65)
+#define IRQ_USBH_EHCI1 (IRQ_SHPI_START + 66)
+#define IRQ_USBH_OHCI1 (IRQ_SHPI_START + 67)
+#define IRQ_PCIE0 (IRQ_SHPI_START + 68)
+#define IRQ_PCIE1 (IRQ_SHPI_START + 69)
+#define IRQ_PCIE2 (IRQ_SHPI_START + 70)
+
+#define IRQ_GIC_END (IRQ_SHPI_START + 128)
+
+#define NR_IRQS IRQ_GIC_END
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/memory.h b/arch/arm/mach-spear13xx/include/mach/memory.h
new file mode 100644
index 0000000..200257c
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/memory.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/memory.h
+ *
+ * Memory map for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+#include <plat/memory.h>
+
+#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/misc_regs.h b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
new file mode 100644
index 0000000..98faae1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
@@ -0,0 +1,386 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/misc_regs.h
+ *
+ * Miscellaneous registers definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MISC_REGS_H
+#define __MACH_MISC_REGS_H
+
+#include <mach/hardware.h>
+
+#define MISC_BASE IOMEM(VA_SPEAR13XX_MISC_BASE)
+
+/* General Configuration */
+#define SOC_CFG (MISC_BASE + 0x000)
+#define BOOTSTRAP_CFG (MISC_BASE + 0x004)
+
+/* Power Management Registers */
+#define PCM_CFG (MISC_BASE + 0x100)
+#define PCM_WKUP_CFG (MISC_BASE + 0x104)
+#define SWITCH_CTR (MISC_BASE + 0x108)
+#define SYS_CLK_CTRL (MISC_BASE + 0x200)
+#define SYS_SW_RES (MISC_BASE + 0x204)
+
+/* Clock Configuration Registers */
+#define SYS_CLK_PLLTIMER (MISC_BASE + 0x208)
+#define SYS_CLK_OSCITIMER (MISC_BASE + 0x20c)
+
+/* PLL related registers and bit values */
+#define PLL_CFG (MISC_BASE + 0x210)
+ /* PLL_CFG bit values */
+ #define OSC_24M_VAL 0
+ #define OSC_25M_VAL 1
+ #define PLL_CLK_MASK 3
+ #define PLL1_CLK_SHIFT 20
+ #define PLL2_CLK_SHIFT 22
+ #define PLL3_CLK_SHIFT 24
+ #define CLCD_SYNT_PLL1_DIV4_VAL 0
+ #define CLCD_SYNT_PLL2_VAL 1
+ #define CLCD_SYNT_CLK_MASK 1
+ #define CLCD_SYNT_CLK_SHIFT 31
+
+#define PLL1_CTR (MISC_BASE + 0x214)
+#define PLL1_FRQ (MISC_BASE + 0x218)
+#define PLL1_MOD (MISC_BASE + 0x21c)
+#define PLL2_CTR (MISC_BASE + 0x220)
+#define PLL2_FRQ (MISC_BASE + 0x224)
+#define PLL2_MOD (MISC_BASE + 0x228)
+#define PLL3_CTR (MISC_BASE + 0x22c)
+#define PLL3_FRQ (MISC_BASE + 0x230)
+#define PLL3_MOD (MISC_BASE + 0x234)
+#define PLL4_CTR (MISC_BASE + 0x238)
+ /* PLL_CTR register masks */
+ #define PLL_ENABLE 2
+ #define PLL_MODE_SHIFT 4
+ #define PLL_MODE_MASK 3
+ #define PLL_MODE_NORMAL 0
+ #define PLL_MODE_FRACTION 1
+ #define PLL_MODE_DITH_DSB 2
+ #define PLL_MODE_DITH_SSB 3
+
+#define PLL4_FRQ (MISC_BASE + 0x23c)
+ /* PLL FRQ register masks */
+ #define PLL_DIV_N_SHIFT 0
+ #define PLL_DIV_N_MASK 0xFF
+ #define PLL_DIV_P_SHIFT 8
+ #define PLL_DIV_P_MASK 0x7
+ #define PLL_NORM_FDBK_M_SHIFT 24
+ #define PLL_NORM_FDBK_M_MASK 0xFF
+ #define PLL_DITH_FDBK_M_SHIFT 16
+ #define PLL_DITH_FDBK_M_MASK 0xFFFF
+
+#define PLL4_MOD (MISC_BASE + 0x240)
+
+#define PERIP_CLK_CFG (MISC_BASE + 0x244)
+ /* PERIP_CLK_CFG bit values */
+ #define GPT_OSC24_VAL 0
+ #define GPT_APB_VAL 1
+ #define GPT_CLK_MASK 1
+ #define GPT0_CLK_SHIFT 8
+ #define GPT1_CLK_SHIFT 9
+ #define GPT2_CLK_SHIFT 12
+ #define GPT3_CLK_SHIFT 13
+ #define AUX_CLK_PLL5_VAL 0
+ #define AUX_CLK_SYNT_VAL 1
+ #define UART_CLK_MASK 1
+ #define UART_CLK_SHIFT 4
+ #define CLCD_PLL5_VAL 0
+ #define CLCD_SYNT_MASK 1
+ #define CLCD_CLK_MASK 3
+ #define CLCD_CLK_SHIFT 2
+ #define C3_CLK_MASK 1
+ #define C3_CLK_SHIFT 1
+ #define MCTR_CLK_SHIFT 10
+ #define MCTR_CLK_MASK 0x1
+ #define MCTR_CLK_PLL1_VAL 0x0
+ #define MCTR_CLK_PLL4_VAL 0x1
+
+#define GMAC_CLK_CFG (MISC_BASE + 0x248)
+
+ #define GMAC_PHY_PAD_VAL 0
+ #define GMAC_PHY_PLL2_VAL 1
+ #define GMAC_PHY_OSC3_VAL 2
+ #define GMAC_PHY_INPUT_CLK_MASK 3
+ #define GMAC_PHY_INPUT_CLK_SHIFT 1
+ #define GMAC_PHY_SYNT_ENB 3
+ #define GMAC_PHY_CLK_MASK 1
+ #define GMAC_PHY_CLK_SHIFT 3
+ #define GMAC_PHY_SYNT_ENB_VAL 4
+
+#define C3_CLK_SYNT (MISC_BASE + 0x24c)
+#define CLCD_CLK_SYNT (MISC_BASE + 0x250)
+ /* CLCD synth reg masks */
+ #define CLCD_SYNT_ENB 31
+ #define CLCD_SYNT_DIV_FACTOR_MASK 0x1ffff
+ #define CLCD_SYNT_DIV_FACTOR_SHIFT 0
+
+#define UART_CLK_SYNT (MISC_BASE + 0x254)
+#define GMAC_CLK_SYNT (MISC_BASE + 0x258)
+#define SDHCI_CLK_SYNT (MISC_BASE + 0x25c)
+#define CFXD_CLK_SYNT (MISC_BASE + 0x260)
+#define RAS_CLK_SYNT0 (MISC_BASE + 0x264)
+#define RAS_CLK_SYNT1 (MISC_BASE + 0x268)
+#define RAS_CLK_SYNT2 (MISC_BASE + 0x26c)
+#define RAS_CLK_SYNT3 (MISC_BASE + 0x270)
+ /* aux clk synthesizer register masks */
+ #define AUX_SYNT_ENB 31
+ #define AUX_EQ_SEL_SHIFT 30
+ #define AUX_EQ_SEL_MASK 1
+ #define AUX_EQ1_SEL 0
+ #define AUX_EQ2_SEL 1
+ #define AUX_XSCALE_SHIFT 16
+ #define AUX_XSCALE_MASK 0xFFF
+ #define AUX_YSCALE_SHIFT 0
+ #define AUX_YSCALE_MASK 0xFFF
+
+#define PERIP1_CLK_ENB (MISC_BASE + 0x274)
+ /* PERIP1_CLK_ENB register masks */
+ #define BUS_CLK_ENB 0
+ #define SYSROM_CLK_ENB 1
+ #define SYSRAM1_CLK_ENB 2
+ #define SYSRAM0_CLK_ENB 3
+ #define FSMC_CLK_ENB 4
+ #define SMI_CLK_ENB 5
+ #define SDHCI_CLK_ENB 6
+ #define CFXD_CLK_ENB 7
+ #define GMAC_CLK_ENB 8
+ #define UHC0_CLK_ENB 9
+ #define UHC1_CLK_ENB 10
+ #define USBD_CLK_ENB 11
+ #define PCIE0_CLK_ENB 12
+ #define PCIE1_CLK_ENB 13
+ #define PCIE2_CLK_ENB 14
+ #define UART_CLK_ENB 15
+ #define SSP_CLK_ENB 17
+ #define I2C_CLK_ENB 18
+ #define I2S0_CLK_ENB 19
+ #define I2S1_CLK_ENB 20
+ #define GPT0_CLK_ENB 21
+ #define GPT1_CLK_ENB 22
+ #define GPIO0_CLK_ENB 23
+ #define GPIO1_CLK_ENB 24
+ #define DMA0_CLK_ENB 25
+ #define DMA1_CLK_ENB 26
+ #define CLCD_CLK_ENB 27
+ #define JPEG_CLK_ENB 28
+ #define C3_CLK_ENB 29
+ #define ADC_CLK_ENB 30
+ #define RTC_CLK_ENB 31
+
+#define PERIP2_CLK_ENB (MISC_BASE + 0x278)
+ /* PERIP2_CLK_ENB register masks */
+ #define DDR_CTRL_CLK_ENB 0
+ #define DDR_CORE_CLK_ENB 1
+ #define CPU_DBG_CLK_ENB 2
+ #define KBD_CLK_ENB 3
+ #define GPT2_CLK_ENB 4
+ #define GPT3_CLK_ENB 5
+ #define ACP_CLK_ENB 6
+ #define I2S_REFOUT_CLK_ENB 7
+ #define THSENS_CLK_ENB 8
+
+#define PERIP1_SW_RST (MISC_BASE + 0x27c)
+ #define JPEG_SOF_RST 28
+#define PERIP2_SW_RST (MISC_BASE + 0x280)
+#define RAS_CLK_ENB (MISC_BASE + 0x284)
+ /* RAS_CLK_ENB register masks */
+ #define ACLK_CLK_ENB 0
+ #define PCLK_CLK_ENB 1
+ #define OSC1_CLK_ENB 2
+ #define OSC2_CLK_ENB 3
+ #define OSC3_CLK_ENB 4
+ #define C48_CLK_ENB 5
+ #define C30_CLK_ENB 6
+ #define C125_CLK_ENB 7
+ #define PLL2_CLK_ENB 8
+ #define PLL3_CLK_ENB 9
+ #define PCLK0_CLK_ENB 10
+ #define PCLK1_CLK_ENB 11
+ #define PCLK2_CLK_ENB 12
+ #define PCLK3_CLK_ENB 13
+ #define SYN0_CLK_ENB 14
+ #define SYN1_CLK_ENB 15
+ #define SYN2_CLK_ENB 16
+ #define SYN3_CLK_ENB 17
+#define RAS_SW_RST (MISC_BASE + 0x288)
+#define PLL1_SYNT (MISC_BASE + 0x28c)
+#define I2S_CLK_CFG (MISC_BASE + 0x290)
+
+/* Peripheral Configuration Registers */
+#define DMAC_HS_SEL (MISC_BASE + 0x300)
+#define DMAC_SEL (MISC_BASE + 0x304)
+#define DMAC_FLOW_SEL (MISC_BASE + 0x308)
+#define DMAC_DIR_SEL (MISC_BASE + 0x30c)
+#define DMAC_CFG (MISC_BASE + 0x310)
+#define USBPHY_GEN_CFG (MISC_BASE + 0x314)
+#define USBPHY_P1_CFG (MISC_BASE + 0x318)
+#define USBPHY_P2_CFG (MISC_BASE + 0x31c)
+#define USBPHY_P3_CFG (MISC_BASE + 0x320)
+#define PCIE_CFG (MISC_BASE + 0x324)
+ /* PCIE CFG MASks */
+ #define PCIE2_CFG_AUX_CLK (1 << 0)
+ #define PCIE1_CFG_AUX_CLK (1 << 1)
+ #define PCIE0_CFG_AUX_CLK (1 << 2)
+ #define PCIE2_CFG_CORE_CLK (1 << 3)
+ #define PCIE1_CFG_CORE_CLK (1 << 4)
+ #define PCIE0_CFG_CORE_CLK (1 << 5)
+ #define PCIE2_CFG_POWERUP_RESET (1 << 6)
+ #define PCIE1_CFG_POWERUP_RESET (1 << 7)
+ #define PCIE0_CFG_POWERUP_RESET (1 << 8)
+ #define PCIE2_CFG_DEVICE_PRESENT (1 << 9)
+ #define PCIE1_CFG_DEVICE_PRESENT (1 << 10)
+ #define PCIE0_CFG_DEVICE_PRESENT (1 << 11)
+ #define PCIE0_CFG_VAL (PCIE0_CFG_AUX_CLK | PCIE0_CFG_CORE_CLK \
+ | PCIE0_CFG_POWERUP_RESET | PCIE0_CFG_DEVICE_PRESENT)
+ #define PCIE1_CFG_VAL (PCIE1_CFG_AUX_CLK | PCIE1_CFG_CORE_CLK \
+ | PCIE1_CFG_POWERUP_RESET | PCIE1_CFG_DEVICE_PRESENT)
+ #define PCIE2_CFG_VAL (PCIE2_CFG_AUX_CLK | PCIE2_CFG_CORE_CLK \
+ | PCIE2_CFG_POWERUP_RESET | PCIE2_CFG_DEVICE_PRESENT)
+
+#define PCIE_MIPHY_CFG (MISC_BASE + 0x328)
+#define PERIP_CFG (MISC_BASE + 0x32c)
+ #define MCIF_SEL_SHIFT 3
+ #define MCIF_SEL_MASK 0x3
+ #define SD_MMC_ACTIVE 0x1
+ #define CF_MMC_ACTIVE 0x2
+ #define XD_MMC_ACTIVE 0x3
+#define FSMC_CFG (MISC_BASE + 0x330)
+ /* FSMC_CFG register masks */
+ #define FSMC_MEMSEL_MASK 0x3
+ #define FSMC_MEMSEL_SHIFT 0
+ #define FSMC_MEM_NOR 0
+ #define FSMC_MEM_NAND 1
+ #define FSMC_MEM_SRAM 2
+ #define NAND_BANK_MASK 0x3
+ #define NAND_BANK_SHIFT 2
+ #define NAND_DEV_WIDTH16 4
+
+#define MPMC_CTR_STS (MISC_BASE + 0x334)
+
+/* Inter-Processor Communication Registers */
+#define PRC1_LOCK_CTR (MISC_BASE + 0x500)
+#define PRC2_LOCK_CTR (MISC_BASE + 0x504)
+#define PRC1_IRQ_CTR (MISC_BASE + 0x508)
+#define PRC2_IRQ_CTR (MISC_BASE + 0x51C)
+
+/* Pad Configuration Registers */
+#define PAD_PU_CFG_1 (MISC_BASE + 0x600)
+#define PAD_PU_CFG_2 (MISC_BASE + 0x604)
+#define PAD_PU_CFG_3 (MISC_BASE + 0x608)
+#define PAD_PU_CFG_4 (MISC_BASE + 0x60c)
+#define PAD_PU_CFG_5 (MISC_BASE + 0x610)
+#define PAD_PU_CFG_6 (MISC_BASE + 0x614)
+#define PAD_PU_CFG_7 (MISC_BASE + 0x618)
+#define PAD_PU_CFG_8 (MISC_BASE + 0x61c)
+#define PAD_PD_CFG_1 (MISC_BASE + 0x620)
+#define PAD_PD_CFG_2 (MISC_BASE + 0x624)
+#define PAD_PD_CFG_3 (MISC_BASE + 0x628)
+#define PAD_PD_CFG_4 (MISC_BASE + 0x62c)
+#define PAD_PD_CFG_5 (MISC_BASE + 0x630)
+#define PAD_PD_CFG_6 (MISC_BASE + 0x634)
+#define PAD_PD_CFG_7 (MISC_BASE + 0x638)
+#define PAD_PD_CFG_8 (MISC_BASE + 0x63c)
+#define PAD_SLEEP_CFG (MISC_BASE + 0x640)
+#define PAD_HYST_CFG (MISC_BASE + 0x644)
+#define PAD_DRV_CFG (MISC_BASE + 0x648)
+#define PAD_SLEW_CFG (MISC_BASE + 0x64c)
+#define PAD_FUNCTION_EN_1 (MISC_BASE + 0x650)
+#define PAD_FUNCTION_EN_2 (MISC_BASE + 0x654)
+#define PAD_FUNCTION_EN_3 (MISC_BASE + 0x658)
+#define DDR_PAD_CFG (MISC_BASE + 0x65c)
+#define THSENS_CFG (MISC_BASE + 0x6c4)
+
+/* Compensation Configuration Registers */
+#define COMP_1V8_2V5_3V3__1_CFG (MISC_BASE + 0x700)
+#define COMP_1V8_2V5_3V3__2_CFG (MISC_BASE + 0x704)
+#define COMP_3V3_1_CFG (MISC_BASE + 0x708)
+#define COMP_3V3_2_CFG (MISC_BASE + 0x70c)
+#define COMP_DDR_CFG (MISC_BASE + 0x710)
+
+/* OTP Programming Registers */
+#define OTP_PROG_CTR (MISC_BASE + 0x800)
+#define OTP_WDATA1_1 (MISC_BASE + 0x804)
+#define OTP_WDATA1_2 (MISC_BASE + 0x808)
+#define OTP_WDATA1_3 (MISC_BASE + 0x80c)
+#define OTP_WDATA1_4 (MISC_BASE + 0x810)
+#define OTP_WDATA1_5 (MISC_BASE + 0x814)
+#define OTP_WDATA1_6 (MISC_BASE + 0x818)
+#define OTP_WDATA1_7 (MISC_BASE + 0x81c)
+#define OTP_WDATA1_8 (MISC_BASE + 0x820)
+#define OTP_WDATA2_1 (MISC_BASE + 0x824)
+#define OTP_WDATA2_2 (MISC_BASE + 0x828)
+#define OTP_WDATA2_3 (MISC_BASE + 0x82c)
+#define OTP_WDATA2_4 (MISC_BASE + 0x830)
+#define OTP_WDATA2_5 (MISC_BASE + 0x834)
+#define OTP_WDATA2_6 (MISC_BASE + 0x838)
+#define OTP_WDATA2_7 (MISC_BASE + 0x83c)
+#define OTP_WDATA2_8 (MISC_BASE + 0x840)
+#define OTP_MASK_1 (MISC_BASE + 0x844)
+#define OTP_MASK_2 (MISC_BASE + 0x848)
+#define OTP_MASK_3 (MISC_BASE + 0x84c)
+#define OTP_MASK_4 (MISC_BASE + 0x850)
+#define OTP_MASK_5 (MISC_BASE + 0x854)
+#define OTP_MASK_6 (MISC_BASE + 0x858)
+#define OTP_MASK_7 (MISC_BASE + 0x85c)
+#define OTP_MASK_8 (MISC_BASE + 0x860)
+#define OTP_RDATA1_1 (MISC_BASE + 0x864)
+#define OTP_RDATA1_2 (MISC_BASE + 0x868)
+#define OTP_RDATA1_3 (MISC_BASE + 0x86c)
+#define OTP_RDATA1_4 (MISC_BASE + 0x870)
+#define OTP_RDATA1_5 (MISC_BASE + 0x874)
+#define OTP_RDATA1_6 (MISC_BASE + 0x878)
+#define OTP_RDATA1_7 (MISC_BASE + 0x87c)
+#define OTP_RDATA1_8 (MISC_BASE + 0x880)
+#define OTP_RDATA2_1 (MISC_BASE + 0x884)
+#define OTP_RDATA2_2 (MISC_BASE + 0x888)
+#define OTP_RDATA2_3 (MISC_BASE + 0x88c)
+#define OTP_RDATA2_4 (MISC_BASE + 0x890)
+#define OTP_RDATA2_5 (MISC_BASE + 0x894)
+#define OTP_RDATA2_6 (MISC_BASE + 0x898)
+#define OTP_RDATA2_7 (MISC_BASE + 0x89c)
+#define OTP_RDATA2_8 (MISC_BASE + 0x8a0)
+#define OTP_RDATAM_1 (MISC_BASE + 0x8a4)
+#define OTP_RDATAM_2 (MISC_BASE + 0x8a8)
+#define OTP_RDATAM_3 (MISC_BASE + 0x8ac)
+#define OTP_RDATAM_4 (MISC_BASE + 0x8b0)
+#define OTP_RDATAM_5 (MISC_BASE + 0x8b4)
+#define OTP_RDATAM_6 (MISC_BASE + 0x8b8)
+#define OTP_RDATAM_7 (MISC_BASE + 0x8bc)
+#define OTP_RDATAM_8 (MISC_BASE + 0x8c0)
+
+/* A9SM Registers */
+#define A9SM_CLUSTERID (MISC_BASE + 0x900)
+#define A9SM_STATUS (MISC_BASE + 0x904)
+#define A9SM_DEBUG (MISC_BASE + 0x908)
+#define A9SM_FILTER (MISC_BASE + 0x90c)
+#define A9SM_PARITY_CFG (MISC_BASE + 0x910)
+#define A9SM_PARITY_ERR (MISC_BASE + 0x914)
+
+/* SOC ID Registers */
+#define DIE_ID_1 (MISC_BASE + 0xa00)
+#define DIE_ID_2 (MISC_BASE + 0xa04)
+#define DIE_ID_3 (MISC_BASE + 0xa08)
+#define DIE_ID_4 (MISC_BASE + 0xa0c)
+#define DIE_ID_VALID (MISC_BASE + 0xa10)
+
+/* SOC TEST & DEBUG Registers */
+#define MIPHY_TEST (MISC_BASE + 0x1000)
+#define PCIE_MSTR_P0 (MISC_BASE + 0x1004)
+#define PCIE_AWMISC_P0 (MISC_BASE + 0x1008)
+#define PCIE_ARMISC_P0 (MISC_BASE + 0x100c)
+#define PCIE_MSTR_P1 (MISC_BASE + 0x1010)
+#define PCIE_AWMISC_P1 (MISC_BASE + 0x1014)
+#define PCIE_ARMISC_P1 (MISC_BASE + 0x1018)
+#define PCIE_MSTR_P2 (MISC_BASE + 0x101c)
+#define PCIE_AWMISC_P2 (MISC_BASE + 0x1020)
+#define PCIE_ARMISC_P2 (MISC_BASE + 0x1024)
+
+#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/smp.h b/arch/arm/mach-spear13xx/include/mach/smp.h
new file mode 100644
index 0000000..c1c4580
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/smp.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/smp.h
+ *
+ * Few SMP related definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+#include <asm/hardware/gic.h>
+
+/* We use IRQ1 as the IPI */
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
+{
+ gic_raise_softirq(mask, ipi);
+}
+
+#endif
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
new file mode 100644
index 0000000..1a1af72
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -0,0 +1,94 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear.h
+ *
+ * spear13xx Machine family specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR13XX_H
+#define __MACH_SPEAR13XX_H
+
+#include <asm/memory.h>
+#include <mach/spear1300.h>
+
+#define SPEAR13XX_L2CC_BASE UL(0xED000000)
+
+/* ARM9SMP peripheral base address */
+#define SPEAR13XX_A9SM_PERIP_BASE UL(0xEC800000)
+#define VA_SPEAR13XX_A9SM_PERIP_BASE IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE)
+/* A9SM peripheral offsets */
+#define SPEAR13XX_SCU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x00)
+#define SPEAR13XX_GIC_CPU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x100)
+#define SPEAR13XX_GLOBAL_TMR_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x200)
+#define SPEAR13XX_LOCAL_TMR_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x600)
+#define SPEAR13XX_WDT_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x620)
+#define SPEAR13XX_GIC_DIST_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x1000)
+
+#define SPEAR13XX_UART_BASE UL(0xE0000000)
+#define VA_SPEAR13XX_UART_BASE IO_ADDRESS(SPEAR13XX_UART_BASE)
+
+#define SPEAR13XX_ADC_BASE UL(0xE0080000)
+#define SPEAR13XX_SSP_BASE UL(0xE0100000)
+#define SPEAR13XX_I2S0_BASE UL(0xE0180000)
+#define SPEAR13XX_I2S1_BASE UL(0xE0200000)
+#define SPEAR13XX_I2C_BASE UL(0xE0280000)
+#define SPEAR13XX_KBD_BASE UL(0xE0300000)
+#define SPEAR13XX_GPT0_BASE UL(0xE0380000)
+#define SPEAR13XX_GPT1_BASE UL(0xE0400000)
+#define SPEAR13XX_GPT2_BASE UL(0xE0480000)
+#define SPEAR13XX_GPT3_BASE UL(0xE0500000)
+#define SPEAR13XX_RTC_BASE UL(0xE0580000)
+#define SPEAR13XX_GPIO0_BASE UL(0xE0600000)
+#define SPEAR13XX_GPIO1_BASE UL(0xE0680000)
+#define SPEAR13XX_MISC_BASE UL(0xE0700000)
+#define VA_SPEAR13XX_MISC_BASE IO_ADDRESS(SPEAR13XX_MISC_BASE)
+
+#define SPEAR13XX_SYSRAM0_BASE UL(0xB3800000)
+#define SPEAR13XX_SYSRAM0_SIZE 0x00800000
+
+/*
+ * The system location which is polled by secondary cpus to find the
+ * jump address
+ */
+#define SPEAR13XX_SYS_LOCATION (SPEAR13XX_SYSRAM0_BASE + 0x600)
+
+#define SPEAR13XX_SYSRAM1_BASE UL(0xE0800000)
+#define SPEAR13XX_SYSRAM1_SIZE 0x00800000
+#define SPEAR13XX_CLCD_BASE UL(0xE1000000)
+#define SPEAR13XX_C3_BASE UL(0xE1800000)
+#define SPEAR13XX_GETH_BASE UL(0xE2000000)
+#define SPEAR13XX_UPD_BASE UL(0xE2800000)
+#define SPEAR13XX_UDC_BASE UL(0xE3800000)
+#define SPEAR13XX_UHC0_OHCI_BASE UL(0xE4000000)
+#define SPEAR13XX_UHC0_EHCI_BASE UL(0xE4800000)
+#define SPEAR13XX_UHC1_OHCI_BASE UL(0xE5000000)
+#define SPEAR13XX_UHC1_EHCI_BASE UL(0xE5800000)
+#define SPEAR13XX_SMI_MEM_BASE UL(0xE6000000)
+#define SPEAR13XX_SMI_CTRL_BASE UL(0xEA000000)
+#define SPEAR13XX_DMAC0_BASE UL(0xEA800000)
+#define SPEAR13XX_DMAC1_BASE UL(0xEB000000)
+#define SPEAR13XX_MII_PHY_BASE UL(0xEB800000)
+#define SPEAR13XX_MPMC_BASE UL(0xEC000000)
+#define SPEAR13XX_PCIE0_BASE UL(0x80000000)
+#define SPEAR13XX_PCIE1_BASE UL(0x90000000)
+#define SPEAR13XX_PCIE2_BASE UL(0xC0000000)
+#define SPEAR13XX_PCIE0_APP_BASE UL(0xB1000000)
+#define SPEAR13XX_PCIE1_APP_BASE UL(0xB1800000)
+#define SPEAR13XX_PCIE2_APP_BASE UL(0xB4000000)
+#define SPEAR13XX_FSMC_MEM_BASE UL(0xA0000000)
+#define SPEAR13XX_FSMC_BASE UL(0xB0000000)
+#define SPEAR13XX_JPEG_BASE UL(0xB2000000)
+#define SPEAR13XX_MCIF_CF_BASE UL(0xB2800000)
+#define SPEAR13XX_MCIF_SDHCI_BASE UL(0xB3000000)
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE SPEAR13XX_UART_BASE
+#define VA_SPEAR_DBG_UART_BASE VA_SPEAR13XX_UART_BASE
+
+#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1300.h b/arch/arm/mach-spear13xx/include/mach/spear1300.h
new file mode 100644
index 0000000..b3ba267
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1300.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear1300.h
+ *
+ * SPEAr1300 Machine specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR1300
+
+#ifndef __MACH_SPEAR1300_H
+#define __MACH_SPEAR1300_H
+
+#endif /* __MACH_SPEAR1300_H */
+
+#endif /* CONFIG_MACH_SPEAR1300 */
diff --git a/arch/arm/mach-spear13xx/include/mach/system.h b/arch/arm/mach-spear13xx/include/mach/system.h
new file mode 100644
index 0000000..a9b159d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/system.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/system.h
+ *
+ * spear13xx Machine family specific architecture functions
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/misc_regs.h>
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+ writel(0x01, SYS_SW_RES);
+}
+
+#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
new file mode 100644
index 0000000..0a81490
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/timex.h
+ *
+ * spear13xx machine family specific timex definitions
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE 24000000
+
+#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
new file mode 100644
index 0000000..3c27f25
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <plat/uncompress.h>
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/vmalloc.h b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
new file mode 100644
index 0000000..0f243af
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/vmalloc.h
+ *
+ * Defining Vmalloc area for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#define VMALLOC_END 0xEC800000UL
+
+#endif /* __MACH_VMALLOC_H */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 02/10] ST SPEAr13xx: Adding machine specific src files
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 01/10] ST SPEAr13xx: Adding machine specific header files Viresh Kumar
@ 2011-03-01 11:27 ` Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 03/10] ST SPEAr13xx: Adding support in SPEAr generic plat/ Viresh Kumar
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/Kconfig | 21 +
arch/arm/mach-spear13xx/Makefile | 14 +
arch/arm/mach-spear13xx/Makefile.boot | 3 +
arch/arm/mach-spear13xx/clock.c | 1013 ++++++++++++++++++++++++
arch/arm/mach-spear13xx/headsmp.S | 42 +
arch/arm/mach-spear13xx/include/mach/generic.h | 2 +-
arch/arm/mach-spear13xx/localtimer.c | 25 +
arch/arm/mach-spear13xx/platsmp.c | 162 ++++
arch/arm/mach-spear13xx/spear1300.c | 23 +
arch/arm/mach-spear13xx/spear1300_evb.c | 48 ++
arch/arm/mach-spear13xx/spear13xx.c | 121 +++
11 files changed, 1473 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/Kconfig
create mode 100644 arch/arm/mach-spear13xx/Makefile
create mode 100644 arch/arm/mach-spear13xx/Makefile.boot
create mode 100644 arch/arm/mach-spear13xx/clock.c
create mode 100644 arch/arm/mach-spear13xx/headsmp.S
create mode 100644 arch/arm/mach-spear13xx/localtimer.c
create mode 100644 arch/arm/mach-spear13xx/platsmp.c
create mode 100644 arch/arm/mach-spear13xx/spear1300.c
create mode 100644 arch/arm/mach-spear13xx/spear1300_evb.c
create mode 100644 arch/arm/mach-spear13xx/spear13xx.c
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
new file mode 100644
index 0000000..3ea463d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -0,0 +1,21 @@
+#
+# SPEAr13XX Machine configuration file
+#
+
+if ARCH_SPEAR13XX
+
+menu "SPEAr13xx Implementations"
+config BOARD_SPEAR1300_EVB
+ bool "SPEAr1300 Evaluation Board"
+ select MACH_SPEAR1300
+ help
+ Supports ST SPEAr1300 Evaluation Board
+
+endmenu
+
+config MACH_SPEAR1300
+ bool "SPEAr1300"
+ help
+ Supports ST SPEAr1300 Machine
+
+endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
new file mode 100644
index 0000000..cb5ae9e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for SPEAr13XX machine series
+#
+
+# common files
+obj-y += spear13xx.o clock.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
+
+# spear1300 specific files
+obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
+
+# spear1300 boards files
+obj-$(CONFIG_BOARD_SPEAR1300_EVB) += spear1300_evb.o
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
new file mode 100644
index 0000000..7a1f3c0
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
new file mode 100644
index 0000000..58d3ec0
--- /dev/null
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -0,0 +1,1013 @@
+/*
+ * arch/arm/mach-spear13xx/clock.c
+ *
+ * SPEAr13xx machines clock framework source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * shiraz hashim<shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <asm/mach-types.h>
+#include <plat/clock.h>
+#include <mach/hardware.h>
+#include <mach/misc_regs.h>
+
+/* root clks */
+/* 24 MHz oscillator clock */
+static struct clk osc1_24m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 24000000,
+};
+
+/* 32 KHz oscillator clock */
+static struct clk osc2_32k_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 32000,
+};
+
+/* 25 MHz MIPHY oscillator clock */
+static struct clk osc3_25m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 25000000,
+};
+
+/* clock derived from 32 KHz osc clk */
+/* rtc clock */
+static struct clk rtc_clk = {
+ .pclk = &osc2_32k_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = RTC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from osc1 or osc3 */
+/* pll[1-3] parents */
+static struct pclk_info pll_pclk_info[] = {
+ {
+ .pclk = &osc1_24m_clk,
+ .pclk_val = OSC_24M_VAL,
+ }, {
+ .pclk = &osc3_25m_clk,
+ .pclk_val = OSC_25M_VAL,
+ },
+};
+
+/* pll[1-3] parent select structure */
+static struct pclk_sel pll_pclk_sel = {
+ .pclk_info = pll_pclk_info,
+ .pclk_count = ARRAY_SIZE(pll_pclk_info),
+ .pclk_sel_reg = PLL_CFG,
+ .pclk_sel_mask = PLL_CLK_MASK,
+};
+
+/* pll masks structure */
+static struct pll_clk_masks pll_masks = {
+ .mode_mask = PLL_MODE_MASK,
+ .mode_shift = PLL_MODE_SHIFT,
+ .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
+ .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
+ .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
+ .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
+ .div_p_mask = PLL_DIV_P_MASK,
+ .div_p_shift = PLL_DIV_P_SHIFT,
+ .div_n_mask = PLL_DIV_N_MASK,
+ .div_n_shift = PLL_DIV_N_SHIFT,
+};
+/* pll1 configuration structure */
+static struct pll_clk_config pll1_config = {
+ .mode_reg = PLL1_CTR,
+ .cfg_reg = PLL1_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll_rtbl[] = {
+ /* PCLK 24MHz */
+ {.mode = 0, .m = 0x7D, .n = 0x03, .p = 0x2}, /* 500 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x03, .p = 0x2}, /* 664 MHz */
+ {.mode = 0, .m = 0xC8, .n = 0x03, .p = 0x2}, /* 800 MHz */
+ {.mode = 0, .m = 0xFA, .n = 0x06, .p = 0x1}, /* 1000 MHz */
+};
+
+/* pll1 clock */
+static struct clk pll1_clk = {
+ .flags = ENABLED_ON_INIT,
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL1_CLK_SHIFT,
+ .en_reg = PLL1_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .private_data = &pll1_config,
+};
+
+/* pll1div2 clock */
+static struct clk pll1div2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* pll1div4 clock */
+static struct clk pll1div4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 4,
+ .recalc = &follow_parent,
+};
+
+/* pll2 configuration structure */
+static struct pll_clk_config pll2_config = {
+ .mode_reg = PLL2_CTR,
+ .cfg_reg = PLL2_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll2 clock */
+static struct clk pll2_clk = {
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL2_CLK_SHIFT,
+ .en_reg = PLL2_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .private_data = &pll2_config,
+};
+
+/* pll3 configuration structure */
+static struct pll_clk_config pll3_config = {
+ .mode_reg = PLL3_CTR,
+ .cfg_reg = PLL3_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll3 clock */
+static struct clk pll3_clk = {
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL3_CLK_SHIFT,
+ .en_reg = PLL3_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .private_data = &pll3_config,
+};
+
+/* pll4 (DDR) configuration structure */
+static struct pll_clk_config pll4_config = {
+ .mode_reg = PLL4_CTR,
+ .cfg_reg = PLL4_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll4 rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll4_rtbl[] = {
+ {.mode = 0, .m = 0x7D, .n = 0x03, .p = 0x2}, /* 500 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x03, .p = 0x2}, /* 664 MHz */
+ {.mode = 0, .m = 0xC8, .n = 0x03, .p = 0x2}, /* 800 MHz */
+ {.mode = 0, .m = 0xFA, .n = 0x06, .p = 0x1}, /* 1000 MHz */
+};
+
+/* pll4 (DDR) clock */
+static struct clk pll4_clk = {
+ .flags = ENABLED_ON_INIT,
+ .pclk = &osc1_24m_clk,
+ .en_reg = PLL4_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll4_rtbl, ARRAY_SIZE(pll4_rtbl), 3},
+ .private_data = &pll4_config,
+};
+
+/* pll5 USB 48 MHz clock */
+static struct clk pll5_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc1_24m_clk,
+ .rate = 48000000,
+};
+
+/* pll6 (MIPHY) clock */
+static struct clk pll6_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc3_25m_clk,
+ .rate = 25000000,
+};
+
+/* clocks derived from pll1 clk */
+/* cpu clock */
+static struct clk cpu_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* ahb clock */
+static struct clk ahb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 6,
+ .recalc = &follow_parent,
+};
+
+/* apb clock */
+static struct clk apb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 12,
+ .recalc = &follow_parent,
+};
+
+/* clocks derived from osc1, ahb or apb */
+/* gpt[0-3] parents */
+static struct pclk_info gpt_pclk_info[] = {
+ {
+ .pclk = &osc1_24m_clk,
+ .pclk_val = GPT_OSC24_VAL,
+ }, {
+ .pclk = &apb_clk,
+ .pclk_val = GPT_APB_VAL,
+ },
+};
+
+/* gpt[0-3] parent select structure */
+static struct pclk_sel gpt_pclk_sel = {
+ .pclk_info = gpt_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
+/* gpt0 timer clock */
+static struct clk gpt0_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT0_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT0_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt1 timer clock */
+static struct clk gpt1_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT1_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT1_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt2 timer clock */
+static struct clk gpt2_clk = {
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = GPT2_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT2_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt3 timer clock */
+static struct clk gpt3_clk = {
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = GPT3_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT3_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* watch dog timer clock */
+static struct clk wdt_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &cpu_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* auxiliary synthesizers masks */
+static struct aux_clk_masks aux_masks = {
+ .eq_sel_mask = AUX_EQ_SEL_MASK,
+ .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+ .eq1_mask = AUX_EQ1_SEL,
+ .eq2_mask = AUX_EQ2_SEL,
+ .xscale_sel_mask = AUX_XSCALE_MASK,
+ .xscale_sel_shift = AUX_XSCALE_SHIFT,
+ .yscale_sel_mask = AUX_YSCALE_MASK,
+ .yscale_sel_shift = AUX_YSCALE_SHIFT,
+};
+
+/* clocks derived multiple parents (pll1, pll5, synthesizers or others) */
+/* uart configurations */
+static struct aux_clk_config uart_synth_config = {
+ .synth_reg = UART_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* aux rate configuration table, in ascending order of rates */
+struct aux_rate_tbl aux_rtbl[] = {
+ /* For PLL1div2 = 500 MHz */
+ {.xscale = 2, .yscale = 21, .eq = 1}, /* 48 MHz */
+ {.xscale = 1, .yscale = 6, .eq = 1}, /* 83 MHz */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* 125 MHz */
+ {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
+};
+
+/* uart synth clock */
+static struct clk uart_synth_clk = {
+ .en_reg = UART_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+ .private_data = &uart_synth_config,
+};
+
+/* uart parents */
+static struct pclk_info uart_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &uart_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* uart parent select structure */
+static struct pclk_sel uart_pclk_sel = {
+ .pclk_info = uart_pclk_info,
+ .pclk_count = ARRAY_SIZE(uart_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = UART_CLK_MASK,
+};
+
+/* uart clock */
+static struct clk uart_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UART_CLK_ENB,
+ .pclk_sel = &uart_pclk_sel,
+ .pclk_sel_shift = UART_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* sdhci configurations */
+static struct aux_clk_config sdhci_synth_config = {
+ .synth_reg = SDHCI_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* sdhci synth clock */
+static struct clk sdhci_synth_clk = {
+ .en_reg = SDHCI_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .private_data = &sdhci_synth_config,
+};
+
+/* sdhci clock */
+static struct clk sdhci_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SDHCI_CLK_ENB,
+ .pclk = &sdhci_synth_clk,
+ .recalc = &follow_parent,
+};
+
+/* cfxd configurations */
+static struct aux_clk_config cfxd_synth_config = {
+ .synth_reg = CFXD_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* cfxd synth clock */
+static struct clk cfxd_synth_clk = {
+ .en_reg = CFXD_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .private_data = &cfxd_synth_config,
+};
+
+/* cfxd clock */
+static struct clk cfxd_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = CFXD_CLK_ENB,
+ .pclk = &cfxd_synth_clk,
+ .recalc = &follow_parent,
+};
+
+/* C3 clk configurations */
+static struct aux_clk_config c3_synth_config = {
+ .synth_reg = C3_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* c3 synth clock */
+static struct clk c3_synth_clk = {
+ .en_reg = C3_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+ .private_data = &c3_synth_config,
+};
+
+/* c3 parents */
+static struct pclk_info c3_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &c3_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* c3 parent select structure */
+static struct pclk_sel c3_pclk_sel = {
+ .pclk_info = c3_pclk_info,
+ .pclk_count = ARRAY_SIZE(c3_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = C3_CLK_MASK,
+};
+
+/* c3 clock */
+static struct clk c3_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = C3_CLK_ENB,
+ .pclk_sel = &c3_pclk_sel,
+ .pclk_sel_shift = C3_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gmac phy clk configurations */
+static struct aux_clk_config gmac_phy_synth_config = {
+ .synth_reg = GMAC_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* gmii external pad clock for phy operation */
+static struct clk gmii_txclk125_pad = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 125000000,
+};
+
+/* gmac phy set of input clks*/
+static struct pclk_info gmac_phy_input_pclk_info[] = {
+ {
+ .pclk = &gmii_txclk125_pad,
+ .pclk_val = GMAC_PHY_PAD_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = GMAC_PHY_PLL2_VAL,
+ }, {
+ .pclk = &osc3_25m_clk,
+ .pclk_val = GMAC_PHY_OSC3_VAL,
+ },
+};
+
+static struct pclk_sel gmac_phy_input_pclk_sel = {
+ .pclk_info = gmac_phy_input_pclk_info,
+ .pclk_count = ARRAY_SIZE(gmac_phy_input_pclk_info),
+ .pclk_sel_reg = GMAC_CLK_CFG,
+ .pclk_sel_mask = GMAC_PHY_INPUT_CLK_MASK,
+};
+
+static struct clk gmac_phy_input_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gmac_phy_input_pclk_sel,
+ .pclk_sel_shift = GMAC_PHY_INPUT_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gmac rate configuration table, in ascending order of rates */
+struct aux_rate_tbl gmac_rtbl[] = {
+ /* For gmac phy input clk */
+ {.xscale = 1, .yscale = 6, .eq = 1}, /* divided by 6 */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* divided by 4 */
+ {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
+};
+
+static struct clk gmac_phy_synth_clk = {
+ .en_reg = GMAC_CLK_CFG,
+ .en_reg_bit = GMAC_PHY_SYNT_ENB,
+ .pclk = &gmac_phy_input_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {gmac_rtbl, ARRAY_SIZE(gmac_rtbl), 0},
+ .private_data = &gmac_phy_synth_config,
+};
+
+/* gmac phy parents */
+static struct pclk_info gmac_phy_pclk_info[] = {
+ {
+ .pclk = &gmac_phy_input_clk,
+ .pclk_val = 0,
+ }, {
+ .pclk = &gmac_phy_synth_clk,
+ .pclk_val = 1,
+ }
+};
+
+/* gmac phy parent select structure */
+static struct pclk_sel gmac_phy_pclk_sel = {
+ .pclk_info = gmac_phy_pclk_info,
+ .pclk_count = ARRAY_SIZE(gmac_phy_pclk_info),
+ .pclk_sel_reg = GMAC_CLK_CFG,
+ .pclk_sel_mask = GMAC_PHY_CLK_MASK,
+};
+
+/* gmac phy clock */
+static struct clk gmac_phy0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gmac_phy_pclk_sel,
+ .pclk_sel_shift = GMAC_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* clcd synthesizers masks */
+static struct clcd_synth_masks clcd_masks = {
+ .div_factor_mask = CLCD_SYNT_DIV_FACTOR_MASK,
+ .div_factor_shift = CLCD_SYNT_DIV_FACTOR_SHIFT,
+};
+
+static struct clcd_clk_config clcd_synth_config = {
+ .synth_reg = CLCD_CLK_SYNT,
+ .masks = &clcd_masks,
+};
+
+/* clcd synth parents */
+static struct pclk_info clcd_synth_pclk_info[] = {
+ {
+ .pclk = &pll1div4_clk,
+ .pclk_val = CLCD_SYNT_PLL1_DIV4_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = CLCD_SYNT_PLL2_VAL,
+ },
+};
+
+/* clcd synth parent select structure */
+static struct pclk_sel clcd_synth_pclk_sel = {
+ .pclk_info = clcd_synth_pclk_info,
+ .pclk_count = ARRAY_SIZE(clcd_synth_pclk_info),
+ .pclk_sel_reg = PLL_CFG,
+ .pclk_sel_mask = CLCD_SYNT_CLK_MASK,
+};
+
+/* clcd rate configuration table, in ascending order of rates */
+struct clcd_rate_tbl clcd_rtbl[] = {
+ /* For pll1div4 = 250 MHz */
+ {.div = 0x4000}, /* 62.5 MHz */
+ {.div = 0x2000}, /* 125 MHz */
+};
+
+/* clcd synth clock */
+static struct clk clcd_synth_clk = {
+ .en_reg = CLCD_CLK_SYNT,
+ .en_reg_bit = CLCD_SYNT_ENB,
+ .pclk_sel = &clcd_synth_pclk_sel,
+ .pclk_sel_shift = CLCD_SYNT_CLK_SHIFT,
+ .calc_rate = &clcd_calc_rate,
+ .recalc = &clcd_clk_recalc,
+ .set_rate = &clcd_clk_set_rate,
+ .rate_config = {clcd_rtbl, ARRAY_SIZE(clcd_rtbl), 1},
+ .private_data = &clcd_synth_config,
+};
+
+/* clcd clock parents */
+static struct pclk_info clcd_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &clcd_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* clcd parent select structure */
+static struct pclk_sel clcd_pclk_sel = {
+ .pclk_info = clcd_pclk_info,
+ .pclk_count = ARRAY_SIZE(clcd_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = CLCD_CLK_MASK,
+};
+
+/* clcd clock */
+static struct clk clcd_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = CLCD_CLK_ENB,
+ .pclk_sel = &clcd_pclk_sel,
+ .pclk_sel_shift = CLCD_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from ahb clk */
+
+/* i2c clock */
+static struct clk i2c_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2C_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* dma clock */
+static struct clk dma0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk dma1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* jpeg clock */
+static struct clk jpeg_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = JPEG_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gmac clock :Fixed Part*/
+static struct clk gmac0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GMAC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* fsmc clock */
+static struct clk fsmc_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = FSMC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* smi clock */
+static struct clk smi_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SMI_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* uhc0 clock */
+static struct clk uhci0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UHC0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* uhc1 clock */
+static struct clk uhci1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UHC1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* usbd clock */
+static struct clk usbd_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = USBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* pci clocks */
+static struct clk pcie0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk pcie1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk pcie2_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* sysram clocks */
+static struct clk sysram0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SYSRAM0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk sysram1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SYSRAM1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from apb clk */
+/* adc clock */
+static struct clk adc_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = ADC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ssp clock */
+static struct clk ssp_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SSP_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio0_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* i2s0 clock */
+static struct clk i2s0_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2S0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* i2s1 clock */
+static struct clk i2s1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2S1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* keyboard clock */
+static struct clk kbd_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = KBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* RAS CLOCKS */
+/* pll3 generated clock */
+static struct clk ras_pll3_clk = {
+ .pclk = &pll3_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PLL3_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* pll2 generated clock */
+static struct clk ras_pll2_clk = {
+ .pclk = &pll2_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PLL2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* 125MHz clock generated on Tx pad */
+static struct clk ras_tx125_clk = {
+ .pclk = &gmii_txclk125_pad,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C125_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* 30 MHz clock generated by USB PHy Pll */
+static struct clk ras_30Mhz_clk = {
+ .rate = 30000000,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C30_CLK_ENB,
+};
+
+/* 48 MHz clock generated by USB PHy Pll */
+static struct clk ras_48Mhz_clk = {
+ .pclk = &pll5_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C48_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc3 generated clock */
+static struct clk ras_osc3_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC3_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc2 generated clock */
+static struct clk ras_osc2_clk = {
+ .pclk = &osc2_32k_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc1 generated clock */
+static struct clk ras_osc1_clk = {
+ .pclk = &osc1_24m_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* apb generated clock */
+static struct clk ras_pclk_clk = {
+ .pclk = &apb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PCLK_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ahb generated clock */
+static struct clk ras_aclk_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = ACLK_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* External pad 50 MHz clock for phy operation */
+static struct clk ras_tx50_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 50000000,
+};
+
+/* spear1300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR1300
+
+#endif
+
+static struct clk dummy_apb_pclk;
+
+/* array of all spear 13xx clock lookups */
+static struct clk_lookup spear_clk_lookups[] = {
+ { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
+ /* root clks */
+ {.con_id = "osc1_24m_clk", .clk = &osc1_24m_clk},
+ {.con_id = "osc2_32k_clk", .clk = &osc2_32k_clk},
+ {.con_id = "osc3_25m_clk", .clk = &osc3_25m_clk},
+
+ /* clock derived from 32 KHz osc clk */
+ {.dev_id = "rtc-spear", .clk = &rtc_clk},
+
+ /* clock derived from 24/25 MHz osc1/osc3 clk */
+ {.con_id = "pll1_clk", .clk = &pll1_clk},
+ {.con_id = "pll2_clk", .clk = &pll2_clk},
+ {.con_id = "pll3_clk", .clk = &pll3_clk},
+ {.con_id = "pll4_clk", .clk = &pll4_clk},
+ {.con_id = "pll5_clk", .clk = &pll5_clk},
+ {.con_id = "pll6_clk", .clk = &pll6_clk},
+
+ /* clock derived from pll1 clk */
+ {.con_id = "cpu_clk", .clk = &cpu_clk},
+ {.con_id = "ahb_clk", .clk = &ahb_clk},
+ {.con_id = "apb_clk", .clk = &apb_clk},
+
+ /* synthesizers/prescaled clocks */
+ {.con_id = "pll1div2_clk", .clk = &pll1div2_clk},
+ {.con_id = "pll1div4_clk", .clk = &pll1div4_clk},
+ {.con_id = "c3_synth_clk", .clk = &c3_synth_clk},
+ {.con_id = "gmii_txclk123_pad_clk", .clk = &gmii_txclk125_pad},
+ {.con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
+ {.con_id = "uart_synth_clk", .clk = &uart_synth_clk},
+ {.con_id = "sdhci_synth_clk", .clk = &sdhci_synth_clk},
+ {.con_id = "cfxd_synth_clk", .clk = &cfxd_synth_clk},
+ {.con_id = "gmac_phy_input_clk", .clk = &gmac_phy_input_clk},
+ {.con_id = "gmac_phy_synth_clk", .clk = &gmac_phy_synth_clk},
+ {.dev_id = "stmmacphy.0", .clk = &gmac_phy0_clk},
+
+ /* RAS clocks */
+ {.con_id = "ras_pll3_clk", .clk = &ras_pll3_clk},
+ {.con_id = "ras_pll2_clk", .clk = &ras_pll2_clk},
+ {.con_id = "ras_tx125_clk", .clk = &ras_tx125_clk},
+ {.con_id = "ras_30Mhz_clk", .clk = &ras_30Mhz_clk},
+ {.con_id = "ras_48Mhz_clk", .clk = &ras_48Mhz_clk},
+ {.con_id = "ras_osc3_clk", .clk = &ras_osc3_clk},
+ {.con_id = "ras_osc2_clk", .clk = &ras_osc2_clk},
+ {.con_id = "ras_osc1_clk", .clk = &ras_osc1_clk},
+ {.con_id = "ras_pclk_clk", .clk = &ras_pclk_clk},
+ {.con_id = "ras_aclk_clk", .clk = &ras_aclk_clk},
+ {.con_id = "ras_tx50_clk", .clk = &ras_tx50_clk},
+
+ /* clocks having multiple parent source from above clocks */
+ {.dev_id = "clcd", .clk = &clcd_clk},
+ {.dev_id = "gpt0", .clk = &gpt0_clk},
+ {.dev_id = "gpt1", .clk = &gpt1_clk},
+ {.dev_id = "gpt2", .clk = &gpt2_clk},
+ {.dev_id = "gpt3", .clk = &gpt3_clk},
+ {.dev_id = "uart", .clk = &uart_clk},
+
+ /* clock derived from ahb clk */
+ {.dev_id = "smi", .clk = &smi_clk},
+ {.con_id = "usbh.0_clk", .clk = &uhci0_clk},
+ {.con_id = "usbh.1_clk", .clk = &uhci1_clk},
+ {.dev_id = "designware_udc", .clk = &usbd_clk},
+ {.dev_id = "i2c_designware.0", .clk = &i2c_clk},
+ {.dev_id = "dma0", .clk = &dma0_clk},
+ {.dev_id = "dma1", .clk = &dma1_clk},
+ {.dev_id = "jpeg", .clk = &jpeg_clk},
+ {.dev_id = "stmmaceth.0", .clk = &gmac0_clk},
+ {.dev_id = "c3", .clk = &c3_clk},
+ {.dev_id = "pcie0", .clk = &pcie0_clk},
+ {.dev_id = "pcie1", .clk = &pcie1_clk},
+ {.dev_id = "pcie2", .clk = &pcie2_clk},
+ {.dev_id = "cfxd", .clk = &cfxd_clk},
+ {.dev_id = "sdhci", .clk = &sdhci_clk},
+ {.con_id = "fsmc", .clk = &fsmc_clk},
+ {.dev_id = "sysram0", .clk = &sysram0_clk},
+ {.dev_id = "sysram1", .clk = &sysram1_clk},
+
+ /* clock derived from apb clk */
+ {.dev_id = "i2s0", .clk = &i2s0_clk},
+ {.dev_id = "i2s1", .clk = &i2s1_clk},
+ {.dev_id = "adc", .clk = &adc_clk},
+ {.dev_id = "ssp-pl022", .clk = &ssp_clk},
+ {.dev_id = "gpio0", .clk = &gpio0_clk},
+ {.dev_id = "gpio1", .clk = &gpio1_clk},
+ {.dev_id = "keyboard", .clk = &kbd_clk},
+ {.dev_id = "wdt", .clk = &wdt_clk},
+};
+
+/* array of all spear 1300 clock lookups */
+#ifdef CONFIG_MACH_SPEAR1300
+static struct clk_lookup spear1300_clk_lookups[] = {
+};
+#endif
+
+void __init spear13xx_clk_init(void)
+{
+ int i, cnt;
+ struct clk_lookup *lookups;
+
+ if (machine_is_spear1300()) {
+ cnt = ARRAY_SIZE(spear1300_clk_lookups);
+ lookups = spear1300_clk_lookups;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ for (i = 0; i < cnt; i++)
+ clk_register(&lookups[i]);
+
+ clk_init();
+}
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
new file mode 100644
index 0000000..502c4fe
--- /dev/null
+++ b/arch/arm/mach-spear13xx/headsmp.S
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-spear13XX/headsmp.S
+ *
+ * Picked from realview
+ * Copyright (c) 2010 ST Microelectronics Limited
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+/*
+ * spear13xx specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(spear13xx_secondary_startup)
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ /*
+ * we've been released from the holding pen: secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+
+ .align
+1: .long .
+ .long pen_release
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 95011a2..781894e 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -33,7 +33,7 @@ extern struct amba_device spear13xx_uart_device;
extern struct sys_timer spear13xx_timer;
/* Add spear13xx family function declarations here */
-void __init clk_init(void);
+void __init spear13xx_clk_init(void);
void __init spear_setup_timer(void);
void __init spear13xx_map_io(void);
void __init spear13xx_init_irq(void);
diff --git a/arch/arm/mach-spear13xx/localtimer.c b/arch/arm/mach-spear13xx/localtimer.c
new file mode 100644
index 0000000..816b08c
--- /dev/null
+++ b/arch/arm/mach-spear13xx/localtimer.c
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear13xx/localtimer.c
+ * Directly picked from realview
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/* Setup the local clock events for a CPU. */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+ evt->irq = IRQ_LOCALTIMER;
+ twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
new file mode 100644
index 0000000..6aa4435
--- /dev/null
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -0,0 +1,162 @@
+/*
+ * arch/arm/mach-spear13xx/platsmp.c
+ *
+ * based upon linux/arch/arm/mach-realview/platsmp.c
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/smp_scu.h>
+#include <asm/system.h>
+#include <asm/unified.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+static DEFINE_SPINLOCK(boot_lock);
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not. This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+ pen_release = val;
+ smp_wmb();
+ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static void __iomem *scu_base_addr(void)
+{
+ return __io_address(SPEAR13XX_SCU_BASE);
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+ /*
+ * if any interrupts are already enabled for the primary
+ * core (e.g. timer irq), then they will not have been enabled
+ * for us: do so
+ */
+ gic_secondary_init(0);
+
+ /*
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+ write_pen_release(-1);
+
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long timeout;
+
+ /*
+ * set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ /*
+ * The secondary processor is waiting to be released from
+ * the holding pen - release it, then wait for it to flag
+ * that it has been released by resetting pen_release.
+ *
+ * Note that "pen_release" is the hardware CPU ID, whereas
+ * "cpu" is Linux's internal ID.
+ */
+ write_pen_release(cpu);
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+ smp_rmb();
+ if (pen_release == -1)
+ break;
+
+ udelay(10);
+ }
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+ void __iomem *scu_base = scu_base_addr();
+ unsigned int i, ncores;
+
+ ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+}
+
+static void __init wakeup_secondary(void)
+{
+ /*
+ * Write the address of secondary startup into the system-wide
+ * location (presently it is in SRAM). The BootMonitor waits
+ * for this register to become non-zero.
+ * We must also send an sev to wake it up
+ */
+ __raw_writel(BSYM(virt_to_phys(spear13xx_secondary_startup)),
+ __io_address(SPEAR13XX_SYS_LOCATION));
+
+ mb();
+
+ /*
+ * Send a 'sev' to wake the secondary core from WFE.
+ */
+ sev();
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ /*
+ * Initialise the present map, which describes the set of CPUs
+ * actually populated at the present time.
+ */
+ for (i = 0; i < max_cpus; i++)
+ set_cpu_present(i, true);
+
+ scu_enable(scu_base_addr());
+ wakeup_secondary();
+}
diff --git a/arch/arm/mach-spear13xx/spear1300.c b/arch/arm/mach-spear13xx/spear1300.c
new file mode 100644
index 0000000..9c38bec
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1300.c
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-spear13xx/spear1300.c
+ *
+ * SPEAr1300 machine source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* Add spear1300 specific devices here */
+
+void __init spear1300_init(void)
+{
+ /* call spear13xx family common init function */
+ spear13xx_init();
+}
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
new file mode 100644
index 0000000..c95c141
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-spear13xx/spear1300_evb.c
+ *
+ * SPEAr1300 evaluation board source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ &spear13xx_uart_device,
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+};
+
+static void __init spear1300_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear1300 machine init function */
+ spear1300_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR1300, "ST-SPEAR1300-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear13xx_map_io,
+ .init_irq = spear13xx_init_irq,
+ .timer = &spear13xx_timer,
+ .init_machine = spear1300_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
new file mode 100644
index 0000000..06f9abb
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -0,0 +1,121 @@
+/*
+ * arch/arm/mach-spear13xx/spear13xx.c
+ *
+ * SPEAr13XX machines common source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/io.h>
+#include <asm/hardware/gic.h>
+#include <asm/irq.h>
+#include <asm/localtimer.h>
+#include <asm/mach/arch.h>
+#include <asm/smp_twd.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+/* Add spear13xx machines common devices here */
+/* uart device registeration */
+struct amba_device spear13xx_uart_device = {
+ .dev = {
+ .init_name = "uart",
+ },
+ .res = {
+ .start = SPEAR13XX_UART_BASE,
+ .end = SPEAR13XX_UART_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART, NO_IRQ},
+};
+
+/* Do spear13xx familiy common initialization part here */
+void __init spear13xx_init(void)
+{
+ /* nothing to do for now */
+}
+
+/* This will initialize vic */
+void __init spear13xx_init_irq(void)
+{
+ gic_init(0, 29, __io_address(SPEAR13XX_GIC_DIST_BASE),
+ __io_address(SPEAR13XX_GIC_CPU_BASE));
+}
+
+/* Following will create static virtual/physical mappings */
+struct map_desc spear13xx_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(SPEAR13XX_UART_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_UART_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_A9SM_PERIP_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_MISC_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_MISC_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_SYSRAM0_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_SYSRAM0_BASE),
+ .length = SZ_32K,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear13xx_map_io(void)
+{
+ iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
+
+ /* This will initialize clock framework */
+ spear13xx_clk_init();
+}
+
+static void __init spear13xx_timer_init(void)
+{
+ char pclk_name[] = "osc1_24m_clk";
+ struct clk *gpt_clk, *pclk;
+
+#ifdef CONFIG_LOCAL_TIMERS
+ /* Setup the local timer base */
+ twd_base = __io_address(SPEAR13XX_LOCAL_TMR_BASE);
+#endif
+
+ /* get the system timer clock */
+ gpt_clk = clk_get_sys("gpt0", NULL);
+ if (IS_ERR(gpt_clk)) {
+ pr_err("%s:couldn't get clk for gpt\n", __func__);
+ BUG();
+ }
+
+ /* get the suitable parent clock for timer*/
+ pclk = clk_get(NULL, pclk_name);
+ if (IS_ERR(pclk)) {
+ pr_err("%s:couldn't get %s as parent for gpt\n",
+ __func__, pclk_name);
+ BUG();
+ }
+
+ clk_set_parent(gpt_clk, pclk);
+ clk_put(gpt_clk);
+ clk_put(pclk);
+
+ spear_setup_timer();
+}
+
+struct sys_timer spear13xx_timer = {
+ .init = spear13xx_timer_init,
+};
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 03/10] ST SPEAr13xx: Adding support in SPEAr generic plat/
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 01/10] ST SPEAr13xx: Adding machine specific header files Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 02/10] ST SPEAr13xx: Adding machine specific src files Viresh Kumar
@ 2011-03-01 11:27 ` Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 04/10] ST SPEAr13xx: Added compilation support in arch/arm/ Viresh Kumar
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/plat-spear/Kconfig | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbc..29a25d2 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -8,6 +8,13 @@ choice
prompt "ST SPEAr Family"
default ARCH_SPEAR3XX
+config ARCH_SPEAR13XX
+ bool "SPEAr13XX"
+ select ARM_GIC
+ select CPU_V7
+ help
+ Supports for ARM's SPEAR13XX family
+
config ARCH_SPEAR3XX
bool "SPEAr3XX"
select ARM_VIC
@@ -25,6 +32,7 @@ config ARCH_SPEAR6XX
endchoice
# Adding SPEAr machine specific configuration files
+source "arch/arm/mach-spear13xx/Kconfig"
source "arch/arm/mach-spear3xx/Kconfig"
source "arch/arm/mach-spear6xx/Kconfig"
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 04/10] ST SPEAr13xx: Added compilation support in arch/arm/
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (2 preceding siblings ...)
2011-03-01 11:27 ` [PATCH V6 03/10] ST SPEAr13xx: Adding support in SPEAr generic plat/ Viresh Kumar
@ 2011-03-01 11:27 ` Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 05/10] ST SPEAr13xx: Adding default config file Viresh Kumar
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
This patch adds compilation support for ST Microelectronics SPEAr13xx machines.
SPEAr13xx SOC's are based on Arm CortexA9 CPUs.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/Kconfig | 4 ++--
arch/arm/Makefile | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 166efa2..d9efe86 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1278,8 +1278,8 @@ config SMP
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
- ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
- ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
+ ARCH_S5PV310 || ARCH_SPEAR13XX || ARCH_TEGRA || ARCH_U8500 || \
+ ARCH_VEXPRESS_CA9X4 || ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
select USE_GENERIC_SMP_HELPERS
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f7b292..f4f3021 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -193,6 +193,7 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
machine-$(CONFIG_FOOTBRIDGE) := footbridge
+machine-$(CONFIG_MACH_SPEAR1300) := spear13xx
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 05/10] ST SPEAr13xx: Adding default config file
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (3 preceding siblings ...)
2011-03-01 11:27 ` [PATCH V6 04/10] ST SPEAr13xx: Added compilation support in arch/arm/ Viresh Kumar
@ 2011-03-01 11:27 ` Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 06/10] ST SPEAr13xx: Adding information in Documentation/ and MAINTAINERS Viresh Kumar
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/configs/spear13xx_defconfig | 60 ++++++++++++++++++++++++++++++++++
1 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/configs/spear13xx_defconfig
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
new file mode 100644
index 0000000..10b1cf5
--- /dev/null
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -0,0 +1,60 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR13XX=y
+CONFIG_BOARD_SPEAR1300_EVB=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_AEABI=y
+CONFIG_BINFMT_MISC=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+# CONFIG_HWMON is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_INFO=y
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 06/10] ST SPEAr13xx: Adding information in Documentation/ and MAINTAINERS
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (4 preceding siblings ...)
2011-03-01 11:27 ` [PATCH V6 05/10] ST SPEAr13xx: Adding default config file Viresh Kumar
@ 2011-03-01 11:27 ` Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 07/10] ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms Viresh Kumar
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
Documentation/arm/SPEAr/overview.txt | 34 +++++++++++++++++++++++-----------
MAINTAINERS | 6 ++++++
2 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c..4e510061 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -9,8 +9,9 @@ Introduction
The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
supported by the 'spear' platform of ARM Linux. Currently SPEAr300,
- SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX
- series is in progress.
+ SPEAr310, SPEAr320, SPEAr600, SPEAr1300 and SPEAr1310 SOCs are supported.
+ SPEAr3XX and SPEAr6XX are based on ARM9 whereas SPEAr13XX is based on latest
+ ARM Cortex A9 CPUs.
Hierarchy in SPEAr is as follows:
@@ -27,16 +28,25 @@ Introduction
- SPEAr600_EVB (Evaluation Board)
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
+ - SPEAr1300_EVB (Evaluation Board)
+ - SPEAr1310 (SOC)
+ - SPEAr1310_EVB (Evaluation Board)
Configuration
-------------
- A generic configuration is provided for each machine, and can be used as the
+ A generic configuration is provided for each machine family, and can be used as the
default by
- make spear600_defconfig
- make spear300_defconfig
- make spear310_defconfig
- make spear320_defconfig
+ #make ARCH=arm spear13xx_defconfig
+ #make ARCH=arm spear3xx_defconfig
+ #make ARCH=arm spear6xx_defconfig
+
+ Compilation
+ -----------
+
+ After applying default configuration, Linux kernel for SPEAr architecture
+ can be compiled as
+ #make ARCH=arm CROSS_COMPILE=arm-linux- uImage
Layout
------
@@ -48,13 +58,15 @@ Introduction
Each machine series have a directory with name arch/arm/mach-spear followed by
series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
- Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
- spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
+ Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for
+ spear6xx is mach-spear6xx/spear6xx.c and similarly for spear13xx is
+ mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
- mach-spear* also contains board specific files for each machine type.
+ Board specific files for each machine type is also contained in mach-spear*
+ folder.
Document Author
---------------
- Viresh Kumar, (c) 2010 ST Microelectronics
+ Viresh Kumar, Shiraz Hashim (c) 2010 ST Microelectronics
diff --git a/MAINTAINERS b/MAINTAINERS
index 8afba63..da45149 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5852,6 +5852,12 @@ W: http://www.st.com/spear
S: Maintained
F: arch/arm/plat-spear/
+SPEAR13XX MACHINE SUPPORT
+M: Shiraz Hashim <shiraz.hashim@st.com>
+W: http://www.st.com/spear
+S: Maintained
+F: arch/arm/mach-spear13xx/
+
SPEAR3XX MACHINE SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
W: http://www.st.com/spear
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 07/10] ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (5 preceding siblings ...)
2011-03-01 11:27 ` [PATCH V6 06/10] ST SPEAr13xx: Adding information in Documentation/ and MAINTAINERS Viresh Kumar
@ 2011-03-01 11:27 ` Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 08/10] ST SPEAr13xx: add L2 cache support Viresh Kumar
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
From: Deepak Sikri <deepak.sikri@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/Makefile | 1 +
arch/arm/mach-spear13xx/hotplug.c | 121 +++++++++++++++++++++++++++++++++++++
2 files changed, 122 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/hotplug.c
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
index cb5ae9e..09b71e4 100644
--- a/arch/arm/mach-spear13xx/Makefile
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -5,6 +5,7 @@
# common files
obj-y += spear13xx.o clock.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
# spear1300 specific files
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
new file mode 100644
index 0000000..ee6b06d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -0,0 +1,121 @@
+/*
+ * linux/arch/arm/mach-spear13xx/hotplug.c
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Deepak Sikri <deepak.sikri@st.com>
+ *
+ * based upon linux/arch/arm/mach-realview/hotplug.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/system.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+ unsigned int v;
+
+ flush_cache_all();
+ asm volatile(
+ " mcr p15, 0, %1, c7, c5, 0\n"
+ " dsb\n"
+ /*
+ * Turn off coherency
+ */
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " bic %0, %0, #0x20\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " bic %0, %0, %2\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ : "=&r" (v)
+ : "r" (0), "Ir" (CR_C)
+ : "cc", "memory");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+ unsigned int v;
+
+ asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+ " orr %0, %0, %1\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " orr %0, %0, #0x20\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v)
+ : "Ir" (CR_C)
+ : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+ for (;;) {
+ wfi();
+
+ if (pen_release == cpu) {
+ /*
+ * OK, proper wakeup, we're done
+ */
+ break;
+ }
+
+ /*
+ * Getting here, means that we have come out of WFI without
+ * having been woken up - this shouldn't happen
+ *
+ * Just note it happening - when we're woken, we can report
+ * its occurrence.
+ */
+ (*spurious)++;
+ }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+ return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __cpuinit platform_cpu_die(unsigned int cpu)
+{
+ int spurious = 0;
+
+ /*
+ * we're ready for shutdown now, so do it
+ */
+ cpu_enter_lowpower();
+ platform_do_lowpower(cpu, &spurious);
+
+ /*
+ * bring this CPU back into the world of cache
+ * coherency, and then restore interrupts
+ */
+ cpu_leave_lowpower();
+
+ if (spurious)
+ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+ /*
+ * we don't allow CPU 0 to be shutdown (it is still too special
+ * e.g. clock tick interrupts)
+ */
+ return cpu == 0 ? -EPERM : 0;
+}
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 08/10] ST SPEAr13xx: add L2 cache support
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (6 preceding siblings ...)
2011-03-01 11:27 ` [PATCH V6 07/10] ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms Viresh Kumar
@ 2011-03-01 11:27 ` Viresh Kumar
2011-03-01 11:27 ` [PATCH V6 09/10] ST SPEAr13xx: Adding support for SPEAr1310 Viresh Kumar
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/spear13xx.c | 19 ++++++++++++++++++-
arch/arm/mm/Kconfig | 2 +-
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 06f9abb..b5da555 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -18,6 +18,7 @@
#include <asm/irq.h>
#include <asm/localtimer.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
#include <asm/smp_twd.h>
#include <mach/generic.h>
#include <mach/hardware.h>
@@ -40,7 +41,16 @@ struct amba_device spear13xx_uart_device = {
/* Do spear13xx familiy common initialization part here */
void __init spear13xx_init(void)
{
- /* nothing to do for now */
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * 512KB (64KB/way), 8-way associativity, parity supported
+ *
+ * TODO: 0x249, picked from nomadik, to be analyzed
+ * Comment from nomadik:
+ * At full speed latency must be >=2, so 0x249 in low bits
+ */
+ l2x0_init(__io_address(SPEAR13XX_L2CC_BASE), 0x00260249, 0xfe00ffff);
+#endif
}
/* This will initialize vic */
@@ -62,6 +72,13 @@ struct map_desc spear13xx_io_desc[] __initdata = {
.pfn = __phys_to_pfn(SPEAR13XX_A9SM_PERIP_BASE),
.length = SZ_8K,
.type = MT_DEVICE
+#ifdef CONFIG_CACHE_L2X0
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_L2CC_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_L2CC_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+#endif
}, {
.virtual = IO_ADDRESS(SPEAR13XX_MISC_BASE),
.pfn = __phys_to_pfn(SPEAR13XX_MISC_BASE),
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e4509ba..fff2d89 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -813,7 +813,7 @@ config CACHE_L2X0
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
+ ARCH_SPEAR13XX || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
default y
select OUTER_CACHE
select OUTER_CACHE_SYNC
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 09/10] ST SPEAr13xx: Adding support for SPEAr1310
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (7 preceding siblings ...)
2011-03-01 11:27 ` [PATCH V6 08/10] ST SPEAr13xx: add L2 cache support Viresh Kumar
@ 2011-03-01 11:27 ` Viresh Kumar
2011-03-01 11:30 ` [PATCH V6 10/10] ST SPEAr13xx: Add padmux support Viresh Kumar
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
From: Bhupesh Sharma <bhupesh.sharma@st.com>
This patch adds support for SPEAr1310 Machine and evaluation board.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
---
arch/arm/Makefile | 1 +
arch/arm/configs/spear13xx_defconfig | 1 +
arch/arm/mach-spear13xx/Kconfig | 11 ++
arch/arm/mach-spear13xx/Makefile | 6 +
arch/arm/mach-spear13xx/clock.c | 154 ++++++++++++++++++++++
arch/arm/mach-spear13xx/include/mach/generic.h | 17 +++
arch/arm/mach-spear13xx/include/mach/irqs.h | 37 +++++
arch/arm/mach-spear13xx/include/mach/spear.h | 1 +
arch/arm/mach-spear13xx/include/mach/spear1310.h | 64 +++++++++
arch/arm/mach-spear13xx/spear1310.c | 144 ++++++++++++++++++++
arch/arm/mach-spear13xx/spear1310_evb.c | 61 +++++++++
11 files changed, 497 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1310.h
create mode 100644 arch/arm/mach-spear13xx/spear1310.c
create mode 100644 arch/arm/mach-spear13xx/spear1310_evb.c
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f4f3021..4b25e69 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -194,6 +194,7 @@ machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
machine-$(CONFIG_FOOTBRIDGE) := footbridge
machine-$(CONFIG_MACH_SPEAR1300) := spear13xx
+machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 10b1cf5..9f3baf8 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -9,6 +9,7 @@ CONFIG_MODVERSIONS=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR13XX=y
CONFIG_BOARD_SPEAR1300_EVB=y
+CONFIG_BOARD_SPEAR1310_EVB=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_AEABI=y
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
index 3ea463d..229ef93 100644
--- a/arch/arm/mach-spear13xx/Kconfig
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -11,6 +11,12 @@ config BOARD_SPEAR1300_EVB
help
Supports ST SPEAr1300 Evaluation Board
+config BOARD_SPEAR1310_EVB
+ bool "SPEAr1310 Evaluation Board"
+ select MACH_SPEAR1310
+ help
+ Supports ST SPEAr1310 Evaluation Board
+
endmenu
config MACH_SPEAR1300
@@ -18,4 +24,9 @@ config MACH_SPEAR1300
help
Supports ST SPEAr1300 Machine
+config MACH_SPEAR1310
+ bool "SPEAr1310"
+ help
+ Supports ST SPEAr1310 Machine
+
endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
index 09b71e4..24bbe16 100644
--- a/arch/arm/mach-spear13xx/Makefile
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -13,3 +13,9 @@ obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
# spear1300 boards files
obj-$(CONFIG_BOARD_SPEAR1300_EVB) += spear1300_evb.o
+
+# spear1310 specific files
+obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
+
+# spear1310 boards files
+obj-$(CONFIG_BOARD_SPEAR1310_EVB) += spear1310_evb.o
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
index 58d3ec0..008749a 100644
--- a/arch/arm/mach-spear13xx/clock.c
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -896,6 +896,136 @@ static struct clk ras_tx50_clk = {
#endif
+/* spear1310 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR1310
+/* can0 clock */
+static struct clk can0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* can1 clock */
+static struct clk can1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* gmac clocks :RAS part*/
+static struct clk gmac_ras1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+static struct clk gmac_ras2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+static struct clk gmac_ras3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+static struct clk gmac_ras4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* phy clock parent select */
+static struct pclk_info phy_pclk_info[] = {
+ {
+ .pclk = &ras_pll2_clk,
+ .pclk_val = 0x8,
+ }, {
+ .pclk = &ras_tx125_clk,
+ .pclk_val = 0x4,
+ }, {
+ .pclk = &ras_tx50_clk,
+ .pclk_val = 0x0,
+ },
+};
+
+static struct pclk_sel phy_pclk_sel = {
+ .pclk_info = phy_pclk_info,
+ .pclk_count = ARRAY_SIZE(phy_pclk_info),
+ .pclk_sel_reg = IOMEM(IO_ADDRESS(SPEAR1310_RAS_CTRL_REG1)),
+ .pclk_sel_mask = SPEAR1310_PHY_CLK_MASK,
+};
+
+/* Phy 1 Clock */
+struct clk gmac_phy1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* Phy 2 Clock */
+static struct clk gmac_phy2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* Phy 3 Clock */
+static struct clk gmac_phy3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* Phy 4 Clock */
+static struct clk gmac_phy4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* uart1 clock */
+static struct clk uart1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart2 clock */
+static struct clk uart2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart3 clock */
+static struct clk uart3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart4 clock */
+static struct clk uart4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart5 clock */
+static struct clk uart5_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+#endif
+
static struct clk dummy_apb_pclk;
/* array of all spear 13xx clock lookups */
@@ -993,6 +1123,27 @@ static struct clk_lookup spear1300_clk_lookups[] = {
};
#endif
+/* array of all spear 1310 clock lookups */
+#ifdef CONFIG_MACH_SPEAR1310
+static struct clk_lookup spear1310_clk_lookups[] = {
+ {.dev_id = "c_can_platform.0", .clk = &can0_clk},
+ {.dev_id = "c_can_platform.1", .clk = &can1_clk},
+ {.dev_id = "stmmaceth.1", .clk = &gmac_ras1_clk},
+ {.dev_id = "stmmaceth.2", .clk = &gmac_ras2_clk},
+ {.dev_id = "stmmaceth.3", .clk = &gmac_ras3_clk},
+ {.dev_id = "stmmaceth.4", .clk = &gmac_ras4_clk},
+ {.dev_id = "stmmacphy.1", .clk = &gmac_phy1_clk},
+ {.dev_id = "stmmacphy.2", .clk = &gmac_phy2_clk},
+ {.dev_id = "stmmacphy.3", .clk = &gmac_phy3_clk},
+ {.dev_id = "stmmacphy.4", .clk = &gmac_phy4_clk},
+ {.dev_id = "uart1", .clk = &uart1_clk},
+ {.dev_id = "uart2", .clk = &uart2_clk},
+ {.dev_id = "uart3", .clk = &uart3_clk},
+ {.dev_id = "uart4", .clk = &uart4_clk},
+ {.dev_id = "uart5", .clk = &uart5_clk},
+};
+#endif
+
void __init spear13xx_clk_init(void)
{
int i, cnt;
@@ -1001,6 +1152,9 @@ void __init spear13xx_clk_init(void)
if (machine_is_spear1300()) {
cnt = ARRAY_SIZE(spear1300_clk_lookups);
lookups = spear1300_clk_lookups;
+ } else {
+ cnt = ARRAY_SIZE(spear1310_clk_lookups);
+ lookups = spear1310_clk_lookups;
}
for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 781894e..64feaa5 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -47,4 +47,21 @@ void __init spear1300_init(void);
#endif /* CONFIG_MACH_SPEAR1300 */
+/* spear1310 declarations */
+#ifdef CONFIG_MACH_SPEAR1310
+/* Add spear1310 machine device structure declarations here */
+extern struct amba_device spear1310_uart1_device;
+extern struct amba_device spear1310_uart2_device;
+extern struct amba_device spear1310_uart3_device;
+extern struct amba_device spear1310_uart4_device;
+extern struct amba_device spear1310_uart5_device;
+extern struct platform_device spear1310_can0_device;
+extern struct platform_device spear1310_can1_device;
+
+/* Add spear1310 machine function declarations here */
+void __init spear1310_init(void);
+void __init spear1310_map_io(void);
+
+#endif /* CONFIG_MACH_SPEAR1310 */
+
#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
index d9fe051..c175175 100644
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -5,6 +5,7 @@
*
* Copyright (C) 2010 ST Microelectronics
* Shiraz Hashim <shiraz.hashim@st.com>
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
@@ -84,6 +85,42 @@
#define IRQ_PCIE1 (IRQ_SHPI_START + 69)
#define IRQ_PCIE2 (IRQ_SHPI_START + 70)
+/* Add spear1310 specific IRQs here */
+#ifdef CONFIG_MACH_SPEAR1310
+#define IRQ_FSMC_PC1 (IRQ_SHPI_START + 76)
+#define IRQ_FSMC_PC2 (IRQ_SHPI_START + 77)
+#define IRQ_FSMC_PC3 (IRQ_SHPI_START + 78)
+#define IRQ_FSMC_PC4 (IRQ_SHPI_START + 79)
+#define IRQ_RS4850 (IRQ_SHPI_START + 80)
+#define IRQ_RS4851 (IRQ_SHPI_START + 81)
+#define IRQ_CCAN0 (IRQ_SHPI_START + 82)
+#define IRQ_CCAN1 (IRQ_SHPI_START + 83)
+#define IRQ_TDM0 (IRQ_SHPI_START + 84)
+#define IRQ_TDM1 (IRQ_SHPI_START + 85)
+#define IRQ_UART1 (IRQ_SHPI_START + 86)
+#define IRQ_UART2 (IRQ_SHPI_START + 87)
+#define IRQ_UART3 (IRQ_SHPI_START + 88)
+#define IRQ_UART4 (IRQ_SHPI_START + 89)
+#define IRQ_UART5 (IRQ_SHPI_START + 90)
+#define IRQ_I2C_CNTR (IRQ_SHPI_START + 91)
+#define IRQ_GMAC0_SBD (IRQ_SHPI_START + 92)
+#define IRQ_GMAC0_PMT (IRQ_SHPI_START + 93)
+#define IRQ_GMAC1_SBD (IRQ_SHPI_START + 94)
+#define IRQ_GMAC1_PMT (IRQ_SHPI_START + 95)
+#define IRQ_GMAC2_SBD (IRQ_SHPI_START + 96)
+#define IRQ_GMAC2_PMT (IRQ_SHPI_START + 97)
+#define IRQ_GMAC3_SBD (IRQ_SHPI_START + 98)
+#define IRQ_GMAC3_PMT (IRQ_SHPI_START + 99)
+#define IRQ_GPIO (IRQ_SHPI_START + 100)
+#define IRQ_PCI_BRDG_HOST_FATAL (IRQ_SHPI_START + 101)
+#define IRQ_PCI_INTA (IRQ_SHPI_START + 102)
+#define IRQ_PCI_INTB (IRQ_SHPI_START + 103)
+#define IRQ_PCI_INTC (IRQ_SHPI_START + 104)
+#define IRQ_PCI_INTD (IRQ_SHPI_START + 105)
+#define IRQ_PCI_ME_TO_ARM (IRQ_SHPI_START + 106)
+#define IRQ_PCI_SERR_TO_ARM (IRQ_SHPI_START + 107)
+#endif /* CONFIG_MACH_SPEAR1310 */
+
#define IRQ_GIC_END (IRQ_SHPI_START + 128)
#define NR_IRQS IRQ_GIC_END
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 1a1af72..cf25eb5 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -16,6 +16,7 @@
#include <asm/memory.h>
#include <mach/spear1300.h>
+#include <mach/spear1310.h>
#define SPEAR13XX_L2CC_BASE UL(0xED000000)
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310.h b/arch/arm/mach-spear13xx/include/mach/spear1310.h
new file mode 100644
index 0000000..34f0a27
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1310.h
@@ -0,0 +1,64 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear1310.h
+ *
+ * SPEAr1310 Machine specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR1310
+
+#ifndef __MACH_SPEAR1310_H
+#define __MACH_SPEAR1310_H
+
+#define SPEAR1310_TDM_E1_0_BASE UL(0x6C200000)
+#define SPEAR1310_TDM_E1_1_BASE UL(0x6C300000)
+#define SPEAR1310_RS485_0_BASE UL(0x6C400000)
+#define SPEAR1310_RS485_1_BASE UL(0x6C500000)
+#define SPEAR1310_GETH1_BASE UL(0x6D000000)
+#define SPEAR1310_GETH2_BASE UL(0x6D100000)
+#define SPEAR1310_GETH3_BASE UL(0x6D200000)
+#define SPEAR1310_GETH4_BASE UL(0x6D300000)
+#define SPEAR1310_UART1_BASE UL(0x6D400000)
+#define SPEAR1310_UART2_BASE UL(0x6D500000)
+#define SPEAR1310_UART3_BASE UL(0x6D600000)
+#define SPEAR1310_UART4_BASE UL(0x6D700000)
+#define SPEAR1310_UART5_BASE UL(0x6D800000)
+#define SPEAR1310_I2C1_BASE UL(0x6D900000)
+#define SPEAR1310_CAN0_BASE UL(0x6DA00000)
+#define SPEAR1310_CAN1_BASE UL(0x6DB00000)
+#define SPEAR1310_RAS_BASE UL(0x6C800000)
+#define SPEAR1310_GETH1_BASE UL(0x6D000000)
+#define SPEAR1310_GETH2_BASE UL(0x6D100000)
+#define SPEAR1310_GETH3_BASE UL(0x6D200000)
+#define SPEAR1310_GETH4_BASE UL(0x6D300000)
+#define SPEAR1310_FSMC1_CS0_BASE UL(0x70000000)
+#define SPEAR1310_FSMC1_CS1_BASE UL(0x74000000)
+#define SPEAR1310_FSMC1_CS2_BASE UL(0x78000000)
+#define SPEAR1310_FSMC1_CS3_BASE UL(0x7C000000)
+#define SPEAR1310_FSMC1_BASE UL(0x6FF00000)
+
+/* RAS Area Control Register */
+#define SPEAR1310_RAS_CTRL_REG0 (SPEAR1310_RAS_BASE + 0x0)
+#define SPEAR1310_RAS_CTRL_REG1 (SPEAR1310_RAS_BASE + 0x4)
+#define SPEAR1310_PHY_CLK_MASK 0xF
+#define SPEAR1310_PHY_CLK_SHIFT 0
+
+#define RAS_FSMC_MODE_MASK 0x3
+#define RAS_FSMC_MODE_NOR 0
+#define RAS_FSMC_MODE_NAND 1
+#define RAS_FSMC_MODE_SRAM 2
+#define RAS_FSMC_WIDTH_MASK 0x30
+#define RAS_FSMC_WIDTH_8 0x00
+#define RAS_FSMC_WIDTH_16 0x10
+#define RAS_FSMC_WIDTH_32 0x20
+#define RAS_FSMC_CS_SPLIT 0x40
+
+#endif /* __MACH_SPEAR1310_H */
+
+#endif /* CONFIG_MACH_SPEAR1310 */
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
new file mode 100644
index 0000000..e4ad092
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -0,0 +1,144 @@
+/*
+ * arch/arm/mach-spear13xx/spear1310.c
+ *
+ * SPEAr1310 machine source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/ptrace.h>
+#include <asm/irq.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* Add spear1310 specific devices here */
+/* uart1 device registeration */
+struct amba_device spear1310_uart1_device = {
+ .dev = {
+ .init_name = "uart1",
+ },
+ .res = {
+ .start = SPEAR1310_UART1_BASE,
+ .end = SPEAR1310_UART1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART1, NO_IRQ},
+};
+
+/* uart2 device registeration */
+struct amba_device spear1310_uart2_device = {
+ .dev = {
+ .init_name = "uart2",
+ },
+ .res = {
+ .start = SPEAR1310_UART2_BASE,
+ .end = SPEAR1310_UART2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART2, NO_IRQ},
+};
+
+/* uart3 device registeration */
+struct amba_device spear1310_uart3_device = {
+ .dev = {
+ .init_name = "uart3",
+ },
+ .res = {
+ .start = SPEAR1310_UART3_BASE,
+ .end = SPEAR1310_UART3_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART3, NO_IRQ},
+};
+
+/* uart4 device registeration */
+struct amba_device spear1310_uart4_device = {
+ .dev = {
+ .init_name = "uart4",
+ },
+ .res = {
+ .start = SPEAR1310_UART4_BASE,
+ .end = SPEAR1310_UART4_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART4, NO_IRQ},
+};
+
+/* uart5 device registeration */
+struct amba_device spear1310_uart5_device = {
+ .dev = {
+ .init_name = "uart5",
+ },
+ .res = {
+ .start = SPEAR1310_UART5_BASE,
+ .end = SPEAR1310_UART5_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART5, NO_IRQ},
+};
+
+/* CAN device registeration */
+static struct resource can0_resources[] = {
+ {
+ .start = SPEAR1310_CAN0_BASE,
+ .end = SPEAR1310_CAN0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_CCAN0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear1310_can0_device = {
+ .name = "c_can_platform",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(can0_resources),
+ .resource = can0_resources,
+};
+
+static struct resource can1_resources[] = {
+ {
+ .start = SPEAR1310_CAN1_BASE,
+ .end = SPEAR1310_CAN1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_CCAN1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear1310_can1_device = {
+ .name = "c_can_platform",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(can1_resources),
+ .resource = can1_resources,
+};
+
+/* Following will create 1310 specific static virtual/physical mappings */
+struct map_desc spear1310_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(SPEAR1310_RAS_BASE),
+ .pfn = __phys_to_pfn(SPEAR1310_RAS_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear1310_map_io(void)
+{
+ iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
+ spear13xx_map_io();
+}
+
+void __init spear1310_init(void)
+{
+ /* call spear13xx family common init function */
+ spear13xx_init();
+}
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
new file mode 100644
index 0000000..a87e82b
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-spear13xx/spear1310_evb.c
+ *
+ * SPEAr1310 evaluation board source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ /* spear13xx specific devices */
+ &spear13xx_uart_device,
+
+ /* spear1310 specific devices */
+ &spear1310_uart1_device,
+ &spear1310_uart2_device,
+ &spear1310_uart3_device,
+ &spear1310_uart4_device,
+ &spear1310_uart5_device,
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+ /* spear13xx specific devices */
+
+ /* spear1310 specific devices */
+ &spear1310_can0_device,
+ &spear1310_can1_device,
+};
+
+static void __init spear1310_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear1310 machine init function */
+ spear1310_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR1310, "ST-SPEAR1310-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear1310_map_io,
+ .init_irq = spear13xx_init_irq,
+ .timer = &spear13xx_timer,
+ .init_machine = spear1310_evb_init,
+MACHINE_END
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 10/10] ST SPEAr13xx: Add padmux support
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (8 preceding siblings ...)
2011-03-01 11:27 ` [PATCH V6 09/10] ST SPEAr13xx: Adding support for SPEAr1310 Viresh Kumar
@ 2011-03-01 11:30 ` Viresh Kumar
2011-03-28 5:53 ` [PATCH V6 01/10 resend] SPEAr13xx: Add machine specific header files Viresh Kumar
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-01 11:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Vipin Kumar <vipin.kumar@st.com>
This patch adds padmux support for SPEAr1300 & SPEAr1310.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 198 +++++++++-
arch/arm/mach-spear13xx/spear1300.c | 17 +-
arch/arm/mach-spear13xx/spear1300_evb.c | 21 +-
arch/arm/mach-spear13xx/spear1310.c | 352 +++++++++++++++-
arch/arm/mach-spear13xx/spear1310_evb.c | 27 ++-
arch/arm/mach-spear13xx/spear13xx.c | 559 ++++++++++++++++++++++++
arch/arm/plat-spear/Makefile | 1 +
7 files changed, 1169 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 64feaa5..a75de93 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -19,6 +19,198 @@
#include <linux/amba/bus.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
+#include <plat/padmux.h>
+
+/*
+ * Function enable (Pad multiplexing register) offsets
+ */
+/* Pad multiplexing base */
+#define SPEAR13XX_FUNC_ENB_BASE UL(0xE0700650)
+#define SPEAR13XX_PCM_CFG_BASE UL(0xE0700100)
+
+#define PAD_MUX_CONFIG_REG_0 UL(0xE0700650)
+#define PAD_MUX_CONFIG_REG_1 UL(0xE0700654)
+#define PAD_MUX_CONFIG_REG_2 UL(0xE0700658)
+#define PAD_MUX_CONFIG_REG_3 UL(0xE070065C)
+
+#if defined(CONFIG_MACH_SPEAR1310)
+#define SPEAR1310_FUNC_CNTL_0 UL(0x6C800000)
+
+#define PMX_SMII_MASK (1 << 24) /* Func cntl reg0 */
+#define PMX_EGPIO7_MASK (1 << 2) /* Pcm cfg reg */
+#endif
+
+/* pad mux declarations */
+#define PMX_I2S1_MASK (1 << 3)
+#define PMX_I2S2_MASK (1 << 16) /* Offset 4 */
+#define PMX_CLCD1_MASK (1 << 5)
+#define PMX_CLCD2_MASK (1 << 3) /* Offset 4 */
+#define PMX_EGPIO00_MASK (1 << 6)
+#define PMX_EGPIO01_MASK (1 << 7)
+#define PMX_EGPIO02_MASK (1 << 8)
+#define PMX_EGPIO03_MASK (1 << 9)
+#define PMX_EGPIO04_MASK (1 << 10)
+#define PMX_EGPIO05_MASK (1 << 11)
+#define PMX_EGPIO06_MASK (1 << 12)
+#define PMX_EGPIO07_MASK (1 << 13)
+#define PMX_EGPIO08_MASK (1 << 14)
+#define PMX_EGPIO09_MASK (1 << 15)
+#define PMX_EGPIO10_MASK (1 << 5) /* Offset 4 */
+#define PMX_EGPIO11_MASK (1 << 6) /* Offset 4 */
+#define PMX_EGPIO12_MASK (1 << 7) /* Offset 4 */
+#define PMX_EGPIO13_MASK (1 << 8) /* Offset 4 */
+#define PMX_EGPIO14_MASK (1 << 9) /* Offset 4 */
+#define PMX_EGPIO15_MASK (1 << 10) /* Offset 4 */
+#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
+ PMX_EGPIO02_MASK | PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
+ PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | PMX_EGPIO07_MASK | \
+ PMX_EGPIO08_MASK | PMX_EGPIO09_MASK)
+#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
+ PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | PMX_EGPIO14_MASK | \
+ PMX_EGPIO15_MASK)
+
+#define PMX_SMI_MASK (1 << 16)
+#define PMX_SMINCS2_MASK (1 << 1) /* Offset 4 */
+#define PMX_SMINCS3_MASK (1 << 2) /* Offset 4 */
+
+#define PMX_GMIICLK_MASK (1 << 18)
+#define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
+#define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
+#define PMX_GMIID47_MASK (1 << 21)
+#define PMX_MDC_MDIO_MASK (1 << 22)
+
+#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
+ PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
+ PMX_RXCLK_RDV_TXEN_D03_MASK | PMX_GMIID47_MASK | \
+ PMX_MDC_MDIO_MASK)
+
+#define PMX_NAND8_MASK (1 << 17)
+#define PMX_NFAD023_MASK (1 << 24)
+#define PMX_NFAD24_MASK (1 << 25)
+#define PMX_NFAD25_MASK (1 << 26)
+#define PMX_NFWPRT1_MASK (1 << 24) /* Offset 4 */
+#define PMX_NFWPRT2_MASK (1 << 26) /* Offset 4 */
+#define PMX_NFWPRT3_MASK (1 << 28)
+#define PMX_NFRSTPWDWN0_MASK (1 << 29)
+#define PMX_NFRSTPWDWN1_MASK (1 << 30)
+#define PMX_NFRSTPWDWN2_MASK (1 << 31)
+#define PMX_NFRSTPWDWN3_MASK (1 << 0) /* Offset 4 */
+#define PMX_NFCE1_MASK (1 << 20) /* Offset 4 */
+#define PMX_NFCE2_MASK (1 << 22) /* Offset 4 */
+#define PMX_NFCE3_MASK (1 << 27)
+#define PMX_NFIO815_MASK (1 << 18) /* Offset 4 */
+
+#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD023_MASK | \
+ PMX_NFAD24_MASK | PMX_NFAD25_MASK | PMX_NFWPRT3_MASK | \
+ PMX_NFRSTPWDWN0_MASK | PMX_NFRSTPWDWN1_MASK | \
+ PMX_NFRSTPWDWN2_MASK | PMX_NFCE3_MASK)
+#define PMX_NAND8BIT_1_MASK (PMX_NFRSTPWDWN3_MASK)
+
+#define PMX_NAND8BIT4DEV_0_MASK (PMX_NAND8BIT_0_MASK)
+#define PMX_NAND8BIT4DEV_1_MASK (PMX_NAND8BIT_1_MASK | PMX_NFCE1_MASK | \
+ PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK)
+
+#define PMX_NAND16BIT_0_MASK (PMX_NAND8BIT_0_MASK)
+#define PMX_NAND16BIT_1_MASK (PMX_NAND8BIT_1_MASK | PMX_NFIO815_MASK)
+#define PMX_NAND16BIT4DEV_0_MASK (PMX_NAND8BIT4DEV_0_MASK)
+#define PMX_NAND16BIT4DEV_1_MASK (PMX_NAND8BIT4DEV_1_MASK | \
+ PMX_NFIO815_MASK)
+
+#define PMX_KBD_ROW0_MASK (1 << 25) /* Offset 4 */
+#define PMX_KBD_ROW1_MASK (1 << 23) /* Offset 4 */
+#define PMX_KBD_ROWCOL25_MASK (1 << 17) /* Offset 4 */
+#define PMX_KBD_ROWCOL68_MASK (1 << 4) /* Offset 4 */
+#define PMX_KBD_COL0_MASK (1 << 21) /* Offset 4 */
+#define PMX_KBD_COL1_MASK (1 << 19) /* Offset 4 */
+#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
+ PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
+
+#define PMX_UART0_MASK (1 << 1)
+#define PMX_I2C_MASK (1 << 2)
+#define PMX_SSP_MASK (1 << 4)
+#define PMX_UART0_MODEM_MASK (1 << 11) /* Offset 4 */
+#define PMX_GPT0_TMR1_MASK (1 << 12) /* Offset 4 */
+#define PMX_GPT0_TMR2_MASK (1 << 13) /* Offset 4 */
+#define PMX_GPT1_TMR1_MASK (1 << 14) /* Offset 4 */
+#define PMX_GPT1_TMR2_MASK (1 << 15) /* Offset 4 */
+
+#define PMX_MCIDATA0_MASK (1 << 27) /* Offset 4 */
+#define PMX_MCIDATA1_MASK (1 << 28) /* Offset 4 */
+#define PMX_MCIDATA2_MASK (1 << 29) /* Offset 4 */
+#define PMX_MCIDATA3_MASK (1 << 30) /* Offset 4 */
+#define PMX_MCIDATA4_MASK (1 << 31) /* Offset 4 */
+#define PMX_MCIDATA5_MASK (1 << 0) /* Offset 8 */
+#define PMX_MCIDATA6_MASK (1 << 1) /* Offset 8 */
+#define PMX_MCIDATA7_MASK (1 << 2) /* Offset 8 */
+#define PMX_MCIDATA1SD_MASK (1 << 3) /* Offset 8 */
+#define PMX_MCIDATA2SD_MASK (1 << 4) /* Offset 8 */
+#define PMX_MCIDATA3SD_MASK (1 << 5) /* Offset 8 */
+#define PMX_MCIADDR0ALE_MASK (1 << 6) /* Offset 8 */
+#define PMX_MCIADDR1CLECLK_MASK (1 << 7) /* Offset 8 */
+#define PMX_MCIADDR2_MASK (1 << 8) /* Offset 8 */
+#define PMX_MCICECF_MASK (1 << 9) /* Offset 8 */
+#define PMX_MCICEXD_MASK (1 << 10) /* Offset 8 */
+#define PMX_MCICESDMMC_MASK (1 << 11) /* Offset 8 */
+#define PMX_MCICDCF1_MASK (1 << 12) /* Offset 8 */
+#define PMX_MCICDCF2_MASK (1 << 13) /* Offset 8 */
+#define PMX_MCICDXD_MASK (1 << 14) /* Offset 8 */
+#define PMX_MCICDSDMMC_MASK (1 << 15) /* Offset 8 */
+#define PMX_MCIDATADIR_MASK (1 << 16) /* Offset 8 */
+#define PMX_MCIDMARQWP_MASK (1 << 17) /* Offset 8 */
+#define PMX_MCIIORDRE_MASK (1 << 18) /* Offset 8 */
+#define PMX_MCIIOWRWE_MASK (1 << 19) /* Offset 8 */
+#define PMX_MCIRESETCF_MASK (1 << 20) /* Offset 8 */
+#define PMX_MCICS0CE_MASK (1 << 21) /* Offset 8 */
+#define PMX_MCICFINTR_MASK (1 << 22) /* Offset 8 */
+#define PMX_MCIIORDY_MASK (1 << 23) /* Offset 8 */
+#define PMX_MCICS1_MASK (1 << 24) /* Offset 8 */
+#define PMX_MCIDMAACK_MASK (1 << 25) /* Offset 8 */
+#define PMX_MCISDCMD_MASK (1 << 26) /* Offset 8 */
+#define PMX_MCILEDS_MASK (1 << 27) /* Offset 8 */
+
+#define PMX_MCIFALL_1_MASK (0xF8000000)
+#define PMX_MCIFALL_2_MASK (0x0FFFFFFF)
+
+/* pad mux devices */
+extern struct pmx_dev pmx_i2c;
+extern struct pmx_dev pmx_ssp;
+extern struct pmx_dev pmx_i2s1;
+extern struct pmx_dev pmx_i2s2;
+extern struct pmx_dev pmx_clcd;
+extern struct pmx_dev pmx_clcd_hires;
+extern struct pmx_dev pmx_egpio_grp;
+extern struct pmx_dev pmx_smi_2_chips;
+extern struct pmx_dev pmx_smi_4_chips;
+extern struct pmx_dev pmx_gmii;
+extern struct pmx_dev pmx_nand_8bit;
+extern struct pmx_dev pmx_nand_16bit;
+extern struct pmx_dev pmx_keyboard_6x6;
+extern struct pmx_dev pmx_keyboard_9x9;
+extern struct pmx_dev pmx_uart0;
+extern struct pmx_dev pmx_uart0_modem;
+extern struct pmx_dev pmx_gpt_0_1;
+extern struct pmx_dev pmx_gpt_0_2;
+extern struct pmx_dev pmx_gpt_1_1;
+extern struct pmx_dev pmx_gpt_1_2;
+extern struct pmx_dev pmx_mcif;
+
+#if defined(CONFIG_MACH_SPEAR1310)
+extern struct pmx_dev pmx_uart1_modem;
+extern struct pmx_dev pmx_uart_1;
+extern struct pmx_dev pmx_uart_2;
+extern struct pmx_dev pmx_uart_3_4_5;
+extern struct pmx_dev pmx_rs485_hdlc_1_2;
+extern struct pmx_dev pmx_tdm_hdlc_1_2;
+extern struct pmx_dev pmx_nand32bit;
+extern struct pmx_dev pmx_fsmc16bit_4_chips;
+extern struct pmx_dev pmx_fsmc32bit_4_chips;
+extern struct pmx_dev pmx_gmii1;
+extern struct pmx_dev pmx_rgmii;
+extern struct pmx_dev pmx_i2c1;
+extern struct pmx_dev pmx_smii_0_1_2;
+extern struct pmx_dev pmx_can;
+extern struct pmx_dev pmx_uart1_modem;
+#endif
/*
* Each GPT has 2 timer channels
@@ -43,7 +235,8 @@ void spear13xx_secondary_startup(void);
/* spear1300 declarations */
#ifdef CONFIG_MACH_SPEAR1300
/* Add spear1300 machine function declarations here */
-void __init spear1300_init(void);
+void __init spear1300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR1300 */
@@ -59,7 +252,8 @@ extern struct platform_device spear1310_can0_device;
extern struct platform_device spear1310_can1_device;
/* Add spear1310 machine function declarations here */
-void __init spear1310_init(void);
+void __init spear1310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
void __init spear1310_map_io(void);
#endif /* CONFIG_MACH_SPEAR1310 */
diff --git a/arch/arm/mach-spear13xx/spear1300.c b/arch/arm/mach-spear13xx/spear1300.c
index 9c38bec..c0f1743 100644
--- a/arch/arm/mach-spear13xx/spear1300.c
+++ b/arch/arm/mach-spear13xx/spear1300.c
@@ -14,10 +14,25 @@
#include <mach/generic.h>
#include <mach/hardware.h>
+/* pmx driver structure */
+static struct pmx_driver pmx_driver;
+
/* Add spear1300 specific devices here */
-void __init spear1300_init(void)
+void __init spear1300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
+ int ret;
+
/* call spear13xx family common init function */
spear13xx_init();
+
+ /* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registeration failed. err no: %d\n", ret);
}
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index c95c141..2e966cf 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -17,6 +17,25 @@
#include <mach/generic.h>
#include <mach/hardware.h>
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+ /* spear13xx specific devices */
+ &pmx_i2c,
+ &pmx_i2s1,
+ &pmx_i2s2,
+ &pmx_clcd,
+ &pmx_egpio_grp,
+ &pmx_gmii,
+ &pmx_keyboard_6x6,
+ &pmx_mcif,
+ &pmx_nand_8bit,
+ &pmx_smi_4_chips,
+ &pmx_ssp,
+ &pmx_uart0,
+
+ /* spear1300 specific devices */
+};
+
static struct amba_device *amba_devs[] __initdata = {
&spear13xx_uart_device,
};
@@ -29,7 +48,7 @@ static void __init spear1300_evb_init(void)
unsigned int i;
/* call spear1300 machine init function */
- spear1300_init();
+ spear1300_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index e4ad092..21ec388 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -17,6 +17,344 @@
#include <mach/generic.h>
#include <mach/hardware.h>
+/* pmx driver structure */
+static struct pmx_driver pmx_driver;
+
+/* Pad multiplexing for uart1_modem device */
+static struct pmx_mux_reg pmx_uart1_modem_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_I2S1_MASK | PMX_SSP_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
+ {
+ .mux_regs = pmx_uart1_modem_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart1_modem_mux),
+ },
+};
+
+struct pmx_dev pmx_uart1_modem = {
+ .name = "uart1_modem",
+ .modes = pmx_uart1_modem_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
+};
+
+/* Pad multiplexing for uart1 device */
+static struct pmx_mux_reg pmx_uart1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SSP_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart1_modes[] = {
+ {
+ .mux_regs = pmx_uart1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart1_mux),
+ },
+};
+
+struct pmx_dev pmx_uart_1 = {
+ .name = "uart1",
+ .modes = pmx_uart1_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart1_modes),
+};
+
+/* Pad multiplexing for uart2 device */
+static struct pmx_mux_reg pmx_uart2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SSP_MASK | PMX_CLCD1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart2_modes[] = {
+ {
+ .mux_regs = pmx_uart2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart2_mux),
+ },
+};
+
+struct pmx_dev pmx_uart_2 = {
+ .name = "uart2",
+ .modes = pmx_uart2_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart2_modes),
+};
+
+/* Pad multiplexing for uart_3_4_5 device */
+static struct pmx_mux_reg pmx_uart_3_4_5_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart_3_4_5_modes[] = {
+ {
+ .mux_regs = pmx_uart_3_4_5_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart_3_4_5_mux),
+ },
+};
+
+struct pmx_dev pmx_uart_3_4_5 = {
+ .name = "uart_3_4_5",
+ .modes = pmx_uart_3_4_5_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart_3_4_5_modes),
+};
+
+/* Pad multiplexing for rs485_hdlc_1_2 device */
+static struct pmx_mux_reg pmx_rs485_hdlc_1_2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_rs485_hdlc_1_2_modes[] = {
+ {
+ .mux_regs = pmx_rs485_hdlc_1_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_rs485_hdlc_1_2_mux),
+ },
+};
+
+struct pmx_dev pmx_rs485_hdlc_1_2 = {
+ .name = "rs485_hdlc_1_2",
+ .modes = pmx_rs485_hdlc_1_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_rs485_hdlc_1_2_modes),
+};
+
+/* Pad multiplexing for tdm_hdlc_1_2 device */
+static struct pmx_mux_reg pmx_tdm_hdlc_1_2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_tdm_hdlc_1_2_modes[] = {
+ {
+ .mux_regs = pmx_tdm_hdlc_1_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_tdm_hdlc_1_2_mux),
+ },
+};
+
+struct pmx_dev pmx_tdm_hdlc_1_2 = {
+ .name = "tdm_hdlc_1_2",
+ .modes = pmx_tdm_hdlc_1_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_tdm_hdlc_1_2_modes),
+};
+
+/* Pad multiplexing for fsmc32bit device */
+static struct pmx_mux_reg pmx_fsmc32bit_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_EGPIO_0_GRP_MASK | PMX_SMI_MASK | \
+ PMX_NAND16BIT4DEV_0_MASK | PMX_CLCD1_MASK,
+ .value = 0,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_KEYBOARD_6X6_MASK | PMX_NAND16BIT4DEV_1_MASK,
+ .value = 0,
+ }, {
+ .address = SPEAR13XX_PCM_CFG_BASE,
+ .mask = PMX_EGPIO7_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_fsmc32bit_modes[] = {
+ {
+ .mux_regs = pmx_fsmc32bit_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_fsmc32bit_mux),
+ },
+};
+
+struct pmx_dev pmx_fsmc32bit_4_chips = {
+ .name = "fsmc32bit",
+ .modes = pmx_fsmc32bit_modes,
+ .mode_count = ARRAY_SIZE(pmx_fsmc32bit_modes),
+};
+
+/* Pad multiplexing for fsmc16bit device */
+static struct pmx_mux_reg pmx_fsmc16bit_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND16BIT4DEV_0_MASK,
+ .value = 0,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_KEYBOARD_6X6_MASK | PMX_NAND16BIT4DEV_1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_fsmc16bit_modes[] = {
+ {
+ .mux_regs = pmx_fsmc16bit_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_fsmc16bit_mux),
+ },
+};
+
+struct pmx_dev pmx_fsmc16bit_4_chips = {
+ .name = "fsmc16bit",
+ .modes = pmx_fsmc16bit_modes,
+ .mode_count = ARRAY_SIZE(pmx_fsmc16bit_modes),
+};
+
+/* Pad multiplexing for gmii1 device */
+static struct pmx_mux_reg pmx_gmii1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_GMII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_gmii1_modes[] = {
+ {
+ .mux_regs = pmx_gmii1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gmii1_mux),
+ },
+};
+
+struct pmx_dev pmx_gmii1 = {
+ .name = "gmii1",
+ .modes = pmx_gmii1_modes,
+ .mode_count = ARRAY_SIZE(pmx_gmii1_modes),
+};
+
+/* Pad multiplexing for rgmii device */
+static struct pmx_mux_reg pmx_rgmii_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_GMII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_rgmii_modes[] = {
+ {
+ .mux_regs = pmx_rgmii_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_rgmii_mux),
+ },
+};
+
+struct pmx_dev pmx_rgmii = {
+ .name = "rgmii",
+ .modes = pmx_rgmii_modes,
+ .mode_count = ARRAY_SIZE(pmx_rgmii_modes),
+};
+
+/* Pad multiplexing for i2c1 device */
+static struct pmx_mux_reg pmx_i2c1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2c1_modes[] = {
+ {
+ .mux_regs = pmx_i2c1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2c1_mux),
+ },
+};
+
+struct pmx_dev pmx_i2c1 = {
+ .name = "i2c1",
+ .modes = pmx_i2c1_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
+};
+
+/* Pad multiplexing for smii_0_1_2 device */
+static struct pmx_mux_reg pmx_smii_0_1_2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
+ PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR1_MASK | \
+ PMX_GPT0_TMR2_MASK | PMX_GPT1_TMR1_MASK | \
+ PMX_GPT1_TMR2_MASK,
+ .value = 0,
+ }, {
+ .address = SPEAR1310_FUNC_CNTL_0,
+ .mask = PMX_SMII_MASK,
+ .value = PMX_SMII_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_smii_0_1_2_modes[] = {
+ {
+ .mux_regs = pmx_smii_0_1_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_smii_0_1_2_mux),
+ },
+};
+
+struct pmx_dev pmx_smii_0_1_2 = {
+ .name = "smii_0_1_2",
+ .modes = pmx_smii_0_1_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_smii_0_1_2_modes),
+};
+
+/* Pad multiplexing for pci1 device */
+static struct pmx_mux_reg pmx_pci1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
+ PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR1_MASK | \
+ PMX_GPT0_TMR2_MASK | PMX_GPT1_TMR1_MASK | \
+ PMX_GPT1_TMR2_MASK,
+ .value = 0,
+ }, {
+ .address = SPEAR1310_FUNC_CNTL_0,
+ .mask = PMX_SMII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_pci1_modes[] = {
+ {
+ .mux_regs = pmx_pci1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_pci1_mux),
+ },
+};
+
+struct pmx_dev pmx_pci1 = {
+ .name = "pci1",
+ .modes = pmx_pci1_modes,
+ .mode_count = ARRAY_SIZE(pmx_pci1_modes),
+};
+
+/* Pad multiplexing for can device */
+static struct pmx_mux_reg pmx_can_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_I2S2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_can_modes[] = {
+ {
+ .mux_regs = pmx_can_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_can_mux),
+ },
+};
+
+struct pmx_dev pmx_can = {
+ .name = "can",
+ .modes = pmx_can_modes,
+ .mode_count = ARRAY_SIZE(pmx_can_modes),
+};
+
/* Add spear1310 specific devices here */
/* uart1 device registeration */
struct amba_device spear1310_uart1_device = {
@@ -137,8 +475,20 @@ void __init spear1310_map_io(void)
spear13xx_map_io();
}
-void __init spear1310_init(void)
+void __init spear1310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
+ int ret;
+
/* call spear13xx family common init function */
spear13xx_init();
+
+ /* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registeration failed. err no: %d\n", ret);
}
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
index a87e82b..42625c8 100644
--- a/arch/arm/mach-spear13xx/spear1310_evb.c
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -17,6 +17,31 @@
#include <mach/generic.h>
#include <mach/hardware.h>
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+ /* spear13xx specific devices */
+ &pmx_i2c,
+ &pmx_i2s1,
+ &pmx_egpio_grp,
+ &pmx_gmii,
+ &pmx_keyboard_6x6,
+ &pmx_mcif,
+ &pmx_nand_8bit,
+ &pmx_smi_2_chips,
+ &pmx_uart0,
+
+ /* spear1310 specific devices */
+ &pmx_can,
+ &pmx_i2c1,
+ &pmx_smii_0_1_2,
+ &pmx_fsmc16bit_4_chips,
+ &pmx_rs485_hdlc_1_2,
+ &pmx_tdm_hdlc_1_2,
+ &pmx_uart_1,
+ &pmx_uart_2,
+ &pmx_uart_3_4_5,
+};
+
static struct amba_device *amba_devs[] __initdata = {
/* spear13xx specific devices */
&spear13xx_uart_device,
@@ -42,7 +67,7 @@ static void __init spear1310_evb_init(void)
unsigned int i;
/* call spear1310 machine init function */
- spear1310_init();
+ spear1310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index b5da555..7832c1a 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -136,3 +136,562 @@ static void __init spear13xx_timer_init(void)
struct sys_timer spear13xx_timer = {
.init = spear13xx_timer_init,
};
+
+/* pad multiplexing support */
+/* devices */
+
+/* Pad multiplexing for i2c device */
+static struct pmx_mux_reg pmx_i2c_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_I2C_MASK,
+ .value = PMX_I2C_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2c_modes[] = {
+ {
+ .mux_regs = pmx_i2c_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2c_mux),
+ },
+};
+
+struct pmx_dev pmx_i2c = {
+ .name = "i2c",
+ .modes = pmx_i2c_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2c_modes),
+};
+
+/* Pad multiplexing for ssp device */
+static struct pmx_mux_reg pmx_ssp_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SSP_MASK,
+ .value = PMX_SSP_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_ssp_modes[] = {
+ {
+ .mux_regs = pmx_ssp_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_ssp_mux),
+ },
+};
+
+struct pmx_dev pmx_ssp = {
+ .name = "ssp",
+ .modes = pmx_ssp_modes,
+ .mode_count = ARRAY_SIZE(pmx_ssp_modes),
+};
+
+/* Pad multiplexing for i2s1 device */
+static struct pmx_mux_reg pmx_i2s1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_I2S1_MASK,
+ .value = PMX_I2S1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2s1_modes[] = {
+ {
+ .mux_regs = pmx_i2s1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2s1_mux),
+ },
+};
+
+struct pmx_dev pmx_i2s1 = {
+ .name = "i2s1",
+ .modes = pmx_i2s1_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2s1_modes),
+};
+
+/* Pad multiplexing for i2s2 device */
+static struct pmx_mux_reg pmx_i2s2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_I2S2_MASK,
+ .value = PMX_I2S2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2s2_modes[] = {
+ {
+ .mux_regs = pmx_i2s2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2s2_mux),
+ },
+};
+
+struct pmx_dev pmx_i2s2 = {
+ .name = "i2s2",
+ .modes = pmx_i2s2_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2s2_modes),
+};
+
+/* Pad multiplexing for clcd device */
+static struct pmx_mux_reg pmx_clcd_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = PMX_CLCD1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_clcd_modes[] = {
+ {
+ .mux_regs = pmx_clcd_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_clcd_mux),
+ },
+};
+
+struct pmx_dev pmx_clcd = {
+ .name = "clcd",
+ .modes = pmx_clcd_modes,
+ .mode_count = ARRAY_SIZE(pmx_clcd_modes),
+};
+
+/* Pad multiplexing for clcd_hires device */
+static struct pmx_mux_reg pmx_clcd_hires_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = PMX_CLCD1_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_CLCD2_MASK,
+ .value = PMX_CLCD2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_clcd_hires_modes[] = {
+ {
+ .mux_regs = pmx_clcd_hires_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_clcd_hires_mux),
+ },
+};
+
+struct pmx_dev pmx_clcd_hires = {
+ .name = "clcd_high_res",
+ .modes = pmx_clcd_hires_modes,
+ .mode_count = ARRAY_SIZE(pmx_clcd_hires_modes),
+};
+
+/*
+ * By default, all EGPIOs are enabled.
+ * TBD : Board specific enabling of specific GPIOs only
+ */
+static struct pmx_mux_reg pmx_egpio_grp_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_EGPIO_0_GRP_MASK,
+ .value = PMX_EGPIO_0_GRP_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_EGPIO_1_GRP_MASK,
+ .value = PMX_EGPIO_1_GRP_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_egpio_grp_modes[] = {
+ {
+ .mux_regs = pmx_egpio_grp_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_egpio_grp_mux),
+ },
+};
+
+struct pmx_dev pmx_egpio_grp = {
+ .name = "egpios",
+ .modes = pmx_egpio_grp_modes,
+ .mode_count = ARRAY_SIZE(pmx_egpio_grp_modes),
+};
+
+/* Pad multiplexing for smi 2 chips device */
+static struct pmx_mux_reg pmx_smi_2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SMI_MASK,
+ .value = PMX_SMI_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_smi_2_modes[] = {
+ {
+ .mux_regs = pmx_smi_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_smi_2_mux),
+ },
+};
+
+struct pmx_dev pmx_smi_2_chips = {
+ .name = "smi_2_chips",
+ .modes = pmx_smi_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_smi_2_modes),
+};
+
+/* Pad multiplexing for smi 4 chips device */
+static struct pmx_mux_reg pmx_smi_4_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SMI_MASK,
+ .value = PMX_SMI_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+ .value = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_smi_4_modes[] = {
+ {
+ .mux_regs = pmx_smi_4_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_smi_4_mux),
+ },
+};
+
+struct pmx_dev pmx_smi_4_chips = {
+ .name = "smi_4_chips",
+ .modes = pmx_smi_4_modes,
+ .mode_count = ARRAY_SIZE(pmx_smi_4_modes),
+};
+
+/* Pad multiplexing for gmii device */
+static struct pmx_mux_reg pmx_gmii_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_GMII_MASK,
+ .value = PMX_GMII_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gmii_modes[] = {
+ {
+ .mux_regs = pmx_gmii_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gmii_mux),
+ },
+};
+
+struct pmx_dev pmx_gmii = {
+ .name = "gmii",
+ .modes = pmx_gmii_modes,
+ .mode_count = ARRAY_SIZE(pmx_gmii_modes),
+};
+
+/* Pad multiplexing for nand 8bit (4 chips) */
+static struct pmx_mux_reg pmx_nand8_4_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND8BIT4DEV_0_MASK,
+ .value = PMX_NAND8BIT4DEV_0_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND8BIT4DEV_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_NAND8BIT4DEV_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_nand8_4_modes[] = {
+ {
+ .mux_regs = pmx_nand8_4_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_nand8_4_mux),
+ },
+};
+
+struct pmx_dev pmx_nand_8bit_4_chips = {
+ .name = "nand-8bit_4_chips",
+ .modes = pmx_nand8_4_modes,
+ .mode_count = ARRAY_SIZE(pmx_nand8_4_modes),
+};
+
+/* Pad multiplexing for nand 8bit device (cs0 only) */
+static struct pmx_mux_reg pmx_nand8_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND8BIT_0_MASK,
+ .value = PMX_NAND8BIT_0_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND8BIT_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_NAND8BIT_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_nand8_modes[] = {
+ {
+ .mux_regs = pmx_nand8_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_nand8_mux),
+ },
+};
+
+struct pmx_dev pmx_nand_8bit = {
+ .name = "nand-8bit",
+ .modes = pmx_nand8_modes,
+ .mode_count = ARRAY_SIZE(pmx_nand8_modes),
+};
+
+/*
+ * Pad multiplexing for nand 16bit device
+ * Note : Enabling pmx_nand_16bit means that all the required pads for
+ * 16bit nand device operations are enabled. These also include pads
+ * for 8bit devices
+ */
+static struct pmx_mux_reg pmx_nand16_4_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND16BIT4DEV_0_MASK,
+ .value = PMX_NAND16BIT4DEV_0_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND16BIT4DEV_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_NAND16BIT4DEV_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_nand16_4_modes[] = {
+ {
+ .mux_regs = pmx_nand16_4_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_nand16_4_mux),
+ },
+};
+
+struct pmx_dev pmx_nand_16bit_4_chips = {
+ .name = "nand-16bit_4_chips",
+ .modes = pmx_nand16_4_modes,
+ .mode_count = ARRAY_SIZE(pmx_nand16_4_modes),
+};
+
+/* Pad multiplexing for nand 16bit device (cs0 only) */
+static struct pmx_mux_reg pmx_nand16_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND16BIT_0_MASK,
+ .value = PMX_NAND16BIT_0_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND16BIT_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_NAND16BIT_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_nand16_modes[] = {
+ {
+ .mux_regs = pmx_nand16_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_nand16_mux),
+ },
+};
+
+struct pmx_dev pmx_nand_16bit = {
+ .name = "nand-16bit",
+ .modes = pmx_nand16_modes,
+ .mode_count = ARRAY_SIZE(pmx_nand16_modes),
+};
+
+/* Pad multiplexing for keyboard_6x6 device */
+static struct pmx_mux_reg pmx_keyboard_6x6_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_KEYBOARD_6X6_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NFIO815_MASK | PMX_NFCE1_MASK | \
+ PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_keyboard_6x6_modes[] = {
+ {
+ .mux_regs = pmx_keyboard_6x6_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_keyboard_6x6_mux),
+ },
+};
+
+struct pmx_dev pmx_keyboard_6x6 = {
+ .name = "keyboard_6x6",
+ .modes = pmx_keyboard_6x6_modes,
+ .mode_count = ARRAY_SIZE(pmx_keyboard_6x6_modes),
+};
+
+/* Pad multiplexing for keyboard_9x9 device */
+static struct pmx_mux_reg pmx_keyboard_9x9_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_KEYBOARD_6X6_MASK | PMX_KBD_ROWCOL68_MASK,
+ .value = PMX_KEYBOARD_6X6_MASK | PMX_KBD_ROWCOL68_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NFIO815_MASK | PMX_NFCE1_MASK | \
+ PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_keyboard_9x9_modes[] = {
+ {
+ .mux_regs = pmx_keyboard_9x9_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_keyboard_9x9_mux),
+ },
+};
+
+struct pmx_dev pmx_keyboard_9x9 = {
+ .name = "keyboard_9x9",
+ .modes = pmx_keyboard_9x9_modes,
+ .mode_count = ARRAY_SIZE(pmx_keyboard_9x9_modes),
+};
+
+/* Pad multiplexing for uart0 device */
+static struct pmx_mux_reg pmx_uart0_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_UART0_MASK,
+ .value = PMX_UART0_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart0_modes[] = {
+ {
+ .mux_regs = pmx_uart0_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart0_mux),
+ },
+};
+
+struct pmx_dev pmx_uart0 = {
+ .name = "uart0",
+ .modes = pmx_uart0_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart0_modes),
+};
+
+/* Pad multiplexing for uart0_modem device */
+static struct pmx_mux_reg pmx_uart0_modem_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_UART0_MODEM_MASK,
+ .value = PMX_UART0_MODEM_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
+ {
+ .mux_regs = pmx_uart0_modem_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart0_modem_mux),
+ },
+};
+
+struct pmx_dev pmx_uart0_modem = {
+ .name = "uart0_modem",
+ .modes = pmx_uart0_modem_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
+};
+
+/* Pad multiplexing for gpt_0_1 device */
+static struct pmx_mux_reg pmx_gpt_0_1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_GPT0_TMR1_MASK,
+ .value = PMX_GPT0_TMR1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpt_0_1_modes[] = {
+ {
+ .mux_regs = pmx_gpt_0_1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpt_0_1_mux),
+ },
+};
+
+struct pmx_dev pmx_gpt_0_1 = {
+ .name = "gpt_0_1",
+ .modes = pmx_gpt_0_1_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpt_0_1_modes),
+};
+
+/* Pad multiplexing for gpt_0_2 device */
+static struct pmx_mux_reg pmx_gpt_0_2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_GPT0_TMR2_MASK,
+ .value = PMX_GPT0_TMR2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpt_0_2_modes[] = {
+ {
+ .mux_regs = pmx_gpt_0_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpt_0_2_mux),
+ },
+};
+
+struct pmx_dev pmx_gpt_0_2 = {
+ .name = "gpt_0_2",
+ .modes = pmx_gpt_0_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpt_0_2_modes),
+};
+
+/* Pad multiplexing for gpt_1_1 device */
+static struct pmx_mux_reg pmx_gpt_1_1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_GPT1_TMR1_MASK,
+ .value = PMX_GPT1_TMR1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpt_1_1_modes[] = {
+ {
+ .mux_regs = pmx_gpt_1_1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpt_1_1_mux),
+ },
+};
+
+struct pmx_dev pmx_gpt_1_1 = {
+ .name = "gpt_1_1",
+ .modes = pmx_gpt_1_1_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpt_1_1_modes),
+};
+
+/* Pad multiplexing for gpt_1_2 device */
+static struct pmx_mux_reg pmx_gpt_1_2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_GPT1_TMR2_MASK,
+ .value = PMX_GPT1_TMR2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpt_1_2_modes[] = {
+ {
+ .mux_regs = pmx_gpt_1_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpt_1_2_mux),
+ },
+};
+
+struct pmx_dev pmx_gpt_1_2 = {
+ .name = "gpt_1_2",
+ .modes = pmx_gpt_1_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpt_1_2_modes),
+};
+
+/* Pad multiplexing for mcif device */
+static struct pmx_mux_reg pmx_mcif_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_MCIFALL_1_MASK,
+ .value = PMX_MCIFALL_1_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_2,
+ .mask = PMX_MCIFALL_2_MASK,
+ .value = PMX_MCIFALL_2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_mcif_modes[] = {
+ {
+ .mux_regs = pmx_mcif_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_mcif_mux),
+ },
+};
+
+struct pmx_dev pmx_mcif = {
+ .name = "mcif",
+ .modes = pmx_mcif_modes,
+ .mode_count = ARRAY_SIZE(pmx_mcif_modes),
+};
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index b4f340b..03f9acc 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -5,4 +5,5 @@
# Common support
obj-y := clock.o time.o
+obj-$(CONFIG_ARCH_SPEAR13XX) += padmux.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 01/10 resend] SPEAr13xx: Add machine specific header files
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (9 preceding siblings ...)
2011-03-01 11:30 ` [PATCH V6 10/10] ST SPEAr13xx: Add padmux support Viresh Kumar
@ 2011-03-28 5:53 ` Viresh Kumar
2011-03-28 5:53 ` [PATCH V6 02/10 resend] SPEAr13xx: Add machine specific src files Viresh Kumar
2011-05-27 6:15 ` [PATCH V6 00/10] Adding SPEAr13xx support viresh kumar
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-28 5:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Changes in V6 resend:
- misc register definitions are fixed & updated in misc_regs.h
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/clkdev.h | 19 +
arch/arm/mach-spear13xx/include/mach/debug-macro.S | 14 +
arch/arm/mach-spear13xx/include/mach/entry-macro.S | 22 +
arch/arm/mach-spear13xx/include/mach/generic.h | 50 +++
arch/arm/mach-spear13xx/include/mach/gpio.h | 19 +
arch/arm/mach-spear13xx/include/mach/hardware.h | 31 ++
arch/arm/mach-spear13xx/include/mach/io.h | 19 +
arch/arm/mach-spear13xx/include/mach/irqs.h | 91 +++++
arch/arm/mach-spear13xx/include/mach/memory.h | 19 +
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 424 ++++++++++++++++++++
arch/arm/mach-spear13xx/include/mach/smp.h | 25 ++
arch/arm/mach-spear13xx/include/mach/spear.h | 94 +++++
arch/arm/mach-spear13xx/include/mach/spear1300.h | 21 +
arch/arm/mach-spear13xx/include/mach/system.h | 35 ++
arch/arm/mach-spear13xx/include/mach/timex.h | 19 +
arch/arm/mach-spear13xx/include/mach/uncompress.h | 19 +
arch/arm/mach-spear13xx/include/mach/vmalloc.h | 18 +
17 files changed, 939 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/io.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/memory.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/smp.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1300.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/vmalloc.h
diff --git a/arch/arm/mach-spear13xx/include/mach/clkdev.h b/arch/arm/mach-spear13xx/include/mach/clkdev.h
new file mode 100644
index 0000000..effdb81
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/clkdev.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/clkdev.h
+ *
+ * Clock Dev framework definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+#include <plat/clkdev.h>
+
+#endif /* __MACH_CLKDEV_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
new file mode 100644
index 0000000..3933edc
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header spear13xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/entry-macro.S b/arch/arm/mach-spear13xx/include/mach/entry-macro.S
new file mode 100644
index 0000000..5257929
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/entry-macro.S
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * Copy of RealView platform implementation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/hardware/entry-macro-gic.S>
+#include <mach/hardware.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
new file mode 100644
index 0000000..95011a2
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/generic.h
+ *
+ * spear13xx machine family generic header file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GENERIC_H
+#define __MACH_GENERIC_H
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+/*
+ * Each GPT has 2 timer channels
+ * Following GPT channels will be used as clock source and clockevent
+ */
+#define SPEAR_GPT0_BASE SPEAR13XX_GPT0_BASE
+#define SPEAR_GPT0_CHAN0_IRQ IRQ_GPT0_TMR0
+#define SPEAR_GPT0_CHAN1_IRQ IRQ_GPT0_TMR1
+
+/* Add spear13xx family device structure declarations here */
+extern struct amba_device spear13xx_uart_device;
+extern struct sys_timer spear13xx_timer;
+
+/* Add spear13xx family function declarations here */
+void __init clk_init(void);
+void __init spear_setup_timer(void);
+void __init spear13xx_map_io(void);
+void __init spear13xx_init_irq(void);
+void __init spear13xx_init(void);
+void spear13xx_secondary_startup(void);
+
+/* spear1300 declarations */
+#ifdef CONFIG_MACH_SPEAR1300
+/* Add spear1300 machine function declarations here */
+void __init spear1300_init(void);
+
+#endif /* CONFIG_MACH_SPEAR1300 */
+
+#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
new file mode 100644
index 0000000..43fa541
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/gpio.h
+ *
+ * GPIO macros for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
new file mode 100644
index 0000000..fd8c2dc
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/hardware.h
+ *
+ * Hardware definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+#include <plat/hardware.h>
+#include <mach/spear.h>
+
+/* Vitual to physical translation of statically mapped space */
+/*
+ * if phy_addr is 0x8...,.... and above then map it to 0xF...,....
+ * else map it to 0xE...,....
+ */
+
+#define IO_ADDRESS(x) ((x) | ((((x) >> 31) << 28) | 0xE0000000))
+
+/* typesafe io address */
+#define __io_address(n) __io(IO_ADDRESS(n))
+
+#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/io.h b/arch/arm/mach-spear13xx/include/mach/io.h
new file mode 100644
index 0000000..2fe3503
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/io.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/io.h
+ *
+ * IO definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#include <plat/io.h>
+
+#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
new file mode 100644
index 0000000..d9fe051
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/irqs.h
+ *
+ * IRQ helper macros for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+/* IRQ definitions */
+/*
+ * SGI : ID0 - ID15
+ * PPI : ID16 - ID31
+ * SHPI : ID32 - ID224
+ */
+
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
+
+/* Shared Peripheral Interrupt (SHPI) */
+#define IRQ_SHPI_START 32
+
+#define IRQ_PLAY_I2S2 (IRQ_SHPI_START + 10)
+#define IRQ_REC_I2S2 (IRQ_SHPI_START + 11)
+#define IRQ_ADC (IRQ_SHPI_START + 12)
+#define IRQ_CLCD (IRQ_SHPI_START + 13)
+#define IRQ_DMAC0_FLAG_0 (IRQ_SHPI_START + 14)
+#define IRQ_DMAC0_FLAG_1 (IRQ_SHPI_START + 15)
+#define IRQ_DMAC0_FLAG_2 (IRQ_SHPI_START + 16)
+#define IRQ_DMAC0_FLAG_3 (IRQ_SHPI_START + 17)
+#define IRQ_DMAC0_FLAG_4 (IRQ_SHPI_START + 18)
+#define IRQ_DMAC0_COMBINED (IRQ_SHPI_START + 19)
+#define IRQ_FSMC0 (IRQ_SHPI_START + 20)
+#define IRQ_FSMC1 (IRQ_SHPI_START + 21)
+#define IRQ_FSMC2 (IRQ_SHPI_START + 22)
+#define IRQ_FSMC3 (IRQ_SHPI_START + 23)
+#define IRQ_GPIO0 (IRQ_SHPI_START + 24)
+#define IRQ_GPIO1 (IRQ_SHPI_START + 25)
+#define IRQ_PLAY_I2S1 (IRQ_SHPI_START + 26)
+#define IRQ_JPEG (IRQ_SHPI_START + 27)
+#define IRQ_SDHCI (IRQ_SHPI_START + 28)
+#define IRQ_CF (IRQ_SHPI_START + 29)
+#define IRQ_SMI (IRQ_SHPI_START + 30)
+#define IRQ_SSP (IRQ_SHPI_START + 31)
+#define IRQ_C3 (IRQ_SHPI_START + 32)
+#define IRQ_GMAC_1 (IRQ_SHPI_START + 33)
+#define IRQ_GMAC_2 (IRQ_SHPI_START + 34)
+#define IRQ_UART (IRQ_SHPI_START + 35)
+#define IRQ_RTC (IRQ_SHPI_START + 36)
+#define IRQ_GPT0_TMR0 (IRQ_SHPI_START + 37)
+#define IRQ_GPT0_TMR1 (IRQ_SHPI_START + 38)
+#define IRQ_GPT1_TMR0 (IRQ_SHPI_START + 39)
+#define IRQ_GPT1_TMR1 (IRQ_SHPI_START + 40)
+#define IRQ_I2C (IRQ_SHPI_START + 41)
+#define IRQ_GPT2_TMR0 (IRQ_SHPI_START + 42)
+#define IRQ_GPT2_TMR1 (IRQ_SHPI_START + 43)
+#define IRQ_GPT3_TMR0 (IRQ_SHPI_START + 44)
+#define IRQ_GPT3_TMR1 (IRQ_SHPI_START + 45)
+
+#define IRQ_JPEG_RME (IRQ_SHPI_START + 52)
+#define IRQ_KBD (IRQ_SHPI_START + 52)
+#define IRQ_REC_I2S1 (IRQ_SHPI_START + 53)
+#define IRQ_DMAC1_FLAG_0 (IRQ_SHPI_START + 54)
+#define IRQ_DMAC1_FLAG_1 (IRQ_SHPI_START + 55)
+#define IRQ_DMAC1_FLAG_2 (IRQ_SHPI_START + 56)
+#define IRQ_DMAC1_FLAG_3 (IRQ_SHPI_START + 57)
+#define IRQ_DMAC1_FLAG_4 (IRQ_SHPI_START + 58)
+#define IRQ_DMAC1_COMBINED (IRQ_SHPI_START + 59)
+
+#define IRQ_UDC (IRQ_SHPI_START + 62)
+#define IRQ_UPD (IRQ_SHPI_START + 63)
+#define IRQ_USBH_EHCI0 (IRQ_SHPI_START + 64)
+#define IRQ_USBH_OHCI0 (IRQ_SHPI_START + 65)
+#define IRQ_USBH_EHCI1 (IRQ_SHPI_START + 66)
+#define IRQ_USBH_OHCI1 (IRQ_SHPI_START + 67)
+#define IRQ_PCIE0 (IRQ_SHPI_START + 68)
+#define IRQ_PCIE1 (IRQ_SHPI_START + 69)
+#define IRQ_PCIE2 (IRQ_SHPI_START + 70)
+
+#define IRQ_GIC_END (IRQ_SHPI_START + 128)
+
+#define NR_IRQS IRQ_GIC_END
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/memory.h b/arch/arm/mach-spear13xx/include/mach/memory.h
new file mode 100644
index 0000000..200257c
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/memory.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/memory.h
+ *
+ * Memory map for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+#include <plat/memory.h>
+
+#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/misc_regs.h b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
new file mode 100644
index 0000000..1811b27
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
@@ -0,0 +1,424 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/misc_regs.h
+ *
+ * Miscellaneous registers definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MISC_REGS_H
+#define __MACH_MISC_REGS_H
+
+#include <mach/hardware.h>
+
+#define MISC_BASE IOMEM(VA_SPEAR13XX_MISC_BASE)
+
+/* General Configuration */
+#define SOC_CFG (MISC_BASE + 0x000)
+#define BOOTSTRAP_CFG (MISC_BASE + 0x004)
+
+/* Power Management Registers */
+#define PCM_CFG (MISC_BASE + 0x100)
+#define PCM_WKUP_CFG (MISC_BASE + 0x104)
+#define SWITCH_CTR (MISC_BASE + 0x108)
+
+/* Clock Configuration Registers */
+#define SYS_CLK_CTRL (MISC_BASE + 0x200)
+#define SYS_SW_RES (MISC_BASE + 0x204)
+#define SYS_CLK_PLLTIMER (MISC_BASE + 0x208)
+#define SYS_CLK_OSCITIMER (MISC_BASE + 0x20C)
+
+/* PLL related registers and bit values */
+#define PLL_CFG (MISC_BASE + 0x210)
+ /* PLL_CFG bit values */
+ #define CLCD_SYNT_PLL1_DIV4_VAL 0
+ #define CLCD_SYNT_PLL2_VAL 1
+ #define CLCD_SYNT_CLK_MASK 1
+ #define CLCD_SYNT_CLK_SHIFT 31
+ #define RAS_SYNT2_3_PLL1_DIV4_VAL 0
+ #define RAS_SYNT2_3_PLL2_DIV2_VAL 1
+ #define RAS_SYNT2_3_PLL2_VAL 2
+ #define RAS_SYNT2_3_CLK_MASK 3
+ #define RAS_SYNT2_3_CLK_SHIFT 29
+ #define RAS_SYNT0_1_PLL1_DIV4_VAL 0
+ #define RAS_SYNT0_1_PLL3_DIV2_VAL 1
+ #define RAS_SYNT0_1_PLL3_VAL 2
+ #define RAS_SYNT0_1_CLK_MASK 3
+ #define RAS_SYNT0_1_CLK_SHIFT 27
+ #define OSC_24M_VAL 0
+ #define OSC_25M_VAL 1
+ #define PLL_CLK_MASK 3
+ #define PLL3_CLK_SHIFT 24
+ #define PLL2_CLK_SHIFT 22
+ #define PLL1_CLK_SHIFT 20
+
+#define PLL1_CTR (MISC_BASE + 0x214)
+#define PLL1_FRQ (MISC_BASE + 0x218)
+#define PLL1_MOD (MISC_BASE + 0x21C)
+#define PLL2_CTR (MISC_BASE + 0x220)
+#define PLL2_FRQ (MISC_BASE + 0x224)
+#define PLL2_MOD (MISC_BASE + 0x228)
+#define PLL3_CTR (MISC_BASE + 0x22C)
+#define PLL3_FRQ (MISC_BASE + 0x230)
+#define PLL3_MOD (MISC_BASE + 0x234)
+#define PLL4_CTR (MISC_BASE + 0x238)
+ /* PLL_CTR register masks */
+ #define PLL_MODE_NORMAL 0
+ #define PLL_MODE_FRACTION 1
+ #define PLL_MODE_DITH_DSM 2
+ #define PLL_MODE_DITH_SSM 3
+ #define PLL_MODE_MASK 3
+ #define PLL_MODE_SHIFT 3
+ #define PLL_ENABLE 1
+
+#define PLL4_FRQ (MISC_BASE + 0x23C)
+ /* PLL FRQ register masks */
+ #define PLL_NORM_FDBK_M_MASK 0xFF
+ #define PLL_NORM_FDBK_M_SHIFT 24
+ #define PLL_DITH_FDBK_M_MASK 0xFFFF
+ #define PLL_DITH_FDBK_M_SHIFT 16
+ #define PLL_DIV_P_MASK 0x7
+ #define PLL_DIV_P_SHIFT 8
+ #define PLL_DIV_N_MASK 0xFF
+ #define PLL_DIV_N_SHIFT 0
+
+#define PLL4_MOD (MISC_BASE + 0x240)
+#define PERIP_CLK_CFG (MISC_BASE + 0x244)
+ /* PERIP_CLK_CFG bit values */
+ #define GPT3_CLK_SHIFT 13
+ #define GPT2_CLK_SHIFT 12
+ #define MCTR_CLK_PLL1_VAL 0x0
+ #define MCTR_CLK_PLL4_VAL 0x1
+ #define MCTR_CLK_MASK 0x1
+ #define MCTR_CLK_SHIFT 10
+ #define GPT_APB_VAL 1
+ #define GPT_OSC24_VAL 0
+ #define GPT_CLK_MASK 1
+ #define GPT1_CLK_SHIFT 9
+ #define GPT0_CLK_SHIFT 8
+
+ #define AUX_CLK_PLL5_VAL 0
+ #define AUX_CLK_SYNT_VAL 1
+ #define UART_CLK_MASK 1
+ #define UART_CLK_SHIFT 4
+ #define CLCD_CLK_MASK 3
+ #define CLCD_CLK_SHIFT 2
+ #define C3_CLK_MASK 1
+ #define C3_CLK_SHIFT 1
+
+#define GMAC_CLK_CFG (MISC_BASE + 0x248)
+ #define GMAC_PHY_IF_GMII_VAL 0
+ #define GMAC_PHY_IF_RGMII_VAL 1
+ #define GMAC_PHY_IF_RMII_VAL 4
+ #define GMAC_PHY_IF_SEL_MASK 7
+ #define GMAC_PHY_IF_SEL_SHIFT 4
+ #define GMAC_PHY_INPUT_ENB_VAL 0
+ #define GMAC_PHY_SYNT_ENB_VAL 1
+ #define GMAC_PHY_CLK_MASK 1
+ #define GMAC_PHY_CLK_SHIFT 3
+ #define GMAC_PHY_125M_PAD_VAL 0
+ #define GMAC_PHY_PLL2_VAL 1
+ #define GMAC_PHY_OSC3_VAL 2
+ #define GMAC_PHY_INPUT_CLK_MASK 3
+ #define GMAC_PHY_INPUT_CLK_SHIFT 1
+
+#define C3_CLK_SYNT (MISC_BASE + 0x24C)
+ /* refer AUX_* macros for reg masks */
+#define CLCD_CLK_SYNT (MISC_BASE + 0x250)
+ /* Fractional synthesizer reg masks */
+ #define FRAC_SYNT_DIV_FACTOR_MASK 0x1FFFF
+ #define FRAC_SYNT_DIV_FACTOR_SHIFT 0
+
+#define UART_CLK_SYNT (MISC_BASE + 0x254)
+#define GMAC_CLK_SYNT (MISC_BASE + 0x258)
+#define SDHCI_CLK_SYNT (MISC_BASE + 0x25C)
+#define CFXD_CLK_SYNT (MISC_BASE + 0x260)
+ /* aux clk synthesizer register masks */
+ #define AUX_SYNT_ENB 31
+ #define AUX_EQ_SEL_SHIFT 30
+ #define AUX_EQ_SEL_MASK 1
+ #define AUX_EQ1_SEL 0
+ #define AUX_EQ2_SEL 1
+ #define AUX_XSCALE_SHIFT 16
+ #define AUX_XSCALE_MASK 0xFFF
+ #define AUX_YSCALE_SHIFT 0
+ #define AUX_YSCALE_MASK 0xFFF
+
+#define RAS_CLK_SYNT0 (MISC_BASE + 0x264)
+#define RAS_CLK_SYNT1 (MISC_BASE + 0x268)
+#define RAS_CLK_SYNT2 (MISC_BASE + 0x26C)
+#define RAS_CLK_SYNT3 (MISC_BASE + 0x270)
+ /* Check Fractional synthesizer reg masks */
+
+#define PERIP1_CLK_ENB (MISC_BASE + 0x274)
+ /* PERIP1_CLK_ENB register masks */
+ #define RTC_CLK_ENB 31
+ #define ADC_CLK_ENB 30
+ #define C3_CLK_ENB 29
+ #define JPEG_CLK_ENB 28
+ #define CLCD_CLK_ENB 27
+ #define DMA1_CLK_ENB 26
+ #define DMA0_CLK_ENB 25
+ #define GPIO1_CLK_ENB 24
+ #define GPIO0_CLK_ENB 23
+ #define GPT1_CLK_ENB 22
+ #define GPT0_CLK_ENB 21
+ #define I2S0_CLK_ENB 20
+ #define I2S1_CLK_ENB 19
+ #define I2C_CLK_ENB 18
+ #define SSP_CLK_ENB 17
+ #define UART_CLK_ENB 15
+ #define PCIE2_CLK_ENB 14
+ #define PCIE1_CLK_ENB 13
+ #define PCIE0_CLK_ENB 12
+ #define USBD_CLK_ENB 11
+ #define UHC1_CLK_ENB 10
+ #define UHC0_CLK_ENB 9
+ #define GMAC_CLK_ENB 8
+ #define CFXD_CLK_ENB 7
+ #define SDHCI_CLK_ENB 6
+ #define SMI_CLK_ENB 5
+ #define FSMC_CLK_ENB 4
+ #define SYSRAM0_CLK_ENB 3
+ #define SYSRAM1_CLK_ENB 2
+ #define SYSROM_CLK_ENB 1
+ #define BUS_CLK_ENB 0
+
+#define PERIP2_CLK_ENB (MISC_BASE + 0x278)
+ /* PERIP2_CLK_ENB register masks */
+ #define THSENS_CLK_ENB 8
+ #define I2S_REF_PAD_CLK_ENB 7
+ #define ACP_CLK_ENB 6
+ #define GPT3_CLK_ENB 5
+ #define GPT2_CLK_ENB 4
+ #define KBD_CLK_ENB 3
+ #define CPU_DBG_CLK_ENB 2
+ #define DDR_CORE_CLK_ENB 1
+ #define DDR_CTRL_CLK_ENB 0
+
+#define PERIP1_SW_RST (MISC_BASE + 0x27C)
+ #define JPEG_SOF_RST 28
+#define PERIP2_SW_RST (MISC_BASE + 0x280)
+#define RAS_CLK_ENB (MISC_BASE + 0x284)
+ /* RAS_CLK_ENB register masks */
+ #define SYNT3_CLK_ENB 17
+ #define SYNT2_CLK_ENB 16
+ #define SYNT1_CLK_ENB 15
+ #define SYNT0_CLK_ENB 14
+ #define PCLK3_CLK_ENB 13
+ #define PCLK2_CLK_ENB 12
+ #define PCLK1_CLK_ENB 11
+ #define PCLK0_CLK_ENB 10
+ #define PLL3_CLK_ENB 9
+ #define PLL2_CLK_ENB 8
+ #define C125M_PAD_CLK_ENB 7
+ #define C30M_CLK_ENB 6
+ #define C48M_CLK_ENB 5
+ #define OSC3_CLK_ENB 4
+ #define OSC2_CLK_ENB 3
+ #define OSC1_CLK_ENB 2
+ #define PCLK_CLK_ENB 1
+ #define ACLK_CLK_ENB 0
+#define RAS_SW_RST (MISC_BASE + 0x288)
+#define PLL1_SYNT (MISC_BASE + 0x28C)
+ /* Check Fractional synthesizer reg masks */
+
+#define I2S_CLK_CFG (MISC_BASE + 0x290)
+ /* I2S_CLK_CFG register mask */
+ #define I2S_SCLK_X_MASK 0x1F
+ #define I2S_SCLK_X_SHIFT 27
+ #define I2S_SCLK_Y_MASK 0x1F
+ #define I2S_SCLK_Y_SHIFT 22
+ #define I2S_SCLK_EQ_SEL_SHIFT 21
+ #define I2S_SCLK_SYNTH_ENB 20
+ #define I2S_PRS1_CLK_X_MASK 0xFF
+ #define I2S_PRS1_CLK_X_SHIFT 12
+ #define I2S_PRS1_CLK_Y_MASK 0xFF
+ #define I2S_PRS1_CLK_Y_SHIFT 4
+ #define I2S_PRS1_EQ_SEL_SHIFT 3
+ #define I2S_REF_SRC_VAL 0
+ #define I2S_REF_PRS1_VAL 1
+ #define I2S_REF_SEL_MASK 1
+ #define I2S_REF_SHIFT 2
+ #define I2S_SRC_PLLDIV2_VAL 0
+ #define I2S_SRC_PLL3_VAL 1
+ #define I2S_SRC_PL_CLK1_VAL 2
+ #define I2S_SRC_CLK_MASK 3
+ #define I2S_SRC_CLK_SHIFT 0
+
+/* Peripheral Configuration Registers */
+#define DMAC_HS_SEL (MISC_BASE + 0x300)
+#define DMAC_SEL (MISC_BASE + 0x304)
+#define DMAC_FLOW_SEL (MISC_BASE + 0x308)
+#define DMAC_DIR_SEL (MISC_BASE + 0x30C)
+#define DMAC_CFG (MISC_BASE + 0x310)
+#define USBPHY_GEN_CFG (MISC_BASE + 0x314)
+#define USBPHY_P1_CFG (MISC_BASE + 0x318)
+#define USBPHY_P2_CFG (MISC_BASE + 0x31C)
+#define USBPHY_P3_CFG (MISC_BASE + 0x320)
+#define PCIE_CFG (MISC_BASE + 0x324)
+ /* PCIE CFG MASks */
+ #define PCIE0_CFG_DEVICE_PRESENT (1 << 11)
+ #define PCIE1_CFG_DEVICE_PRESENT (1 << 10)
+ #define PCIE2_CFG_DEVICE_PRESENT (1 << 9)
+ #define PCIE0_CFG_POWERUP_RESET (1 << 8)
+ #define PCIE1_CFG_POWERUP_RESET (1 << 7)
+ #define PCIE2_CFG_POWERUP_RESET (1 << 6)
+ #define PCIE0_CFG_CORE_CLK_EN (1 << 5)
+ #define PCIE1_CFG_CORE_CLK_EN (1 << 4)
+ #define PCIE2_CFG_CORE_CLK_EN (1 << 3)
+ #define PCIE0_CFG_AUX_CLK_EN (1 << 2)
+ #define PCIE1_CFG_AUX_CLK_EN (1 << 1)
+ #define PCIE2_CFG_AUX_CLK_EN (1 << 0)
+ #define PCIE0_CFG_VAL (PCIE0_CFG_AUX_CLK_EN | PCIE0_CFG_CORE_CLK_EN \
+ | PCIE0_CFG_POWERUP_RESET | PCIE0_CFG_DEVICE_PRESENT)
+ #define PCIE1_CFG_VAL (PCIE1_CFG_AUX_CLK_EN | PCIE1_CFG_CORE_CLK_EN \
+ | PCIE1_CFG_POWERUP_RESET | PCIE1_CFG_DEVICE_PRESENT)
+ #define PCIE2_CFG_VAL (PCIE2_CFG_AUX_CLK_EN | PCIE2_CFG_CORE_CLK_EN \
+ | PCIE2_CFG_POWERUP_RESET | PCIE2_CFG_DEVICE_PRESENT)
+
+#define PCIE_MIPHY_CFG (MISC_BASE + 0x328)
+#define PERIP_CFG (MISC_BASE + 0x32C)
+ /* PERIP_CFG register masks */
+ #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
+ #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
+ #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
+ #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
+ #define MCIF_SEL_SHIFT 3
+#define FSMC_CFG (MISC_BASE + 0x330)
+ /* FSMC_CFG register masks */
+ #define NAND_DEV_WIDTH16 4
+ #define NAND_BANK_MASK 3
+ #define NAND_BANK_SHIFT 2
+ #define FSMC_MEM_NOR 0
+ #define FSMC_MEM_NAND 1
+ #define FSMC_MEM_SRAM 2
+ #define FSMC_MEMSEL_MASK 3
+ #define FSMC_MEMSEL_SHIFT 0
+
+#define MPMC_CTR_STS (MISC_BASE + 0x334)
+
+/* Inter-Processor Communication Registers */
+#define PRC1_LOCK_CTR (MISC_BASE + 0x500)
+#define PRC2_LOCK_CTR (MISC_BASE + 0x504)
+#define PRC1_IRQ_CTR (MISC_BASE + 0x508)
+#define PRC2_IRQ_CTR (MISC_BASE + 0x51C)
+
+/* Pad Configuration Registers */
+#define PAD_PU_CFG_1 (MISC_BASE + 0x600)
+#define PAD_PU_CFG_2 (MISC_BASE + 0x604)
+#define PAD_PU_CFG_3 (MISC_BASE + 0x608)
+#define PAD_PU_CFG_4 (MISC_BASE + 0x60C)
+#define PAD_PU_CFG_5 (MISC_BASE + 0x610)
+#define PAD_PU_CFG_6 (MISC_BASE + 0x614)
+#define PAD_PU_CFG_7 (MISC_BASE + 0x618)
+#define PAD_PU_CFG_8 (MISC_BASE + 0x61C)
+#define PAD_PD_CFG_1 (MISC_BASE + 0x620)
+#define PAD_PD_CFG_2 (MISC_BASE + 0x624)
+#define PAD_PD_CFG_3 (MISC_BASE + 0x628)
+#define PAD_PD_CFG_4 (MISC_BASE + 0x62C)
+#define PAD_PD_CFG_5 (MISC_BASE + 0x630)
+#define PAD_PD_CFG_6 (MISC_BASE + 0x634)
+#define PAD_PD_CFG_7 (MISC_BASE + 0x638)
+#define PAD_PD_CFG_8 (MISC_BASE + 0x63C)
+#define PAD_SLEEP_CFG (MISC_BASE + 0x640)
+#define PAD_HYST_CFG (MISC_BASE + 0x644)
+#define PAD_DRV_CFG (MISC_BASE + 0x648)
+#define PAD_SLEW_CFG (MISC_BASE + 0x64C)
+#define PAD_FUNCTION_EN_1 (MISC_BASE + 0x650)
+#define PAD_FUNCTION_EN_2 (MISC_BASE + 0x654)
+#define PAD_FUNCTION_EN_3 (MISC_BASE + 0x658)
+#define DDR_PAD_CFG (MISC_BASE + 0x65C)
+#define THSENS_CFG (MISC_BASE + 0x6C4)
+
+/* Compensation Configuration Registers */
+#define COMP_1V8_2V5_3V3__1_CFG (MISC_BASE + 0x700)
+#define COMP_1V8_2V5_3V3__2_CFG (MISC_BASE + 0x704)
+#define COMP_3V3_1_CFG (MISC_BASE + 0x708)
+#define COMP_3V3_2_CFG (MISC_BASE + 0x70C)
+#define COMP_DDR_CFG (MISC_BASE + 0x710)
+
+/* OTP Programming Registers */
+#define OTP_PROG_CTR (MISC_BASE + 0x800)
+#define OTP_WDATA1_1 (MISC_BASE + 0x804)
+#define OTP_WDATA1_2 (MISC_BASE + 0x808)
+#define OTP_WDATA1_3 (MISC_BASE + 0x80C)
+#define OTP_WDATA1_4 (MISC_BASE + 0x810)
+#define OTP_WDATA1_5 (MISC_BASE + 0x814)
+#define OTP_WDATA1_6 (MISC_BASE + 0x818)
+#define OTP_WDATA1_7 (MISC_BASE + 0x81C)
+#define OTP_WDATA1_8 (MISC_BASE + 0x820)
+#define OTP_WDATA2_1 (MISC_BASE + 0x824)
+#define OTP_WDATA2_2 (MISC_BASE + 0x828)
+#define OTP_WDATA2_3 (MISC_BASE + 0x82C)
+#define OTP_WDATA2_4 (MISC_BASE + 0x830)
+#define OTP_WDATA2_5 (MISC_BASE + 0x834)
+#define OTP_WDATA2_6 (MISC_BASE + 0x838)
+#define OTP_WDATA2_7 (MISC_BASE + 0x83C)
+#define OTP_WDATA2_8 (MISC_BASE + 0x840)
+#define OTP_MASK_1 (MISC_BASE + 0x844)
+#define OTP_MASK_2 (MISC_BASE + 0x848)
+#define OTP_MASK_3 (MISC_BASE + 0x84C)
+#define OTP_MASK_4 (MISC_BASE + 0x850)
+#define OTP_MASK_5 (MISC_BASE + 0x854)
+#define OTP_MASK_6 (MISC_BASE + 0x858)
+#define OTP_MASK_7 (MISC_BASE + 0x85C)
+#define OTP_MASK_8 (MISC_BASE + 0x860)
+#define OTP_RDATA1_1 (MISC_BASE + 0x864)
+#define OTP_RDATA1_2 (MISC_BASE + 0x868)
+#define OTP_RDATA1_3 (MISC_BASE + 0x86C)
+#define OTP_RDATA1_4 (MISC_BASE + 0x870)
+#define OTP_RDATA1_5 (MISC_BASE + 0x874)
+#define OTP_RDATA1_6 (MISC_BASE + 0x878)
+#define OTP_RDATA1_7 (MISC_BASE + 0x87C)
+#define OTP_RDATA1_8 (MISC_BASE + 0x880)
+#define OTP_RDATA2_1 (MISC_BASE + 0x884)
+#define OTP_RDATA2_2 (MISC_BASE + 0x888)
+#define OTP_RDATA2_3 (MISC_BASE + 0x88C)
+#define OTP_RDATA2_4 (MISC_BASE + 0x890)
+#define OTP_RDATA2_5 (MISC_BASE + 0x894)
+#define OTP_RDATA2_6 (MISC_BASE + 0x898)
+#define OTP_RDATA2_7 (MISC_BASE + 0x89C)
+#define OTP_RDATA2_8 (MISC_BASE + 0x8A0)
+#define OTP_RDATAM_1 (MISC_BASE + 0x8A4)
+#define OTP_RDATAM_2 (MISC_BASE + 0x8A8)
+#define OTP_RDATAM_3 (MISC_BASE + 0x8AC)
+#define OTP_RDATAM_4 (MISC_BASE + 0x8B0)
+#define OTP_RDATAM_5 (MISC_BASE + 0x8B4)
+#define OTP_RDATAM_6 (MISC_BASE + 0x8B8)
+#define OTP_RDATAM_7 (MISC_BASE + 0x8BC)
+#define OTP_RDATAM_8 (MISC_BASE + 0x8C0)
+
+/* A9SM Registers */
+#define A9SM_CLUSTERID (MISC_BASE + 0x900)
+#define A9SM_STATUS (MISC_BASE + 0x904)
+#define A9SM_DEBUG (MISC_BASE + 0x908)
+#define A9SM_FILTER (MISC_BASE + 0x90C)
+#define A9SM_PARITY_CFG (MISC_BASE + 0x910)
+#define A9SM_PARITY_ERR (MISC_BASE + 0x914)
+
+/* SOC ID Registers */
+#define DIE_ID_1 (MISC_BASE + 0xA00)
+#define DIE_ID_2 (MISC_BASE + 0xA04)
+#define DIE_ID_3 (MISC_BASE + 0xA08)
+#define DIE_ID_4 (MISC_BASE + 0xA0C)
+#define DIE_ID_VALID (MISC_BASE + 0xA10)
+
+/* SOC TEST & DEBUG Registers */
+#define MIPHY_TEST (MISC_BASE + 0x1000)
+#define PCIE_MSTR_P0 (MISC_BASE + 0x1004)
+#define PCIE_AWMISC_P0 (MISC_BASE + 0x1008)
+#define PCIE_ARMISC_P0 (MISC_BASE + 0x100C)
+#define PCIE_MSTR_P1 (MISC_BASE + 0x1010)
+#define PCIE_AWMISC_P1 (MISC_BASE + 0x1014)
+#define PCIE_ARMISC_P1 (MISC_BASE + 0x1018)
+#define PCIE_MSTR_P2 (MISC_BASE + 0x101C)
+#define PCIE_AWMISC_P2 (MISC_BASE + 0x1020)
+#define PCIE_ARMISC_P2 (MISC_BASE + 0x1024)
+
+#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/smp.h b/arch/arm/mach-spear13xx/include/mach/smp.h
new file mode 100644
index 0000000..c1c4580
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/smp.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/smp.h
+ *
+ * Few SMP related definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+#include <asm/hardware/gic.h>
+
+/* We use IRQ1 as the IPI */
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
+{
+ gic_raise_softirq(mask, ipi);
+}
+
+#endif
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
new file mode 100644
index 0000000..1a1af72
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -0,0 +1,94 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear.h
+ *
+ * spear13xx Machine family specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR13XX_H
+#define __MACH_SPEAR13XX_H
+
+#include <asm/memory.h>
+#include <mach/spear1300.h>
+
+#define SPEAR13XX_L2CC_BASE UL(0xED000000)
+
+/* ARM9SMP peripheral base address */
+#define SPEAR13XX_A9SM_PERIP_BASE UL(0xEC800000)
+#define VA_SPEAR13XX_A9SM_PERIP_BASE IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE)
+/* A9SM peripheral offsets */
+#define SPEAR13XX_SCU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x00)
+#define SPEAR13XX_GIC_CPU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x100)
+#define SPEAR13XX_GLOBAL_TMR_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x200)
+#define SPEAR13XX_LOCAL_TMR_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x600)
+#define SPEAR13XX_WDT_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x620)
+#define SPEAR13XX_GIC_DIST_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x1000)
+
+#define SPEAR13XX_UART_BASE UL(0xE0000000)
+#define VA_SPEAR13XX_UART_BASE IO_ADDRESS(SPEAR13XX_UART_BASE)
+
+#define SPEAR13XX_ADC_BASE UL(0xE0080000)
+#define SPEAR13XX_SSP_BASE UL(0xE0100000)
+#define SPEAR13XX_I2S0_BASE UL(0xE0180000)
+#define SPEAR13XX_I2S1_BASE UL(0xE0200000)
+#define SPEAR13XX_I2C_BASE UL(0xE0280000)
+#define SPEAR13XX_KBD_BASE UL(0xE0300000)
+#define SPEAR13XX_GPT0_BASE UL(0xE0380000)
+#define SPEAR13XX_GPT1_BASE UL(0xE0400000)
+#define SPEAR13XX_GPT2_BASE UL(0xE0480000)
+#define SPEAR13XX_GPT3_BASE UL(0xE0500000)
+#define SPEAR13XX_RTC_BASE UL(0xE0580000)
+#define SPEAR13XX_GPIO0_BASE UL(0xE0600000)
+#define SPEAR13XX_GPIO1_BASE UL(0xE0680000)
+#define SPEAR13XX_MISC_BASE UL(0xE0700000)
+#define VA_SPEAR13XX_MISC_BASE IO_ADDRESS(SPEAR13XX_MISC_BASE)
+
+#define SPEAR13XX_SYSRAM0_BASE UL(0xB3800000)
+#define SPEAR13XX_SYSRAM0_SIZE 0x00800000
+
+/*
+ * The system location which is polled by secondary cpus to find the
+ * jump address
+ */
+#define SPEAR13XX_SYS_LOCATION (SPEAR13XX_SYSRAM0_BASE + 0x600)
+
+#define SPEAR13XX_SYSRAM1_BASE UL(0xE0800000)
+#define SPEAR13XX_SYSRAM1_SIZE 0x00800000
+#define SPEAR13XX_CLCD_BASE UL(0xE1000000)
+#define SPEAR13XX_C3_BASE UL(0xE1800000)
+#define SPEAR13XX_GETH_BASE UL(0xE2000000)
+#define SPEAR13XX_UPD_BASE UL(0xE2800000)
+#define SPEAR13XX_UDC_BASE UL(0xE3800000)
+#define SPEAR13XX_UHC0_OHCI_BASE UL(0xE4000000)
+#define SPEAR13XX_UHC0_EHCI_BASE UL(0xE4800000)
+#define SPEAR13XX_UHC1_OHCI_BASE UL(0xE5000000)
+#define SPEAR13XX_UHC1_EHCI_BASE UL(0xE5800000)
+#define SPEAR13XX_SMI_MEM_BASE UL(0xE6000000)
+#define SPEAR13XX_SMI_CTRL_BASE UL(0xEA000000)
+#define SPEAR13XX_DMAC0_BASE UL(0xEA800000)
+#define SPEAR13XX_DMAC1_BASE UL(0xEB000000)
+#define SPEAR13XX_MII_PHY_BASE UL(0xEB800000)
+#define SPEAR13XX_MPMC_BASE UL(0xEC000000)
+#define SPEAR13XX_PCIE0_BASE UL(0x80000000)
+#define SPEAR13XX_PCIE1_BASE UL(0x90000000)
+#define SPEAR13XX_PCIE2_BASE UL(0xC0000000)
+#define SPEAR13XX_PCIE0_APP_BASE UL(0xB1000000)
+#define SPEAR13XX_PCIE1_APP_BASE UL(0xB1800000)
+#define SPEAR13XX_PCIE2_APP_BASE UL(0xB4000000)
+#define SPEAR13XX_FSMC_MEM_BASE UL(0xA0000000)
+#define SPEAR13XX_FSMC_BASE UL(0xB0000000)
+#define SPEAR13XX_JPEG_BASE UL(0xB2000000)
+#define SPEAR13XX_MCIF_CF_BASE UL(0xB2800000)
+#define SPEAR13XX_MCIF_SDHCI_BASE UL(0xB3000000)
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE SPEAR13XX_UART_BASE
+#define VA_SPEAR_DBG_UART_BASE VA_SPEAR13XX_UART_BASE
+
+#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1300.h b/arch/arm/mach-spear13xx/include/mach/spear1300.h
new file mode 100644
index 0000000..b3ba267
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1300.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear1300.h
+ *
+ * SPEAr1300 Machine specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR1300
+
+#ifndef __MACH_SPEAR1300_H
+#define __MACH_SPEAR1300_H
+
+#endif /* __MACH_SPEAR1300_H */
+
+#endif /* CONFIG_MACH_SPEAR1300 */
diff --git a/arch/arm/mach-spear13xx/include/mach/system.h b/arch/arm/mach-spear13xx/include/mach/system.h
new file mode 100644
index 0000000..a9b159d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/system.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/system.h
+ *
+ * spear13xx Machine family specific architecture functions
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/misc_regs.h>
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+ writel(0x01, SYS_SW_RES);
+}
+
+#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
new file mode 100644
index 0000000..0a81490
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/timex.h
+ *
+ * spear13xx machine family specific timex definitions
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE 24000000
+
+#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
new file mode 100644
index 0000000..3c27f25
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <plat/uncompress.h>
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/vmalloc.h b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
new file mode 100644
index 0000000..0f243af
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/vmalloc.h
+ *
+ * Defining Vmalloc area for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#define VMALLOC_END 0xEC800000UL
+
+#endif /* __MACH_VMALLOC_H */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 02/10 resend] SPEAr13xx: Add machine specific src files
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (10 preceding siblings ...)
2011-03-28 5:53 ` [PATCH V6 01/10 resend] SPEAr13xx: Add machine specific header files Viresh Kumar
@ 2011-03-28 5:53 ` Viresh Kumar
2011-05-27 6:15 ` [PATCH V6 00/10] Adding SPEAr13xx support viresh kumar
12 siblings, 0 replies; 14+ messages in thread
From: Viresh Kumar @ 2011-03-28 5:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Changes in V6 resend:
- Updated clock.c according to misc register definition updations
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/Kconfig | 21 +
arch/arm/mach-spear13xx/Makefile | 14 +
arch/arm/mach-spear13xx/Makefile.boot | 3 +
arch/arm/mach-spear13xx/clock.c | 1012 ++++++++++++++++++++++++
arch/arm/mach-spear13xx/headsmp.S | 42 +
arch/arm/mach-spear13xx/include/mach/generic.h | 2 +-
arch/arm/mach-spear13xx/localtimer.c | 25 +
arch/arm/mach-spear13xx/platsmp.c | 162 ++++
arch/arm/mach-spear13xx/spear1300.c | 23 +
arch/arm/mach-spear13xx/spear1300_evb.c | 48 ++
arch/arm/mach-spear13xx/spear13xx.c | 121 +++
11 files changed, 1472 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/Kconfig
create mode 100644 arch/arm/mach-spear13xx/Makefile
create mode 100644 arch/arm/mach-spear13xx/Makefile.boot
create mode 100644 arch/arm/mach-spear13xx/clock.c
create mode 100644 arch/arm/mach-spear13xx/headsmp.S
create mode 100644 arch/arm/mach-spear13xx/localtimer.c
create mode 100644 arch/arm/mach-spear13xx/platsmp.c
create mode 100644 arch/arm/mach-spear13xx/spear1300.c
create mode 100644 arch/arm/mach-spear13xx/spear1300_evb.c
create mode 100644 arch/arm/mach-spear13xx/spear13xx.c
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
new file mode 100644
index 0000000..3ea463d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -0,0 +1,21 @@
+#
+# SPEAr13XX Machine configuration file
+#
+
+if ARCH_SPEAR13XX
+
+menu "SPEAr13xx Implementations"
+config BOARD_SPEAR1300_EVB
+ bool "SPEAr1300 Evaluation Board"
+ select MACH_SPEAR1300
+ help
+ Supports ST SPEAr1300 Evaluation Board
+
+endmenu
+
+config MACH_SPEAR1300
+ bool "SPEAr1300"
+ help
+ Supports ST SPEAr1300 Machine
+
+endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
new file mode 100644
index 0000000..cb5ae9e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for SPEAr13XX machine series
+#
+
+# common files
+obj-y += spear13xx.o clock.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
+
+# spear1300 specific files
+obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
+
+# spear1300 boards files
+obj-$(CONFIG_BOARD_SPEAR1300_EVB) += spear1300_evb.o
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
new file mode 100644
index 0000000..7a1f3c0
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
new file mode 100644
index 0000000..1e70cd1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -0,0 +1,1012 @@
+/*
+ * arch/arm/mach-spear13xx/clock.c
+ *
+ * SPEAr13xx machines clock framework source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * shiraz hashim<shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <asm/mach-types.h>
+#include <plat/clock.h>
+#include <mach/hardware.h>
+#include <mach/misc_regs.h>
+
+/* root clks */
+/* 24 MHz oscillator clock */
+static struct clk osc1_24m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 24000000,
+};
+
+/* 32 KHz oscillator clock */
+static struct clk osc2_32k_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 32000,
+};
+
+/* 25 MHz MIPHY oscillator clock */
+static struct clk osc3_25m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 25000000,
+};
+
+/* clock derived from 32 KHz osc clk */
+/* rtc clock */
+static struct clk rtc_clk = {
+ .pclk = &osc2_32k_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = RTC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from osc1 or osc3 */
+/* pll[1-3] parents */
+static struct pclk_info pll_pclk_info[] = {
+ {
+ .pclk = &osc1_24m_clk,
+ .pclk_val = OSC_24M_VAL,
+ }, {
+ .pclk = &osc3_25m_clk,
+ .pclk_val = OSC_25M_VAL,
+ },
+};
+
+/* pll[1-3] parent select structure */
+static struct pclk_sel pll_pclk_sel = {
+ .pclk_info = pll_pclk_info,
+ .pclk_count = ARRAY_SIZE(pll_pclk_info),
+ .pclk_sel_reg = PLL_CFG,
+ .pclk_sel_mask = PLL_CLK_MASK,
+};
+
+/* pll masks structure */
+static struct pll_clk_masks pll_masks = {
+ .mode_mask = PLL_MODE_MASK,
+ .mode_shift = PLL_MODE_SHIFT,
+ .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
+ .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
+ .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
+ .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
+ .div_p_mask = PLL_DIV_P_MASK,
+ .div_p_shift = PLL_DIV_P_SHIFT,
+ .div_n_mask = PLL_DIV_N_MASK,
+ .div_n_shift = PLL_DIV_N_SHIFT,
+};
+/* pll1 configuration structure */
+static struct pll_clk_config pll1_config = {
+ .mode_reg = PLL1_CTR,
+ .cfg_reg = PLL1_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll_rtbl[] = {
+ /* PCLK 24MHz */
+ {.mode = 0, .m = 0x7D, .n = 0x03, .p = 0x2}, /* 500 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x03, .p = 0x2}, /* 664 MHz */
+ {.mode = 0, .m = 0xC8, .n = 0x03, .p = 0x2}, /* 800 MHz */
+ {.mode = 0, .m = 0xFA, .n = 0x06, .p = 0x1}, /* 1000 MHz */
+};
+
+/* pll1 clock */
+static struct clk pll1_clk = {
+ .flags = ENABLED_ON_INIT,
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL1_CLK_SHIFT,
+ .en_reg = PLL1_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .private_data = &pll1_config,
+};
+
+/* pll1div2 clock */
+static struct clk pll1div2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* pll1div4 clock */
+static struct clk pll1div4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 4,
+ .recalc = &follow_parent,
+};
+
+/* pll2 configuration structure */
+static struct pll_clk_config pll2_config = {
+ .mode_reg = PLL2_CTR,
+ .cfg_reg = PLL2_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll2 clock */
+static struct clk pll2_clk = {
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL2_CLK_SHIFT,
+ .en_reg = PLL2_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .private_data = &pll2_config,
+};
+
+/* pll3 configuration structure */
+static struct pll_clk_config pll3_config = {
+ .mode_reg = PLL3_CTR,
+ .cfg_reg = PLL3_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll3 clock */
+static struct clk pll3_clk = {
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL3_CLK_SHIFT,
+ .en_reg = PLL3_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .private_data = &pll3_config,
+};
+
+/* pll4 (DDR) configuration structure */
+static struct pll_clk_config pll4_config = {
+ .mode_reg = PLL4_CTR,
+ .cfg_reg = PLL4_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll4 rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll4_rtbl[] = {
+ {.mode = 0, .m = 0x7D, .n = 0x03, .p = 0x2}, /* 500 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x03, .p = 0x2}, /* 664 MHz */
+ {.mode = 0, .m = 0xC8, .n = 0x03, .p = 0x2}, /* 800 MHz */
+ {.mode = 0, .m = 0xFA, .n = 0x06, .p = 0x1}, /* 1000 MHz */
+};
+
+/* pll4 (DDR) clock */
+static struct clk pll4_clk = {
+ .flags = ENABLED_ON_INIT,
+ .pclk = &osc1_24m_clk,
+ .en_reg = PLL4_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll4_rtbl, ARRAY_SIZE(pll4_rtbl), 3},
+ .private_data = &pll4_config,
+};
+
+/* pll5 USB 48 MHz clock */
+static struct clk pll5_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc1_24m_clk,
+ .rate = 48000000,
+};
+
+/* pll6 (MIPHY) clock */
+static struct clk pll6_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc3_25m_clk,
+ .rate = 25000000,
+};
+
+/* clocks derived from pll1 clk */
+/* cpu clock */
+static struct clk cpu_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* ahb clock */
+static struct clk ahb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 6,
+ .recalc = &follow_parent,
+};
+
+/* apb clock */
+static struct clk apb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 12,
+ .recalc = &follow_parent,
+};
+
+/* clocks derived from osc1, ahb or apb */
+/* gpt[0-3] parents */
+static struct pclk_info gpt_pclk_info[] = {
+ {
+ .pclk = &osc1_24m_clk,
+ .pclk_val = GPT_OSC24_VAL,
+ }, {
+ .pclk = &apb_clk,
+ .pclk_val = GPT_APB_VAL,
+ },
+};
+
+/* gpt[0-3] parent select structure */
+static struct pclk_sel gpt_pclk_sel = {
+ .pclk_info = gpt_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
+/* gpt0 timer clock */
+static struct clk gpt0_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT0_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT0_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt1 timer clock */
+static struct clk gpt1_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT1_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT1_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt2 timer clock */
+static struct clk gpt2_clk = {
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = GPT2_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT2_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt3 timer clock */
+static struct clk gpt3_clk = {
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = GPT3_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT3_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* watch dog timer clock */
+static struct clk wdt_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &cpu_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* auxiliary synthesizers masks */
+static struct aux_clk_masks aux_masks = {
+ .eq_sel_mask = AUX_EQ_SEL_MASK,
+ .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+ .eq1_mask = AUX_EQ1_SEL,
+ .eq2_mask = AUX_EQ2_SEL,
+ .xscale_sel_mask = AUX_XSCALE_MASK,
+ .xscale_sel_shift = AUX_XSCALE_SHIFT,
+ .yscale_sel_mask = AUX_YSCALE_MASK,
+ .yscale_sel_shift = AUX_YSCALE_SHIFT,
+};
+
+/* clocks derived multiple parents (pll1, pll5, synthesizers or others) */
+/* uart configurations */
+static struct aux_clk_config uart_synth_config = {
+ .synth_reg = UART_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* aux rate configuration table, in ascending order of rates */
+struct aux_rate_tbl aux_rtbl[] = {
+ /* For PLL1div2 = 500 MHz */
+ {.xscale = 2, .yscale = 21, .eq = 1}, /* 48 MHz */
+ {.xscale = 1, .yscale = 6, .eq = 1}, /* 83 MHz */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* 125 MHz */
+ {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
+};
+
+/* uart synth clock */
+static struct clk uart_synth_clk = {
+ .en_reg = UART_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+ .private_data = &uart_synth_config,
+};
+
+/* uart parents */
+static struct pclk_info uart_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &uart_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* uart parent select structure */
+static struct pclk_sel uart_pclk_sel = {
+ .pclk_info = uart_pclk_info,
+ .pclk_count = ARRAY_SIZE(uart_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = UART_CLK_MASK,
+};
+
+/* uart clock */
+static struct clk uart_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UART_CLK_ENB,
+ .pclk_sel = &uart_pclk_sel,
+ .pclk_sel_shift = UART_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* sdhci configurations */
+static struct aux_clk_config sdhci_synth_config = {
+ .synth_reg = SDHCI_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* sdhci synth clock */
+static struct clk sdhci_synth_clk = {
+ .en_reg = SDHCI_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .private_data = &sdhci_synth_config,
+};
+
+/* sdhci clock */
+static struct clk sdhci_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SDHCI_CLK_ENB,
+ .pclk = &sdhci_synth_clk,
+ .recalc = &follow_parent,
+};
+
+/* cfxd configurations */
+static struct aux_clk_config cfxd_synth_config = {
+ .synth_reg = CFXD_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* cfxd synth clock */
+static struct clk cfxd_synth_clk = {
+ .en_reg = CFXD_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .private_data = &cfxd_synth_config,
+};
+
+/* cfxd clock */
+static struct clk cfxd_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = CFXD_CLK_ENB,
+ .pclk = &cfxd_synth_clk,
+ .recalc = &follow_parent,
+};
+
+/* C3 clk configurations */
+static struct aux_clk_config c3_synth_config = {
+ .synth_reg = C3_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* c3 synth clock */
+static struct clk c3_synth_clk = {
+ .en_reg = C3_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+ .private_data = &c3_synth_config,
+};
+
+/* c3 parents */
+static struct pclk_info c3_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &c3_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* c3 parent select structure */
+static struct pclk_sel c3_pclk_sel = {
+ .pclk_info = c3_pclk_info,
+ .pclk_count = ARRAY_SIZE(c3_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = C3_CLK_MASK,
+};
+
+/* c3 clock */
+static struct clk c3_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = C3_CLK_ENB,
+ .pclk_sel = &c3_pclk_sel,
+ .pclk_sel_shift = C3_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gmac phy clk configurations */
+static struct aux_clk_config gmac_phy_synth_config = {
+ .synth_reg = GMAC_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* gmii external pad clock for phy operation */
+static struct clk gmii_txclk125_pad = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 125000000,
+};
+
+/* gmac phy set of input clks*/
+static struct pclk_info gmac_phy_input_pclk_info[] = {
+ {
+ .pclk = &gmii_txclk125_pad,
+ .pclk_val = GMAC_PHY_125M_PAD_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = GMAC_PHY_PLL2_VAL,
+ }, {
+ .pclk = &osc3_25m_clk,
+ .pclk_val = GMAC_PHY_OSC3_VAL,
+ },
+};
+
+static struct pclk_sel gmac_phy_input_pclk_sel = {
+ .pclk_info = gmac_phy_input_pclk_info,
+ .pclk_count = ARRAY_SIZE(gmac_phy_input_pclk_info),
+ .pclk_sel_reg = GMAC_CLK_CFG,
+ .pclk_sel_mask = GMAC_PHY_INPUT_CLK_MASK,
+};
+
+static struct clk gmac_phy_input_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gmac_phy_input_pclk_sel,
+ .pclk_sel_shift = GMAC_PHY_INPUT_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gmac rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl gmac_rtbl[] = {
+ /* For gmac phy input clk */
+ {.xscale = 1, .yscale = 6, .eq = 1}, /* divided by 6 */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* divided by 4 */
+ {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
+};
+
+static struct clk gmac_phy_synth_clk = {
+ .en_reg = GMAC_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &gmac_phy_input_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {gmac_rtbl, ARRAY_SIZE(gmac_rtbl), 0},
+ .private_data = &gmac_phy_synth_config,
+};
+
+/* gmac phy parents */
+static struct pclk_info gmac_phy_pclk_info[] = {
+ {
+ .pclk = &gmac_phy_input_clk,
+ .pclk_val = GMAC_PHY_INPUT_ENB_VAL,
+ }, {
+ .pclk = &gmac_phy_synth_clk,
+ .pclk_val = GMAC_PHY_SYNT_ENB_VAL,
+ }
+};
+
+/* gmac phy parent select structure */
+static struct pclk_sel gmac_phy_pclk_sel = {
+ .pclk_info = gmac_phy_pclk_info,
+ .pclk_count = ARRAY_SIZE(gmac_phy_pclk_info),
+ .pclk_sel_reg = GMAC_CLK_CFG,
+ .pclk_sel_mask = GMAC_PHY_CLK_MASK,
+};
+
+/* gmac phy clock */
+static struct clk gmac_phy0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gmac_phy_pclk_sel,
+ .pclk_sel_shift = GMAC_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* clcd synthesizers masks */
+static struct clcd_synth_masks clcd_masks = {
+ .div_factor_mask = FRAC_SYNT_DIV_FACTOR_MASK,
+ .div_factor_shift = FRAC_SYNT_DIV_FACTOR_SHIFT,
+};
+
+static struct clcd_clk_config clcd_synth_config = {
+ .synth_reg = CLCD_CLK_SYNT,
+ .masks = &clcd_masks,
+};
+
+/* clcd synth parents */
+static struct pclk_info clcd_synth_pclk_info[] = {
+ {
+ .pclk = &pll1div4_clk,
+ .pclk_val = CLCD_SYNT_PLL1_DIV4_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = CLCD_SYNT_PLL2_VAL,
+ },
+};
+
+/* clcd synth parent select structure */
+static struct pclk_sel clcd_synth_pclk_sel = {
+ .pclk_info = clcd_synth_pclk_info,
+ .pclk_count = ARRAY_SIZE(clcd_synth_pclk_info),
+ .pclk_sel_reg = PLL_CFG,
+ .pclk_sel_mask = CLCD_SYNT_CLK_MASK,
+};
+
+/* clcd rate configuration table, in ascending order of rates */
+struct clcd_rate_tbl clcd_rtbl[] = {
+ /* For pll1div4 = 250 MHz */
+ {.div = 0x4000}, /* 62.5 MHz */
+ {.div = 0x2000}, /* 125 MHz */
+};
+
+/* clcd synth clock */
+static struct clk clcd_synth_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &clcd_synth_pclk_sel,
+ .pclk_sel_shift = CLCD_SYNT_CLK_SHIFT,
+ .calc_rate = &clcd_calc_rate,
+ .recalc = &clcd_clk_recalc,
+ .set_rate = &clcd_clk_set_rate,
+ .rate_config = {clcd_rtbl, ARRAY_SIZE(clcd_rtbl), 1},
+ .private_data = &clcd_synth_config,
+};
+
+/* clcd clock parents */
+static struct pclk_info clcd_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &clcd_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* clcd parent select structure */
+static struct pclk_sel clcd_pclk_sel = {
+ .pclk_info = clcd_pclk_info,
+ .pclk_count = ARRAY_SIZE(clcd_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = CLCD_CLK_MASK,
+};
+
+/* clcd clock */
+static struct clk clcd_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = CLCD_CLK_ENB,
+ .pclk_sel = &clcd_pclk_sel,
+ .pclk_sel_shift = CLCD_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from ahb clk */
+
+/* i2c clock */
+static struct clk i2c_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2C_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* dma clock */
+static struct clk dma0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk dma1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* jpeg clock */
+static struct clk jpeg_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = JPEG_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gmac clock :Fixed Part*/
+static struct clk gmac0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GMAC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* fsmc clock */
+static struct clk fsmc_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = FSMC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* smi clock */
+static struct clk smi_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SMI_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* uhc0 clock */
+static struct clk uhci0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UHC0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* uhc1 clock */
+static struct clk uhci1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UHC1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* usbd clock */
+static struct clk usbd_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = USBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* pci clocks */
+static struct clk pcie0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk pcie1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk pcie2_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* sysram clocks */
+static struct clk sysram0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SYSRAM0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk sysram1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SYSRAM1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from apb clk */
+/* adc clock */
+static struct clk adc_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = ADC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ssp clock */
+static struct clk ssp_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SSP_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio0_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* i2s0 clock */
+static struct clk i2s0_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2S0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* i2s1 clock */
+static struct clk i2s1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2S1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* keyboard clock */
+static struct clk kbd_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = KBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* RAS CLOCKS */
+/* pll3 generated clock */
+static struct clk ras_pll3_clk = {
+ .pclk = &pll3_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PLL3_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* pll2 generated clock */
+static struct clk ras_pll2_clk = {
+ .pclk = &pll2_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PLL2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* 125MHz clock generated on Tx pad */
+static struct clk ras_tx125_clk = {
+ .pclk = &gmii_txclk125_pad,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C125M_PAD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* 30 MHz clock generated by USB PHy Pll */
+static struct clk ras_30Mhz_clk = {
+ .rate = 30000000,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C30M_CLK_ENB,
+};
+
+/* 48 MHz clock generated by USB PHy Pll */
+static struct clk ras_48Mhz_clk = {
+ .pclk = &pll5_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C48M_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc3 generated clock */
+static struct clk ras_osc3_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC3_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc2 generated clock */
+static struct clk ras_osc2_clk = {
+ .pclk = &osc2_32k_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc1 generated clock */
+static struct clk ras_osc1_clk = {
+ .pclk = &osc1_24m_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* apb generated clock */
+static struct clk ras_pclk_clk = {
+ .pclk = &apb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PCLK_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ahb generated clock */
+static struct clk ras_aclk_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = ACLK_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* External pad 50 MHz clock for phy operation */
+static struct clk ras_tx50_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 50000000,
+};
+
+/* spear1300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR1300
+
+#endif
+
+static struct clk dummy_apb_pclk;
+
+/* array of all spear 13xx clock lookups */
+static struct clk_lookup spear_clk_lookups[] = {
+ { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
+ /* root clks */
+ {.con_id = "osc1_24m_clk", .clk = &osc1_24m_clk},
+ {.con_id = "osc2_32k_clk", .clk = &osc2_32k_clk},
+ {.con_id = "osc3_25m_clk", .clk = &osc3_25m_clk},
+
+ /* clock derived from 32 KHz osc clk */
+ {.dev_id = "rtc-spear", .clk = &rtc_clk},
+
+ /* clock derived from 24/25 MHz osc1/osc3 clk */
+ {.con_id = "pll1_clk", .clk = &pll1_clk},
+ {.con_id = "pll2_clk", .clk = &pll2_clk},
+ {.con_id = "pll3_clk", .clk = &pll3_clk},
+ {.con_id = "pll4_clk", .clk = &pll4_clk},
+ {.con_id = "pll5_clk", .clk = &pll5_clk},
+ {.con_id = "pll6_clk", .clk = &pll6_clk},
+
+ /* clock derived from pll1 clk */
+ {.con_id = "cpu_clk", .clk = &cpu_clk},
+ {.con_id = "ahb_clk", .clk = &ahb_clk},
+ {.con_id = "apb_clk", .clk = &apb_clk},
+
+ /* synthesizers/prescaled clocks */
+ {.con_id = "pll1div2_clk", .clk = &pll1div2_clk},
+ {.con_id = "pll1div4_clk", .clk = &pll1div4_clk},
+ {.con_id = "c3_synth_clk", .clk = &c3_synth_clk},
+ {.con_id = "gmii_125m_pad_clk", .clk = &gmii_txclk125_pad},
+ {.con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
+ {.con_id = "uart_synth_clk", .clk = &uart_synth_clk},
+ {.con_id = "sdhci_synth_clk", .clk = &sdhci_synth_clk},
+ {.con_id = "cfxd_synth_clk", .clk = &cfxd_synth_clk},
+ {.con_id = "gmac_phy_input_clk", .clk = &gmac_phy_input_clk},
+ {.con_id = "gmac_phy_synth_clk", .clk = &gmac_phy_synth_clk},
+ {.dev_id = "stmmacphy.0", .clk = &gmac_phy0_clk},
+
+ /* RAS clocks */
+ {.con_id = "ras_pll3_clk", .clk = &ras_pll3_clk},
+ {.con_id = "ras_pll2_clk", .clk = &ras_pll2_clk},
+ {.con_id = "ras_tx125_clk", .clk = &ras_tx125_clk},
+ {.con_id = "ras_30Mhz_clk", .clk = &ras_30Mhz_clk},
+ {.con_id = "ras_48Mhz_clk", .clk = &ras_48Mhz_clk},
+ {.con_id = "ras_osc3_clk", .clk = &ras_osc3_clk},
+ {.con_id = "ras_osc2_clk", .clk = &ras_osc2_clk},
+ {.con_id = "ras_osc1_clk", .clk = &ras_osc1_clk},
+ {.con_id = "ras_pclk_clk", .clk = &ras_pclk_clk},
+ {.con_id = "ras_aclk_clk", .clk = &ras_aclk_clk},
+ {.con_id = "ras_tx50_clk", .clk = &ras_tx50_clk},
+
+ /* clocks having multiple parent source from above clocks */
+ {.dev_id = "clcd", .clk = &clcd_clk},
+ {.dev_id = "gpt0", .clk = &gpt0_clk},
+ {.dev_id = "gpt1", .clk = &gpt1_clk},
+ {.dev_id = "gpt2", .clk = &gpt2_clk},
+ {.dev_id = "gpt3", .clk = &gpt3_clk},
+ {.dev_id = "uart", .clk = &uart_clk},
+
+ /* clock derived from ahb clk */
+ {.dev_id = "smi", .clk = &smi_clk},
+ {.con_id = "usbh.0_clk", .clk = &uhci0_clk},
+ {.con_id = "usbh.1_clk", .clk = &uhci1_clk},
+ {.dev_id = "designware_udc", .clk = &usbd_clk},
+ {.dev_id = "i2c_designware.0", .clk = &i2c_clk},
+ {.dev_id = "dma0", .clk = &dma0_clk},
+ {.dev_id = "dma1", .clk = &dma1_clk},
+ {.dev_id = "jpeg", .clk = &jpeg_clk},
+ {.dev_id = "stmmaceth.0", .clk = &gmac0_clk},
+ {.dev_id = "c3", .clk = &c3_clk},
+ {.dev_id = "pcie0", .clk = &pcie0_clk},
+ {.dev_id = "pcie1", .clk = &pcie1_clk},
+ {.dev_id = "pcie2", .clk = &pcie2_clk},
+ {.dev_id = "cfxd", .clk = &cfxd_clk},
+ {.dev_id = "sdhci", .clk = &sdhci_clk},
+ {.con_id = "fsmc", .clk = &fsmc_clk},
+ {.dev_id = "sysram0", .clk = &sysram0_clk},
+ {.dev_id = "sysram1", .clk = &sysram1_clk},
+
+ /* clock derived from apb clk */
+ {.dev_id = "i2s0", .clk = &i2s0_clk},
+ {.dev_id = "i2s1", .clk = &i2s1_clk},
+ {.dev_id = "adc", .clk = &adc_clk},
+ {.dev_id = "ssp-pl022", .clk = &ssp_clk},
+ {.dev_id = "gpio0", .clk = &gpio0_clk},
+ {.dev_id = "gpio1", .clk = &gpio1_clk},
+ {.dev_id = "keyboard", .clk = &kbd_clk},
+ {.dev_id = "wdt", .clk = &wdt_clk},
+};
+
+/* array of all spear 1300 clock lookups */
+#ifdef CONFIG_MACH_SPEAR1300
+static struct clk_lookup spear1300_clk_lookups[] = {
+};
+#endif
+
+void __init spear13xx_clk_init(void)
+{
+ int i, cnt;
+ struct clk_lookup *lookups;
+
+ if (machine_is_spear1300()) {
+ cnt = ARRAY_SIZE(spear1300_clk_lookups);
+ lookups = spear1300_clk_lookups;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ for (i = 0; i < cnt; i++)
+ clk_register(&lookups[i]);
+
+ clk_init();
+}
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
new file mode 100644
index 0000000..502c4fe
--- /dev/null
+++ b/arch/arm/mach-spear13xx/headsmp.S
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-spear13XX/headsmp.S
+ *
+ * Picked from realview
+ * Copyright (c) 2010 ST Microelectronics Limited
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+/*
+ * spear13xx specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(spear13xx_secondary_startup)
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ /*
+ * we've been released from the holding pen: secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+
+ .align
+1: .long .
+ .long pen_release
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 95011a2..781894e 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -33,7 +33,7 @@ extern struct amba_device spear13xx_uart_device;
extern struct sys_timer spear13xx_timer;
/* Add spear13xx family function declarations here */
-void __init clk_init(void);
+void __init spear13xx_clk_init(void);
void __init spear_setup_timer(void);
void __init spear13xx_map_io(void);
void __init spear13xx_init_irq(void);
diff --git a/arch/arm/mach-spear13xx/localtimer.c b/arch/arm/mach-spear13xx/localtimer.c
new file mode 100644
index 0000000..816b08c
--- /dev/null
+++ b/arch/arm/mach-spear13xx/localtimer.c
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear13xx/localtimer.c
+ * Directly picked from realview
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/* Setup the local clock events for a CPU. */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+ evt->irq = IRQ_LOCALTIMER;
+ twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
new file mode 100644
index 0000000..6aa4435
--- /dev/null
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -0,0 +1,162 @@
+/*
+ * arch/arm/mach-spear13xx/platsmp.c
+ *
+ * based upon linux/arch/arm/mach-realview/platsmp.c
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/smp_scu.h>
+#include <asm/system.h>
+#include <asm/unified.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+static DEFINE_SPINLOCK(boot_lock);
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not. This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+ pen_release = val;
+ smp_wmb();
+ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static void __iomem *scu_base_addr(void)
+{
+ return __io_address(SPEAR13XX_SCU_BASE);
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+ /*
+ * if any interrupts are already enabled for the primary
+ * core (e.g. timer irq), then they will not have been enabled
+ * for us: do so
+ */
+ gic_secondary_init(0);
+
+ /*
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+ write_pen_release(-1);
+
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long timeout;
+
+ /*
+ * set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ /*
+ * The secondary processor is waiting to be released from
+ * the holding pen - release it, then wait for it to flag
+ * that it has been released by resetting pen_release.
+ *
+ * Note that "pen_release" is the hardware CPU ID, whereas
+ * "cpu" is Linux's internal ID.
+ */
+ write_pen_release(cpu);
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+ smp_rmb();
+ if (pen_release == -1)
+ break;
+
+ udelay(10);
+ }
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+ void __iomem *scu_base = scu_base_addr();
+ unsigned int i, ncores;
+
+ ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+}
+
+static void __init wakeup_secondary(void)
+{
+ /*
+ * Write the address of secondary startup into the system-wide
+ * location (presently it is in SRAM). The BootMonitor waits
+ * for this register to become non-zero.
+ * We must also send an sev to wake it up
+ */
+ __raw_writel(BSYM(virt_to_phys(spear13xx_secondary_startup)),
+ __io_address(SPEAR13XX_SYS_LOCATION));
+
+ mb();
+
+ /*
+ * Send a 'sev' to wake the secondary core from WFE.
+ */
+ sev();
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ /*
+ * Initialise the present map, which describes the set of CPUs
+ * actually populated at the present time.
+ */
+ for (i = 0; i < max_cpus; i++)
+ set_cpu_present(i, true);
+
+ scu_enable(scu_base_addr());
+ wakeup_secondary();
+}
diff --git a/arch/arm/mach-spear13xx/spear1300.c b/arch/arm/mach-spear13xx/spear1300.c
new file mode 100644
index 0000000..9c38bec
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1300.c
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-spear13xx/spear1300.c
+ *
+ * SPEAr1300 machine source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* Add spear1300 specific devices here */
+
+void __init spear1300_init(void)
+{
+ /* call spear13xx family common init function */
+ spear13xx_init();
+}
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
new file mode 100644
index 0000000..c95c141
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-spear13xx/spear1300_evb.c
+ *
+ * SPEAr1300 evaluation board source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ &spear13xx_uart_device,
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+};
+
+static void __init spear1300_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear1300 machine init function */
+ spear1300_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR1300, "ST-SPEAR1300-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear13xx_map_io,
+ .init_irq = spear13xx_init_irq,
+ .timer = &spear13xx_timer,
+ .init_machine = spear1300_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
new file mode 100644
index 0000000..06f9abb
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -0,0 +1,121 @@
+/*
+ * arch/arm/mach-spear13xx/spear13xx.c
+ *
+ * SPEAr13XX machines common source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/io.h>
+#include <asm/hardware/gic.h>
+#include <asm/irq.h>
+#include <asm/localtimer.h>
+#include <asm/mach/arch.h>
+#include <asm/smp_twd.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+/* Add spear13xx machines common devices here */
+/* uart device registeration */
+struct amba_device spear13xx_uart_device = {
+ .dev = {
+ .init_name = "uart",
+ },
+ .res = {
+ .start = SPEAR13XX_UART_BASE,
+ .end = SPEAR13XX_UART_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART, NO_IRQ},
+};
+
+/* Do spear13xx familiy common initialization part here */
+void __init spear13xx_init(void)
+{
+ /* nothing to do for now */
+}
+
+/* This will initialize vic */
+void __init spear13xx_init_irq(void)
+{
+ gic_init(0, 29, __io_address(SPEAR13XX_GIC_DIST_BASE),
+ __io_address(SPEAR13XX_GIC_CPU_BASE));
+}
+
+/* Following will create static virtual/physical mappings */
+struct map_desc spear13xx_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(SPEAR13XX_UART_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_UART_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_A9SM_PERIP_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_MISC_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_MISC_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_SYSRAM0_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_SYSRAM0_BASE),
+ .length = SZ_32K,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear13xx_map_io(void)
+{
+ iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
+
+ /* This will initialize clock framework */
+ spear13xx_clk_init();
+}
+
+static void __init spear13xx_timer_init(void)
+{
+ char pclk_name[] = "osc1_24m_clk";
+ struct clk *gpt_clk, *pclk;
+
+#ifdef CONFIG_LOCAL_TIMERS
+ /* Setup the local timer base */
+ twd_base = __io_address(SPEAR13XX_LOCAL_TMR_BASE);
+#endif
+
+ /* get the system timer clock */
+ gpt_clk = clk_get_sys("gpt0", NULL);
+ if (IS_ERR(gpt_clk)) {
+ pr_err("%s:couldn't get clk for gpt\n", __func__);
+ BUG();
+ }
+
+ /* get the suitable parent clock for timer*/
+ pclk = clk_get(NULL, pclk_name);
+ if (IS_ERR(pclk)) {
+ pr_err("%s:couldn't get %s as parent for gpt\n",
+ __func__, pclk_name);
+ BUG();
+ }
+
+ clk_set_parent(gpt_clk, pclk);
+ clk_put(gpt_clk);
+ clk_put(pclk);
+
+ spear_setup_timer();
+}
+
+struct sys_timer spear13xx_timer = {
+ .init = spear13xx_timer_init,
+};
--
1.7.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V6 00/10] Adding SPEAr13xx support
2011-03-01 11:27 [PATCH V6 00/10] Adding SPEAr13xx support Viresh Kumar
` (11 preceding siblings ...)
2011-03-28 5:53 ` [PATCH V6 02/10 resend] SPEAr13xx: Add machine specific src files Viresh Kumar
@ 2011-05-27 6:15 ` viresh kumar
12 siblings, 0 replies; 14+ messages in thread
From: viresh kumar @ 2011-05-27 6:15 UTC (permalink / raw)
To: linux-arm-kernel
On 03/01/2011 04:57 PM, Viresh KUMAR wrote:
> This patchset adds support for SPEAr13xx machine family. Currently support
> for to machines SPEAr1300 & SPEAr1310 are added.
>
> Note: These patches were earlier sent as part of a larger patchset:
> "Updating SPEAr Support"
>
> Now it is divided into smaller patchsets. In order to apply these patches
> cleanly following order of patchsets must be maintained.
> - SPEAr3xx & SPEAr6xx Fixes
> - SPEAr3xx & SPEAr6xx: Single Image solution and padmux updates
> - Adding SPEAr13xx support
> - Adding devices support for all spear machines
> - Clock Framework & CPU Freq Updates
>
Russell,
I am removing this patchset from your tracker as it can't be pushed as it is.
Will submit new patches after updating stuff.
--
viresh
^ permalink raw reply [flat|nested] 14+ messages in thread