is there the sample for how to use the tcm on userspace ?

is there the sample for how to use the tcm on userspace ?

[Linus Walleij]

On 05/31/2011 04:18 AM, Jello huang wrote:
>   I have readed the tcm.txt but do not get the point. So do i need to
> write char device for the dtcm  or itcm ,then mmap to userspace
> through the char device .
>    

The interface is not designed to be used from userspace,
explain your usecase so I have a chance to understand why
you want to do such a thing.

Yours,
Linus Walleij

is there the sample for how to use the tcm on userspace ?

[Linus Walleij]

On 05/31/2011 10:35 AM, Jello huang wrote:
> HI linus,some critical code(for solve the real time problem)  need to 
> use itcm and dtcm from userspace.So i need design the interface to the 
> userspace app

Hm OK that seems like a good reason to have it available.

But I have no good suggestion of a suitable userspace interface :-(

Maybe the mailing list have some examples of how to use on-chip
memory like SRAM or TCM from userspace?

Linus Walleij

is there the sample for how to use the tcm on userspace ?

[Linus Walleij]

On 05/31/2011 11:35 AM, Jello huang wrote:
> It is easy to define the interface .But
> on ARM11 (ARM10?):
>
>     CPU
>      |
>     MMU
>     / \
> Cache TCM
>  |
> External memory interface

This is how all TCM works, it's behind the MMU but you can *also*
move it in physical address space.

> If we use TCM from userspace whether it directly use  TCM or it need 
> through MMU

You need to get hold of the memory somehow, but there is code in
the kernel managing it as a memory pool, so you need a userspace
interface to tcm_alloc() and tcm_free() and the resulting handles.

> And how much benefit we can get when we use the SDRAM or TCM from 
> usespace.

Define benefit, plus this depends on the bus and cache topology and
frequency of your system.

Frank Rowand presented a very compelling case for using on-chip
memory in the critical latency paths to avoid cache stalls on SMP
systems:
http://www.elinux.org/images/d/dd/Elc2011_rowand.pdf

However my TCM interface is not yet SMP aware. I was planning
to try to fix it for the PB11MPcore (which has per-cpu TCM!) someday
as an interesting exercise. But that depend on time and planning etc.

Yours,
Linus Walleij