From: zecke@selfish.org (Holger Freyther)
To: linux-arm-kernel@lists.infradead.org
Subject: TI-Davinci 6446 oops on interrupts
Date: Fri, 10 Jun 2011 20:47:18 +0200 [thread overview]
Message-ID: <4DF266B6.6090303@selfish.org> (raw)
In-Reply-To: <alpine.LFD.2.02.1106061719290.13964@ionos>
On 06/06/2011 05:25 PM, Thomas Gleixner wrote:
> On Mon, 6 Jun 2011, Holger Freyther wrote:
>> On 06/06/2011 04:54 PM, Thomas Gleixner wrote:
>>
>> and both interrupts should be on REG1.. so for IRQ56 it looks like this method
>> is entered with bogus data. Again, I have no idea about the underlying code,
>> but could there be an issue with chained irq and the GC IRC code?
>
> Crap, yes. The code which does the chained handler setup overwrites
> chip_data.
Hi Thomas,
I think the for loop above the one that was patched has the same kind of issue
(changing the irq_chip_data)? One needs to have a dm365.c for this code to
become active though.
In general what do you think about a patch like the one below, it is at least
boot tested on a qemu-system-i386.
next prev parent reply other threads:[~2011-06-10 18:47 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-06 12:41 TI-Davinci 6446 oops on interrupts Holger Freyther
2011-06-06 13:40 ` Holger Hans Peter Freyther
2011-06-06 14:54 ` Thomas Gleixner
2011-06-06 15:10 ` Holger Freyther
2011-06-06 15:25 ` Thomas Gleixner
2011-06-06 15:32 ` Holger Freyther
2011-06-06 21:31 ` Thomas Gleixner
2011-06-06 22:50 ` Kevin Hilman
2011-06-07 18:13 ` Nori, Sekhar
2011-06-07 22:59 ` Thomas Gleixner
2011-06-10 18:47 ` Holger Freyther [this message]
2011-06-06 14:49 ` Thomas Gleixner
2011-06-06 16:32 ` Russell King - ARM Linux
2011-06-06 17:45 ` Holger Freyther
2011-06-06 17:50 ` Thomas Gleixner
2011-06-06 21:30 ` Thomas Gleixner
2011-06-06 16:30 ` Russell King - ARM Linux
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