From: robherring2@gmail.com (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/6] ARM: realview: ensure visibility of writes during reset
Date: Mon, 08 Aug 2011 16:16:17 -0500 [thread overview]
Message-ID: <4E405221.7050800@gmail.com> (raw)
In-Reply-To: <1312823424-9654-3-git-send-email-will.deacon@arm.com>
On 08/08/2011 12:10 PM, Will Deacon wrote:
> The various reset routines in mach-realview rely on an FPGA to
> power-cycle the board after writing some magic runes to memory-mapped
> registers.
>
> This patch adds a dsb() following the writes, so that they become
> visible before we mdelay(1000) in the arch_reset code. Without this
> patch, the timeout would expire sporadically, causing the reset to fail.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm/mach-realview/include/mach/system.h | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
> index a30f2e3..6657ff2 100644
> --- a/arch/arm/mach-realview/include/mach/system.h
> +++ b/arch/arm/mach-realview/include/mach/system.h
> @@ -44,6 +44,7 @@ static inline void arch_reset(char mode, const char *cmd)
> */
> if (realview_reset)
> realview_reset(mode);
> + dsb();
Wouldn't it be better to do this globally.
Rob
next prev parent reply other threads:[~2011-08-08 21:16 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-08 17:10 [PATCH 0/6] Miscellaneous patches for 3.1 and 3.2 Will Deacon
2011-08-08 17:10 ` [PATCH 1/6] ARM: vexpress: determine active tile site before reading tile ID Will Deacon
2011-08-08 17:10 ` [PATCH 2/6] ARM: realview: ensure visibility of writes during reset Will Deacon
2011-08-08 21:16 ` Rob Herring [this message]
2011-08-09 8:32 ` Will Deacon
2011-08-08 17:10 ` [PATCH 3/6] ARM: twd: register clockevents device before enabling PPI Will Deacon
2011-08-08 18:19 ` Marc Zyngier
2011-08-08 17:10 ` [PATCH 4/6] ARM: smp: set thread_info->cpu to hardware CPU number for boot thread Will Deacon
2011-08-08 17:33 ` Stephen Boyd
2011-08-08 18:14 ` Will Deacon
2011-08-08 20:02 ` Russell King - ARM Linux
2011-08-08 20:25 ` Will Deacon
2011-08-09 11:48 ` Sergei Shtylyov
2011-08-09 12:13 ` Will Deacon
2011-08-08 17:10 ` [PATCH 5/6] ARM: cache: detect VIPT aliasing I-cache on ARMv6 Will Deacon
2011-08-08 17:10 ` [PATCH 6/6] ARM: cache: detect PIPT I-cache using CTR Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4E405221.7050800@gmail.com \
--to=robherring2@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).