[RFC PATCH 00/15] ARM: perf: support multiple PMUs

[RFC PATCH 00/15] ARM: perf: support multiple PMUs

[Mark Rutland]

System (AKA nest or uncore) PMUs exist on devices which are not affine
to a single CPU. They usually cannot be directly associated with
individual tasks and are asynchronous with respect to the current
execution. Examples of devices which could have system PMUs include L2
cache controllers, GPUs and memory buses.

The following patch series refactors the ARM PMU backend, enabling
new PMUs to reuse the existing code. This should allow for system PMUs
to be supported in future. Further work will be required to get perf to
fully understand system PMUs, but this provides something usable.

The framework is intended to be used by system PMUs which hang off core
platform components (e.g. L2 cache, AXI bus). If a device is complex
enough or separate enough from core functionality to have its own
driver, it should implement its own PMU handling using the core perf
API directly.

The first patch ("perf: provide PMU when initing events") is currently
sitting in the tip tree, but as it's required for event initialization
to function (and hence for the PMU to be usable), it's provided here
for convenience.

The series is based on Will Deacon's perf-updates branch at:
	git://linux-arm.org/linux-2.6-wd.git perf-updates

An example driver using the framework (supporting the PMU present in
L220/PL310 level 2 cache controllers) can be found at:
	git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wip

Any comments would be welcome.

Thanks,
Mark.

Mark Rutland (15):
  perf: provide PMU when initing events
  ARM: perf: only register a CPU PMU when present
  ARM: perf: clean up event group validation
  ARM: perf: remove active_mask
  ARM: perf: move active_events into struct arm_pmu
  ARM: perf: move platform device to struct arm_pmu
  ARM: perf: indirect access to cpu_hw_events
  ARM: perf: remove unnecessary armpmu->stop
  ARM: perf: lock PMU registers per-CPU
  ARM: perf: add type field to struct arm_pmu
  ARM: perf: refactor event mapping
  ARM: perf: add support for multiple PMUs
  ARM: perf: remove event limit from pmu_hw_events
  ARM: perf: remove cpu-related misnomers
  ARM: perf: move arm_pmu into <asm/pmu.h>

 arch/arm/include/asm/pmu.h          |   64 +++++++
 arch/arm/kernel/perf_event.c        |  318 +++++++++++++++++------------------
 arch/arm/kernel/perf_event_v6.c     |   73 ++++++---
 arch/arm/kernel/perf_event_v7.c     |   74 +++++---
 arch/arm/kernel/perf_event_xscale.c |   76 +++++----
 kernel/events/core.c                |    4 +-
 6 files changed, 359 insertions(+), 250 deletions(-)

[RFC PATCH 00/15] ARM: perf: support multiple PMUs

[Mark Rutland]

Hi all,

Sorry for the spam.

Evidently git send-email doesn't automatically split mboxes.

I'll resend this in a more manageable form.

Thanks,
Mark.

[RFC PATCH 00/15] ARM: perf: support multiple PMUs

[Mark Rutland]

System (AKA nest or uncore) PMUs exist on devices which are not affine
to a single CPU. They usually cannot be directly associated with
individual tasks and are asynchronous with respect to the current
execution. Examples of devices which could have system PMUs include L2
cache controllers, GPUs and memory buses.

The following patch series refactors the ARM PMU backend, enabling
new PMUs to reuse the existing code. This should allow for system PMUs
to be supported in future. Further work will be required to get perf to
fully understand system PMUs, but this provides something usable.

The framework is intended to be used by system PMUs which hang off core
platform components (e.g. L2 cache, AXI bus). If a device is complex
enough or separate enough from core functionality to have its own
driver, it should implement its own PMU handling using the core perf
API directly.

The first patch ("perf: provide PMU when initing events") is currently
sitting in the tip tree, but as it's required for event initialization
to function (and hence for the PMU to be usable), it's provided here
for convenience.

The series is based on Will Deacon's perf-updates branch at:
	git://linux-arm.org/linux-2.6-wd.git perf-updates

An example driver using the framework (supporting the PMU present in
L220/PL310 level 2 cache controllers) can be found at:
	git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wip

Any comments would be welcome.

Thanks,
Mark.

Mark Rutland (15):
  perf: provide PMU when initing events
  ARM: perf: only register a CPU PMU when present
  ARM: perf: clean up event group validation
  ARM: perf: remove active_mask
  ARM: perf: move active_events into struct arm_pmu
  ARM: perf: move platform device to struct arm_pmu
  ARM: perf: indirect access to cpu_hw_events
  ARM: perf: remove unnecessary armpmu->stop
  ARM: perf: lock PMU registers per-CPU
  ARM: perf: add type field to struct arm_pmu
  ARM: perf: refactor event mapping
  ARM: perf: add support for multiple PMUs
  ARM: perf: remove event limit from pmu_hw_events
  ARM: perf: remove cpu-related misnomers
  ARM: perf: move arm_pmu into <asm/pmu.h>

 arch/arm/include/asm/pmu.h          |   64 +++++++
 arch/arm/kernel/perf_event.c        |  318 +++++++++++++++++------------------
 arch/arm/kernel/perf_event_v6.c     |   73 ++++++---
 arch/arm/kernel/perf_event_v7.c     |   74 +++++---
 arch/arm/kernel/perf_event_xscale.c |   76 +++++----
 kernel/events/core.c                |    4 +-
 6 files changed, 359 insertions(+), 250 deletions(-)

[RFC PATCH 00/15] ARM: perf: support multiple PMUs

[Jamie Iles]

Hi Mark,

On Mon, Aug 15, 2011 at 02:55:01PM +0100, Mark Rutland wrote:
> System (AKA nest or uncore) PMUs exist on devices which are not affine
> to a single CPU. They usually cannot be directly associated with
> individual tasks and are asynchronous with respect to the current
> execution. Examples of devices which could have system PMUs include L2
> cache controllers, GPUs and memory buses.
> 
> The following patch series refactors the ARM PMU backend, enabling
> new PMUs to reuse the existing code. This should allow for system PMUs
> to be supported in future. Further work will be required to get perf to
> fully understand system PMUs, but this provides something usable.
> 
> The framework is intended to be used by system PMUs which hang off core
> platform components (e.g. L2 cache, AXI bus). If a device is complex
> enough or separate enough from core functionality to have its own
> driver, it should implement its own PMU handling using the core perf
> API directly.

Looks like a nice series to me.

Reviewed-by: Jamie Iles <jamie@jamieiles.com>

Jamie

[RFC PATCH 00/15] ARM: perf: support multiple PMUs

[Ashwin Chaugule]

>> -----Original Message-----
>> From: Mark Rutland
>> System (AKA nest or uncore) PMUs exist on devices which are not affine
>> to a single CPU. They usually cannot be directly associated with
>> individual tasks and are asynchronous with respect to the current
>> execution. Examples of devices which could have system PMUs include L2
>> cache controllers, GPUs and memory buses.
>>
>> The following patch series refactors the ARM PMU backend, enabling
>> new PMUs to reuse the existing code. This should allow for system PMUs
>> to be supported in future. Further work will be required to get perf to
>> fully understand system PMUs, but this provides something usable.
>>
>> The framework is intended to be used by system PMUs which hang off core
>> platform components (e.g. L2 cache, AXI bus). If a device is complex
>> enough or separate enough from core functionality to have its own
>> driver, it should implement its own PMU handling using the core perf
>> API directly.
>>
>> The first patch ("perf: provide PMU when initing events") is currently
>> sitting in the tip tree, but as it's required for event initialization
>> to function (and hence for the PMU to be usable), it's provided here
>> for convenience.
>>
>> The series is based on Will Deacon's perf-updates branch at:
>> 	git://linux-arm.org/linux-2.6-wd.git perf-updates
>>
>> An example driver using the framework (supporting the PMU present in
>> L220/PL310 level 2 cache controllers) can be found at:
>> 	git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wip
>>
>> Any comments would be welcome.
>>
>> Thanks,
>> Mark.
>

Other than the comments on patch [05/15] and [08/15], this series looks
good to me !

Reviewed-by: Ashwin Chaugule <ashwinc@codeaurora.org>


-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 00/15] ARM: perf: support multiple PMUs

[Will Deacon]

On Mon, Aug 22, 2011 at 08:04:50PM +0100, Ashwin Chaugule wrote:
> 
> Other than the comments on patch [05/15] and [08/15], this series looks
> good to me !
> 
> Reviewed-by: Ashwin Chaugule <ashwinc@codeaurora.org>

Cracking. Once -rc3 has landed I'll merge this into my perf-updates branch
(since some of my PMU refactoring will conflict with fixes going in for -rc3).

Thanks,

Will

Fwd: [RFC PATCH 00/15] ARM: perf: support multiple PMUs

[Srinidhi Kasagar]

Hello Marc/Will,

[...]

> Subject: [RFC PATCH 00/15] ARM: perf: support multiple PMUs
> ------------------------
> 
> From: Mark Rutland <mark.rutland at arm.com<mailto:mark.rutland@arm.com>>
> Date: Mon, Aug 15, 2011 at 7:12 PM
> To: linux-arm-kernel at lists.infradead.org

[...]

> System (AKA nest or uncore) PMUs exist on devices which are not affine
> to a single CPU. They usually cannot be directly associated with
> individual tasks and are asynchronous with respect to the current
> execution. Examples of devices which could have system PMUs include L2
> cache controllers, GPUs and memory buses.
> 
> The following patch series refactors the ARM PMU backend, enabling
> new PMUs to reuse the existing code. This should allow for system PMUs
> to be supported in future. Further work will be required to get perf to
> fully understand system PMUs, but this provides something usable.
> 
> The framework is intended to be used by system PMUs which hang off core
> platform components (e.g. L2 cache, AXI bus). If a device is complex
> enough or separate enough from core functionality to have its own
> driver, it should implement its own PMU handling using the core perf
> API directly.
> 
> The first patch ("perf: provide PMU when initing events") is currently
> sitting in the tip tree, but as it's required for event initialization
> to function (and hence for the PMU to be usable), it's provided here
> for convenience.
> 
> The series is based on Will Deacon's perf-updates branch at:
>        git://linux-arm.org/linux-2.6-wd.git perf-updates
> 
> An example driver using the framework (supporting the PMU present in
> L220/PL310 level 2 cache controllers) can be found at:
>        git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wip
> 
Do you still maintain this tree? Looks it is empty. I'm wondering if
we can make use of this to instrument the PMU counters of L2/pl310.

/srinidhi 

Fwd: [RFC PATCH 00/15] ARM: perf: support multiple PMUs

[Will Deacon]

On Wed, Jun 13, 2012 at 12:43:27PM +0100, Srinidhi Kasagar wrote:
> > The series is based on Will Deacon's perf-updates branch at:
> >        git://linux-arm.org/linux-2.6-wd.git perf-updates
> > 
> > An example driver using the framework (supporting the PMU present in
> > L220/PL310 level 2 cache controllers) can be found at:
> >        git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wip
> > 
> Do you still maintain this tree? Looks it is empty. I'm wondering if
> we can make use of this to instrument the PMU counters of L2/pl310.

There's an old branch here, but this stuff is pretty bit-rotted and needs
reworking as part of the big.LITTLE support:

http://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=shortlog;h=refs/heads/perf/l2x0

Will

Fwd: [RFC PATCH 00/15] ARM: perf: support multiple PMUs

[Srinidhi Kasagar]

On Wed, Jun 13, 2012 at 19:02:14 +0200, Will Deacon wrote:
> On Wed, Jun 13, 2012 at 12:43:27PM +0100, Srinidhi Kasagar wrote:
> > > The series is based on Will Deacon's perf-updates branch at:
> > >        git://linux-arm.org/linux-2.6-wd.git perf-updates
> > > 
> > > An example driver using the framework (supporting the PMU present in
> > > L220/PL310 level 2 cache controllers) can be found at:
> > >        git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wip
> > > 
> > Do you still maintain this tree? Looks it is empty. I'm wondering if
> > we can make use of this to instrument the PMU counters of L2/pl310.
> 
> There's an old branch here, but this stuff is pretty bit-rotted and needs
> reworking as part of the big.LITTLE support:
> 
> http://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=shortlog;h=refs/heads/perf/l2x0

Thanks, will look at it.

/srinidhi