MX28 fec clock frequency

MX28 fec clock frequency

[Peter Rusko]

Hi all,

I'm trying to get the fec clock frequency on the i.MX28 processor. I0
need it for a PTP clock and it seems that I get a wrong value:
clk_get_rate returns 151578947.

I've tried to get all the clock rates up to the crystal clock through
the parent field and got these results:

CLKRATE: 151578947
CLKRATE: 151578947
CLKRATE: 454736842
CLKRATE: 454736842
CLKRATE: 480000000
CLKRATE: 24000000

The first one is the fec_enet_private's clock and then the parents. Are
these correct values?

I'm currently using the master branch from git.pengutronix.de/git/imx

-- 
Rusk? P?ter
Fejleszt?m?rn?k

Prolan Zrt. / Prolan Co.
Hungary 2011 Budakal?sz, Szentendrei ?t 1-3.
Tel./Phone: +36 20 954 3118
Fax: +36 26 540 420
E-mail: rusko.peter at prolan.hu
Web: www.prolan.hu
Timezone:CET

MX28 fec clock frequency

[Shawn Guo]

Hi Peter,

On Fri, Jan 06, 2012 at 12:08:51PM +0100, Peter Rusko wrote:
> Hi all,
> 
> I'm trying to get the fec clock frequency on the i.MX28 processor. I0
> need it for a PTP clock and it seems that I get a wrong value:
> clk_get_rate returns 151578947.
> 

The ptp clock (CLK_ENET_TIME) was missed from the initial imx28 clock
support.  The fec_clk which is one child of hbus_clk (151 MHz) is
taken as MDIO clock in fec driver.

-- 
Regards,
Shawn

MX28 fec clock frequency

[Peter Rusko]

On 2012-01-08 04:32, Shawn Guo wrote:
> Hi Peter,
>
> On Fri, Jan 06, 2012 at 12:08:51PM +0100, Peter Rusko wrote:
>> Hi all,
>>
>> I'm trying to get the fec clock frequency on the i.MX28 processor. I0
>> need it for a PTP clock and it seems that I get a wrong value:
>> clk_get_rate returns 151578947.
>>
>
> The ptp clock (CLK_ENET_TIME) was missed from the initial imx28 clock
> support.  The fec_clk which is one child of hbus_clk (151 MHz) is
> taken as MDIO clock in fec driver.
>

I'm working on a ptp driver now and I can't deal with the clock.

I've added the CLK_ENET_TIME clock and set it to 40MHz. It should give a
25ns period for the counter in ptp. However the ptp clock is too slow.

If i increase the number (up to the maximum, which is 0x7f), the clock
is still slower then normal. It's like the CLK_ENET_TIME frequency is
less then I think. What can be the problem?

I've attached a patch.

Regards,
-- 
Rusk? P?ter
Fejleszt?m?rn?k

Prolan Zrt. / Prolan Co.
Hungary 2011 Budakal?sz, Szentendrei ?t 1-3.
Tel./Phone: +36 20 954 3118
Fax: +36 26 540 420
E-mail: rusko.peter at prolan.hu
Web: www.prolan.hu
Timezone:CET
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MX28 fec clock frequency

[Shawn Guo]

On Mon, Jan 09, 2012 at 03:07:44PM +0100, Peter Rusko wrote:
> +	/* ENET_CLK setup */
> +	enet_clk.set_parent(&enet_clk, &pll0_clk);
> +	__raw_writel(BF_CLKCTRL_ENET_DIV(12),
> +		       	CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
> +
I'm not sure it's causing the problem you are seeing.  But from i.MX28
spec, it seems that bit BUSY_TIME of register HW_CLKCTRL_ENET should
be polled for new divider setting?

-- 
Regards,
Shawn

MX28 fec clock frequency

[Peter Rusko]

> I'm not sure it's causing the problem you are seeing.  But from i.MX28
> spec, it seems that bit BUSY_TIME of register HW_CLKCTRL_ENET should
> be polled for new divider setting?
>

Thank you, I've added the check, but unfortunately it didn't help :(

-- 
Rusk? P?ter
Fejleszt?m?rn?k

Prolan Zrt. / Prolan Co.
Hungary 2011 Budakal?sz, Szentendrei ?t 1-3.
Tel./Phone: +36 20 954 3118
Fax: +36 26 540 420
E-mail: rusko.peter at prolan.hu
Web: www.prolan.hu
Timezone:CET

MX28 fec clock frequency

[Shawn Guo]

On Tue, Jan 10, 2012 at 02:08:31PM +0100, Peter Rusko wrote:
> >I'm not sure it's causing the problem you are seeing.  But from i.MX28
> >spec, it seems that bit BUSY_TIME of register HW_CLKCTRL_ENET should
> >be polled for new divider setting?
> >
> 
> Thank you, I've added the check, but unfortunately it didn't help :(
> 
Another point worth checking is bit field ATIME_INC of register
HW_ENET_MAC_ATIME_INC.  It should be 25 if your CLK_ENET_TIME runs
at 40 MHz.

-- 
Regards,
Shawn

MX28 fec clock frequency

[Peter Rusko]

On 2012-01-10 15:00, Shawn Guo wrote:
> Another point worth checking is bit field ATIME_INC of register
> HW_ENET_MAC_ATIME_INC.  It should be 25 if your CLK_ENET_TIME runs
> at 40 MHz.
>

No, that was set correctly. Finally, I've found my mistake. I've 
overwritten the other bits when writing the divider so xtal clock was 
selected automatically.
Silly little mistake, isn't it? :) Anyway, thank you for your help.

-- 
Rusk? P?ter
Fejleszt?m?rn?k

Prolan Zrt. / Prolan Co.
Hungary 2011 Budakal?sz, Szentendrei ?t 1-3.
Tel./Phone: +36 20 954 3118
Fax: +36 26 540 420
E-mail: rusko.peter at prolan.hu
Web: www.prolan.hu
Timezone:CET