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Tue, 03 Dec 2024 17:59:08 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id CD3EC4008D; Tue, 3 Dec 2024 17:57:40 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A8F84270D6D; Tue, 3 Dec 2024 17:55:35 +0100 (CET) Received: from [10.129.178.212] (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 3 Dec 2024 17:55:34 +0100 Message-ID: <4a56d133-0173-4ad5-8d36-70d538c88ba7@foss.st.com> Date: Tue, 3 Dec 2024 17:55:28 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] dt-bindings: PCI: Add STM32MP25 PCIe root complex bindings To: Manivannan Sadhasivam CC: , , , , , , , , , , , , , , , , References: <20241126155119.1574564-1-christian.bruel@foss.st.com> <20241126155119.1574564-2-christian.bruel@foss.st.com> <20241203133434.2qbohwi3wrjjja5a@thinkpad> Content-Language: en-US From: Christian Bruel In-Reply-To: <20241203133434.2qbohwi3wrjjja5a@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.129.178.212] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_085930_435118_12B899EC X-CRM114-Status: GOOD ( 15.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/3/24 14:34, Manivannan Sadhasivam wrote: > On Tue, Nov 26, 2024 at 04:51:15PM +0100, Christian Bruel wrote: >> Document the bindings for STM32MP25 PCIe Controller configured in >> root complex mode. >> >> Supports 4 legacy interrupts and MSI interrupts from the ARM >> GICv2m controller. >> >> STM32 PCIe may be in a power domain which is the case for the STM32MP25 >> based boards. >> >> Supports wake# from wake-gpios >> >> Signed-off-by: Christian Bruel >> --- >> .../bindings/pci/st,stm32-pcie-common.yaml | 45 +++++++++ >> .../bindings/pci/st,stm32-pcie-host.yaml | 99 +++++++++++++++++++ >> 2 files changed, 144 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml >> create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml >> new file mode 100644 >> index 000000000000..479c03134da3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml >> @@ -0,0 +1,45 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: STM32MP25 PCIe RC/EP controller >> + >> +maintainers: >> + - Christian Bruel >> + >> +description: >> + STM32MP25 PCIe RC/EP common properties >> + >> +properties: >> + clocks: >> + maxItems: 1 >> + description: PCIe system clock >> + >> + resets: >> + maxItems: 1 >> + >> + phys: >> + maxItems: 1 >> + >> + phy-names: >> + const: pcie-phy >> + >> + power-domains: >> + maxItems: 1 >> + >> + access-controllers: >> + maxItems: 1 >> + >> + reset-gpios: >> + description: GPIO controlled connection to PERST# signal >> + maxItems: 1 >> + >> +required: >> + - clocks >> + - resets >> + - phys >> + - phy-names >> + >> +additionalProperties: true >> diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml >> new file mode 100644 >> index 000000000000..18083cc69024 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml >> @@ -0,0 +1,99 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: STM32MP25 PCIe root complex driver >> + >> +maintainers: >> + - Christian Bruel >> + >> +description: >> + PCIe root complex controller based on the Synopsys DesignWare PCIe core. >> + >> +allOf: >> + - $ref: /schemas/pci/snps,dw-pcie.yaml# >> + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# >> + >> +select: >> + properties: >> + compatible: >> + const: st,stm32mp25-pcie-rc >> + required: >> + - compatible >> + >> +properties: >> + compatible: >> + const: st,stm32mp25-pcie-rc >> + >> + reg: >> + items: >> + - description: Data Bus Interface (DBI) registers. >> + - description: PCIe configuration registers. >> + >> + reg-names: >> + items: >> + - const: dbi >> + - const: config >> + >> + num-lanes: >> + const: 1 >> + >> + msi-parent: >> + maxItems: 1 >> + >> + wake-gpios: >> + description: GPIO controlled connection to WAKE# input signal >> + maxItems: 1 >> + >> + wakeup-source: true >> + >> +dependentRequired: >> + wakeup-source: [ wake-gpios ] >> + >> +required: >> + - interrupt-map >> + - interrupt-map-mask >> + - ranges >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + #include >> + #include >> + >> + pcie@48400000 { >> + compatible = "st,stm32mp25-pcie-rc"; >> + device_type = "pci"; >> + num-lanes = <1>; >> + reg = <0x48400000 0x400000>, >> + <0x10000000 0x10000>; >> + reg-names = "dbi", "config"; >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0 0x10010000 0x10010000 0 0x10000>, > > PCI address of I/O region should start from address 0x00000000. > ok, thanks ! > Also use hex notation for all values. > > - Mani >