From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2FB05D2F7CC for ; Wed, 16 Oct 2024 21:51:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Date:To:Cc:From:Subject: References:In-Reply-To:Content-Transfer-Encoding:MIME-Version:Content-Type: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Dw334JfBalbFiNBUqzFgiGsfSgeWq3HMDzKaKGNjlqI=; b=v1uizvza8qifuZdY1811UtXNF2 UpOamsGj4bGJuxbEXxtM2Wo9/GlTBY3BHTOVO4rfiM15n4F9maDN4FuGqhrd85ZfvCpWFK+PL58vE A9p7OCh6xX7d+EPsTKR4bRyoHYIND/gVJTsOAiz9rbJs/QVwO5si7lV9ah9xDU3MG4JScNDpR6lTV VmnR6Ln4pxve8iQDoAOeSYfBvWt4y9tdOh/4f3oRvAi+oliLkDGv5t9hqXGBbgab5AFkF8Xw+ClEs tIwqX+9MWsRMcgXWFnATGzDdAPd1YIvkHJrSgAueIoU01BiiE+K8Ru+x/jhkYF6HPdZehdbmB/U2l M0ITEqDQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t1BvT-0000000D5b7-0Gi9; Wed, 16 Oct 2024 21:51:27 +0000 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t1Bu2-0000000D5WS-1jxc for linux-arm-kernel@lists.infradead.org; Wed, 16 Oct 2024 21:49:59 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 9E9D1A4252E; Wed, 16 Oct 2024 21:49:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2FC69C4CEC5; Wed, 16 Oct 2024 21:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729115397; bh=Hp+H7yoAyapEdhvaBlQzGXZZGhKUy3jtoMpeNHH/Y0o=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=ab5xwJqainPvNFCX2PalKHOxzA3L3nK5zwFARgT7/XEdijZX9hA/UkoSQkW7mAhg7 d+GCqVvXl2YVMFIF6IQHziwyR5aQbcUH/Om7q9iPTziNPrO6mN4HclkwRDecstvltL PGbCqzvHo26Yka4ACeSDyJL7mGbTcsMmpnv8AXQ36QeRbTgTRsJ9cSZzJIqWLVanpl IRmnWcCWUUGWAuah2wOXkmrZT6F6tgPWmOp9yA96Al8enfsKSM+zVQUSkYfoSDLFlw a6q05U84twcZ+PLbdsOsZ5ToLR5vT8WtU61x+hrddn0ZtNeCqin6YLT1lOwGVjFbLR TgafhqGvGqgmw== Message-ID: <4c7956afc86ea05f07b25d98ffb5b80c.sboyd@kernel.org> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20241014-imx-clk-v1-v1-4-ee75876d3102@nxp.com> References: <20241014-imx-clk-v1-v1-0-ee75876d3102@nxp.com> <20241014-imx-clk-v1-v1-4-ee75876d3102@nxp.com> Subject: Re: [PATCH 4/4] clk: imx: fracn-gppll: fix pll power up From: Stephen Boyd Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan , Jacky Bai To: Abel Vesa , Aisheng Dong , Fabio Estevam , Michael Turquette , Peng Fan (OSS) , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo Date: Wed, 16 Oct 2024 14:49:55 -0700 User-Agent: alot/0.10 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241016_144958_545519_D71E98F2 X-CRM114-Status: GOOD ( 16.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Quoting Peng Fan (OSS) (2024-10-14 02:11:25) > From: Peng Fan >=20 > To i.MX93 which features dual Cortex-A55 cores and DSU, when using > writel_relaxed to write value to PLL registers, the value might be > buffered. To make sure the value has been written into the hardware, > using readl to read back the register could make sure the value > written into hardware. >=20 > current PLL power up flow can be simplified as below: > 1. writel_relaxed to set the PLL POWERUP bit; > 2. readl_poll_timeout to check the PLL lock bit: > a). timeout =3D ktime_add_us(ktime_get(), timeout_us); > b). readl the pll the lock reg; > c). check if the pll lock bit ready > d). check if timeout >=20 > But in some corner cases, both the write in step 1 and read in > step 2 will be blocked by other bus transaction in the SoC for a > long time, saying the value into real hardware is just before step b). > That means the timeout counting has begins for quite sometime since > step a), but value still not written into real hardware until bus > released just at a point before step b). >=20 > Then there maybe chances that the pll lock bit is not ready > when readl done but the timeout happens. readl_poll_timeout will > err return due to timeout. To avoid such unexpected failure, > read back the reg to make sure the write has been done in HW > reg. >=20 > Introduce fence_write for this purpose. Please just write out the readl() instead of introducing a bespoke macro that isn't generic for all architectures.