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Sat, 2 May 2026 00:15:56 -0500 Received: from [10.24.73.74] (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 6425Frcn705867; Sat, 2 May 2026 00:15:53 -0500 Message-ID: <4ce9f13a-b17f-4149-ade8-57519f4a4752@ti.com> Date: Sat, 2 May 2026 10:48:14 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird CC: , , , , , , , , , , Subject: Re: [PATCH 1/2] PCI: cadence: Ensure that cdns_pcie_host_wait_for_link() waits 100 ms after link up To: Hans Zhang <18255117159@163.com> References: <20260501153553.66382-1-18255117159@163.com> <20260501153553.66382-2-18255117159@163.com> Content-Language: en-US From: Siddharth Vadapalli In-Reply-To: <20260501153553.66382-2-18255117159@163.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000015:EE_|CY8PR10MB7220:EE_ X-MS-Office365-Filtering-Correlation-Id: 40ec5ca9-7d88-40e6-1720-08dea809e552 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700016|82310400026|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eFltndShEC7JM4E8AezFGMXXL68G+BjbPl38QbWROyryXTGmu6eDDQ9QkXvKy0XkFCHzwtxOZDjFK+EKT2K2AkWRg4JALwmVFJuLpijU2+ftHk+q4erMKwIOjQiJbDq8YUQUVS9z53hSGfvu+fDDW3QyOs4ZQHDMwmHVnaltZYScQYMAru+7DVY7Xyd+LIEk8P4knl94Pg788R9PZX0wM357qMaYElRda8+fq8p5b/PFI2bFORDA/t47GzPA0vmcxGKz5P+irkSZ5JNzFy8KTUCAhaymemCdZlyq484wDvHTZ5Tn0uv/xJl1jBm9Fu4fA0We2k0uj7R6FbJsgGSUeH3yc34zVIVMwQ0uTfBNFrt8IuW10tyfe4i/ptKAyDBNLP4Vv5qXZu7FyJX5Y6y/z+q9V9EQW9Aac4o9cELvcOWHfJLqzItkkDR5DKQkfjJ2 X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2026 05:15:58.7816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40ec5ca9-7d88-40e6-1720-08dea809e552 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000015.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR10MB7220 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260501_221614_893711_92B26FA5 X-CRM114-Status: GOOD ( 21.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 01/05/26 21:05, Hans Zhang wrote: > As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds > greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link > training completes before sending a Configuration Request. > > Add a new 'max_link_speed' field in struct cdns_pcie to record the > maximum supported (or currently configured) link speed of the controller. > > In cdns_pcie_host_wait_for_link(), after the link is reported as up, > insert a 100 ms delay if max_link_speed > 2 (i.e., > 5 GT/s). This > implements the required delay at the common Cadence host layer. > > Currently max_link_speed is zero-initialized, so the delay is not yet > active. Glue drivers must set max_link_speed appropriately to enable > the delay. This matches the approach taken for the Synopsys DWC > controller in commit 80dc18a0cba8d ("PCI: dwc: Ensure that > dw_pcie_wait_for_link() waits 100 ms after link up"). > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > .../pci/controller/cadence/pcie-cadence-host-common.c | 9 +++++++++ > drivers/pci/controller/cadence/pcie-cadence.h | 2 ++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c > index 2b0211870f02..d4ae762f423f 100644 > --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c > +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c > @@ -14,6 +14,7 @@ > > #include "pcie-cadence.h" > #include "pcie-cadence-host-common.h" > +#include "../../pci.h" > > #define LINK_RETRAIN_TIMEOUT HZ > > @@ -55,6 +56,14 @@ int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, > /* Check if the link is up or not */ > for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { > if (pcie_link_up(pcie)) { > + /* > + * As per PCIe r6.0, sec 6.6.1, a Downstream Port that > + * supports Link speeds greater than 5.0 GT/s, software > + * must wait a minimum of 100 ms after Link training > + * completes before sending a Configuration Request. > + */ > + if (pcie->max_link_speed > 2) > + msleep(PCIE_RESET_CONFIG_WAIT_MS); I think the above could be moved to cdns_pcie_host_start_link() as follows: diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c index 2b0211870f02..0f885dcbdb12 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -115,6 +115,15 @@ int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, if (!ret && rc->quirk_retrain_flag) ret = cdns_pcie_retrain(pcie, pcie_link_up); + /* + * As per PCIe r6.0, sec 6.6.1, a Downstream Port that + * supports Link speeds greater than 5.0 GT/s, software + * must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request. + */ + if (!ret && pcie->max_link_speed > 2) + msleep(PCIE_RESET_CONFIG_WAIT_MS); + return ret; } EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); This will avoid an additional and unnecessary delay when 'cdns_pcie_retrain()' retrains the link. Instead of checking for the link being up using "pcie_link_up(pcie)", checking for 'ret' being zero should also work (ret being zero indicates that the link is up). Since configuration space accesses will not be performed until cdns_pcie_host_start_link() completes executing, it should be safe to switch to the above implementation. > dev_info(dev, "Link up\n"); > return 0; > } [TRIMMED] Regards, Siddharth.