From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B494C3DA7F for ; Thu, 8 Aug 2024 02:07:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:MIME-Version: Content-Transfer-Encoding:Content-Type:References:In-Reply-To:Date:Cc:To:From :Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=OnyU4K9Xs3OQ6gjOrSz6jTsZs25qhB/EPzhnB51St3U=; b=DYEnJigeCiloc8XUVFE0u5l/mG O99164ZByI0/LEXJOArBtUjhxSF7e+q+cdRIKvjiuzPvyGcLvLCgc3DLMgs+5HSIaSXoFIyPk3vFK /8lMY96ktBTXUCqR5vwBiu5u3HUfjQd35dJPC6a7+/y7VURgmTiLUdV8nczWJDxqTfYVaCNTwyb0B UXKxVjlvJf7NyM6phJ+MnU2W6H5D20MpnGhZdamwRhYDzrBGXiEft8Cbed89IkR4WWN2g2Xe+2onb O+n9QGUhrpAQK6AdQT0vE7CewXlbgQAtzeSfqNrgEmp7vaOjxLu8NfzzIcUFq6bYmt4r3CInoSeAv 3u0PW63A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbsYT-00000006mtt-3rNw; Thu, 08 Aug 2024 02:07:05 +0000 Received: from pi.codeconstruct.com.au ([203.29.241.158] helo=codeconstruct.com.au) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbsXv-00000006mpO-128B for linux-arm-kernel@lists.infradead.org; Thu, 08 Aug 2024 02:06:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=codeconstruct.com.au; s=2022a; t=1723082789; bh=OnyU4K9Xs3OQ6gjOrSz6jTsZs25qhB/EPzhnB51St3U=; h=Subject:From:To:Cc:Date:In-Reply-To:References; b=LHsZlJgoxe2y22kAI9EN4j+HNry8kSr3WF2Od0kH5bmtymF7vLHaKSmj2xnzH6zc7 Vc3iX6jMT1QztIpxXfMFEJRVam4nLKamu1TDi/cmZMlfSptW9gtXRWBynGfLzvVDoV 98WI63bq6l72+k4JF6/Bk3+km79IHArILkFHmDvqp5mjMJma2EHn70Qf53yvkzLJCX 7AelvkqsrM7a4bdr5sAnpEMxGK3dp1QWQmgIADUKvrpK2ugsrnJhE1BqVPMhLpPJJJ 9ebml7Gr1q17RVD+8xpsyiSeySQmOBaP+JNv0gJMAZN5EiUcqr1V4Io4mQySZompv8 744nsHhAWMy8w== Received: from [192.168.68.112] (203-57-213-111.dyn.iinet.net.au [203.57.213.111]) by mail.codeconstruct.com.au (Postfix) with ESMTPSA id 8C20B66F97; Thu, 8 Aug 2024 10:06:28 +0800 (AWST) Message-ID: <4d26bde0bda7cb1d44958d967c4b0c2da5b2abc4.camel@codeconstruct.com.au> Subject: Re: [PATCH 2/2] dt-bindings: misc: aspeed,ast2400-cvic: Convert to DT schema From: Andrew Jeffery To: Krzysztof Kozlowski , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org Date: Thu, 08 Aug 2024 11:36:28 +0930 In-Reply-To: References: <20240802-dt-warnings-irq-aspeed-dt-schema-v1-0-8cd4266d2094@codeconstruct.com.au> <20240802-dt-warnings-irq-aspeed-dt-schema-v1-2-8cd4266d2094@codeconstruct.com.au> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4-2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240807_190631_525361_A1E0B48D X-CRM114-Status: GOOD ( 18.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2024-08-06 at 08:12 +0200, Krzysztof Kozlowski wrote: > On 02/08/2024 07:36, Andrew Jeffery wrote: > > Address warnings such as: > >=20 >=20 >=20 > > +description: > > + The Aspeed AST2400 and AST2500 SoCs have a controller that provides = interrupts > > + to the ColdFire coprocessor. It's not a normal interrupt controller = and it > > + would be rather inconvenient to create an interrupt tree for it, as = it > > + somewhat shares some of the same sources as the main ARM interrupt c= ontroller > > + but with different numbers. > > + > > + The AST2500 also supports a software generated interrupt. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - aspeed,ast2400-cvic > > + - aspeed,ast2500-cvic > > + - const: aspeed,cvic > > + > > + reg: > > + maxItems: 1 > > + > > + valid-sources: > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + description: > > + One cell, bitmap of support sources for the implementation. >=20 > maxItems: 1 > (and drop "One cell" - no need to repeat constraints in free form text) Ack to both. >=20 > BTW, for both bindings, I do not see any user in the kernel. Why is this > property needed in the DTS? Good question. This is a hangover from when benh was involved in the Aspeed kernel port. Given it's specified in the prose binding and the devicetrees contain the property I'll leaving it in for now, but I think it's something we could consider removing down the track. >=20 > > + > > + copro-sw-interrupts: > > + $ref: /schemas/types.yaml#/definitions/uint32-array >=20 > uint32? I do not see anywhere usage as an array. The in-kernel driver > explicitly reads just uint32. You're right, and in the context of the hardware an array doesn't make sense here. I'll switch it to a uint32. Thanks for the review. Andrew