[PATCH v3 0/7] Axiado AX3000 SoC and Evaluation Board Support

[PATCH v3 0/7] Axiado AX3000 SoC and Evaluation Board Support

[Harshit Shah]

This patch series adds initial support for the Axiado AX3000 SoC and its
evaluation board.

The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53
cores, secure vault, hardware firewall, and AI acceleration engines. This
initial support enables basic bring-up of the SoC and evaluation platform
with CPU, timer, UART, and I3C functionality.

The series begins by adding the "axiado" vendor prefix and compatible
strings for the SoC and board. It then introduces the device tree files
and minimal ARCH_AXIADO platform support in arm64.

Patch breakdown:
  - Patch 1 add the vendor prefix entry
  - Patch 2 document the SoC and board bindings
  - Patch 3 convert cdns,gpio.txt to gpio-cdns.yaml
  - Patch 4 add Axiado SoC family
  - Patch 5 add device tree for the ax3000 & ax3000-evk
  - Patch 6 add ARCH_AXIADO in defconfig
  - Patch 7 update MAINTAINERS file

Note: A few checkpatch.pl warnings appear due to DT binding conversions and
MAINTAINERS update. The binding conversion and includes were kept together in 
patch 3/7 due to their close relationship, but we are happy to split them if 
preferred.

Feedback and suggestions are welcome.

Signed-off-by: Harshit Shah <hshah@axiado.com>

To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Linus Walleij <linus.walleij@linaro.org>
To: Bartosz Golaszewski <brgl@bgdev.pl>
To: Arnd Bergmann <arnd@arndb.de>
To: Catalin Marinas <catalin.marinas@arm.com>
To: Will Deacon <will@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-gpio@vger.kernel.org
Cc: soc@lists.linux.dev
Cc: Jan Kotas <jank@cadence.com>

Signed-off-by: Harshit Shah <hshah@axiado.com>
---
Changes in v3:
- patch#3 
 - Update with the original filename
 - maitainer and property name updates
- patch#4
  - removed defconfig
- patch#5 
  - update nodes to alphabetical order, remove redudant nodes
  - add fix clock nodes
- patch#6 
  - enable ARCH_AXIADO in defconfig
- Link to v2: https://lore.kernel.org/r/20250615-axiado-ax3000-soc-and-evaluation-board-support-v2-0-341502d38618@axiado.com

Changes in v2:
- update patch#2 to fix the yamlint,dt_binding_check error
- update patch#6 to update path mentioned by kernel test robot
- Link to v1: https://lore.kernel.org/r/20250614-axiado-ax3000-soc-and-evaluation-board-support-v1-0-327ab344c16d@axiado.com

---
Harshit Shah (7):
      dt-bindings: vendor-prefixes: Add Axiado Corporation
      dt-bindings: arm: axiado: add AX3000 EVK compatible strings
      dt-bindings: gpio: gpio-cdns: convert to YAML
      arm64: add Axiado SoC family
      arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
      arm64: defconfig: enable the Axiado family
      MAINTAINERS: Add entry for Axiado

 Documentation/devicetree/bindings/arm/axiado.yaml  |  23 +
 .../devicetree/bindings/gpio/cdns,gpio.txt         |  43 --
 .../devicetree/bindings/gpio/cdns,gpio.yaml        |  80 ++++
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 MAINTAINERS                                        |   8 +
 arch/arm64/Kconfig.platforms                       |   6 +
 arch/arm64/boot/dts/Makefile                       |   1 +
 arch/arm64/boot/dts/axiado/Makefile                |   2 +
 arch/arm64/boot/dts/axiado/ax3000-evk.dts          |  79 ++++
 arch/arm64/boot/dts/axiado/ax3000.dtsi             | 488 +++++++++++++++++++++
 arch/arm64/configs/defconfig                       |   1 +
 11 files changed, 690 insertions(+), 43 deletions(-)
---
base-commit: 8c6bc74c7f8910ed4c969ccec52e98716f98700a
change-id: 20250614-axiado-ax3000-soc-and-evaluation-board-support-1b86b4a9daac

Best regards,
-- 
Harshit Shah <hshah@axiado.com>

[PATCH v3 1/7] dt-bindings: vendor-prefixes: Add Axiado Corporation

[Harshit Shah]

Link: https://axiado.com
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 5d2a7a8d3ac6c666c8b557c2ef385918e5e97bf9..5ada930c79e3b32ff1bf194ee66bb4bdb08d539e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -200,6 +200,8 @@ patternProperties:
     description: Shanghai Awinic Technology Co., Ltd.
   "^axentia,.*":
     description: Axentia Technologies AB
+  "^axiado,.*":
+    description: Axiado Corporation
   "^axis,.*":
     description: Axis Communications AB
   "^azoteq,.*":

-- 
2.25.1

Re: [PATCH v3 1/7] dt-bindings: vendor-prefixes: Add Axiado Corporation

[Rob Herring (Arm)]

On Mon, 23 Jun 2025 10:28:12 -0700, Harshit Shah wrote:
> Link: https://axiado.com
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v3 2/7] dt-bindings: arm: axiado: add AX3000 EVK compatible strings

[Harshit Shah]

Add device tree binding schema for Axiado platforms, specifically the
AX3000 SoC and its associated evaluation board. This binding will be
used for the board-level DTS files that support the AX3000 platforms.

Signed-off-by: Harshit Shah <hshah@axiado.com>
---
 Documentation/devicetree/bindings/arm/axiado.yaml | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/axiado.yaml b/Documentation/devicetree/bindings/arm/axiado.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..bfabe7b32e65fb06d1f4faecfad032219f95dfca
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/axiado.yaml
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/axiado.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axiado Platforms
+
+maintainers:
+  - Harshit Shah <hshah@axiado.com>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: AX3000 based boards
+        items:
+          - enum:
+              - axiado,ax3000-evk       # Axiado AX3000 Evaluation Board
+          - const: axiado,ax3000       # Axiado AX3000 SoC
+
+additionalProperties: true

-- 
2.25.1

Re: [PATCH v3 2/7] dt-bindings: arm: axiado: add AX3000 EVK compatible strings

[Krzysztof Kozlowski]

On 23/06/2025 19:28, Harshit Shah wrote:
> Add device tree binding schema for Axiado platforms, specifically the
> AX3000 SoC and its associated evaluation board. This binding will be
> used for the board-level DTS files that support the AX3000 platforms.
> 
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v3 3/7] dt-bindings: gpio: gpio-cdns: convert to YAML

[Harshit Shah]

Convert Cadence family GPIO controller bindings to DT schema.

Signed-off-by: Harshit Shah <hshah@axiado.com>
---
 .../devicetree/bindings/gpio/cdns,gpio.txt         | 43 ------------
 .../devicetree/bindings/gpio/cdns,gpio.yaml        | 80 ++++++++++++++++++++++
 2 files changed, 80 insertions(+), 43 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.txt b/Documentation/devicetree/bindings/gpio/cdns,gpio.txt
deleted file mode 100644
index 706ef00f5c64951bb29c79a5541db4397e8b2733..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/gpio/cdns,gpio.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-Cadence GPIO controller bindings
-
-Required properties:
-- compatible: should be "cdns,gpio-r1p02".
-- reg: the register base address and size.
-- #gpio-cells: should be 2.
-	* first cell is the GPIO number.
-	* second cell specifies the GPIO flags, as defined in
-		<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
-		and GPIO_ACTIVE_LOW flags are supported.
-- gpio-controller: marks the device as a GPIO controller.
-- clocks: should contain one entry referencing the peripheral clock driving
-	the GPIO controller.
-
-Optional properties:
-- ngpios: integer number of gpio lines supported by this controller, up to 32.
-- interrupts: interrupt specifier for the controllers interrupt.
-- interrupt-controller: marks the device as an interrupt controller. When
-	defined, interrupts, interrupt-parent and #interrupt-cells
-	are required.
-- interrupt-cells: should be 2.
-	* first cell is the GPIO number you want to use as an IRQ source.
-	* second cell specifies the IRQ type, as defined in
-		<dt-bindings/interrupt-controller/irq.h>.
-		Currently only level sensitive IRQs are supported.
-
-
-Example:
-	gpio0: gpio-controller@fd060000 {
-		compatible = "cdns,gpio-r1p02";
-		reg =<0xfd060000 0x1000>;
-
-		clocks = <&gpio_clk>;
-
-		interrupt-parent = <&gic>;
-		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
-
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..265bd62cb0887a860391d56b3154dcd8416c5d2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/cdns,gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence GPIO Controller
+
+maintainers:
+  - Jan Kotas <jank@cadence.com>
+
+properties:
+  compatible:
+    const: cdns,gpio-r1p02
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  ngpios:
+    minimum: 1
+    maximum: 32
+    description: Number of GPIO lines supported, maximum 32.
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+    description: |
+      - First cell is the GPIO line number.
+      - Second cell is flags as defined in <dt-bindings/gpio/gpio.h>,
+        only GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW supported.
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+    description: |
+      - First cell is the GPIO line number used as IRQ.
+      - Second cell is the trigger type, as defined in
+        <dt-bindings/interrupt-controller/irq.h>.
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - gpio-controller
+  - "#gpio-cells"
+
+if:
+  required: [interrupt-controller]
+then:
+  required:
+    - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    gpio0: gpio-controller@fd060000 {
+        compatible = "cdns,gpio-r1p02";
+        reg = <0xfd060000 0x1000>;
+        clocks = <&gpio_clk>;
+
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+        gpio-controller;
+        #gpio-cells = <2>;
+
+        interrupt-controller;
+        #interrupt-cells = <2>;
+    };

-- 
2.25.1

Re: [PATCH v3 3/7] dt-bindings: gpio: gpio-cdns: convert to YAML

[Krzysztof Kozlowski]

On 23/06/2025 19:28, Harshit Shah wrote:
> +$id: http://devicetree.org/schemas/gpio/cdns,gpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence GPIO Controller
> +
> +maintainers:
> +  - Jan Kotas <jank@cadence.com>
> +
> +properties:
> +  compatible:
> +    const: cdns,gpio-r1p02
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  ngpios:
> +    minimum: 1
> +    maximum: 32
> +    description: Number of GPIO lines supported, maximum 32.

Don't repeat constraints in free form text.

No need to resend just for that.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
<form letter>
This is an automated instruction, just in case, because many review tags
are being ignored. If you know the process, just skip it entirely
(please do not feel offended by me posting it here - no bad intentions
intended, no patronizing, I just want to avoid wasted efforts). If you
do not know the process, here is a short explanation:

Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
of patchset, under or above your Signed-off-by tag, unless patch changed
significantly (e.g. new properties added to the DT bindings). Tag is
"received", when provided in a message replied to you on the mailing
list. Tools like b4 can help here ('b4 trailers -u ...'). However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for tags received on the version they apply.

Full context and explanation:
https://elixir.bootlin.com/linux/v6.15/source/Documentation/process/submitting-patches.rst#L591
</form letter>


Best regards,
Krzysztof

Re: [PATCH v3 3/7] dt-bindings: gpio: gpio-cdns: convert to YAML

[Harshit Shah]

On 6/23/2025 11:34 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 23/06/2025 19:28, Harshit Shah wrote:
>> +
>> +  ngpios:
>> +    minimum: 1
>> +    maximum: 32
>> +    description: Number of GPIO lines supported, maximum 32.
> Don't repeat constraints in free form text.
>
> No need to resend just for that.

Got it. I will remove the "description".

> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> <form letter>
> This is an automated instruction, just in case, because many review tags
> are being ignored. If you know the process, just skip it entirely
> (please do not feel offended by me posting it here - no bad intentions
> intended, no patronizing, I just want to avoid wasted efforts). If you
> do not know the process, here is a short explanation:
>
> Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
> of patchset, under or above your Signed-off-by tag, unless patch changed
> significantly (e.g. new properties added to the DT bindings). Tag is
> "received", when provided in a message replied to you on the mailing
> list. Tools like b4 can help here ('b4 trailers -u ...'). However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for tags received on the version they apply.
>
> Full context and explanation:
> https://elixir.bootlin.com/linux/v6.15/source/Documentation/process/submitting-patches.rst#L591
> </form letter>

I was not aware of this before, apologies for the same. I will add this 
line of this from next patchset as per your suggestion.

I will take care for all the patches in this series. Thank you Krzysztof.

Regards,

Harshit.

[PATCH v3 4/7] arm64: add Axiado SoC family

[Harshit Shah]

This patch introduce ARCH_AXIADO to add the support of the Axiado
SoC for arm64 architecture.

Signed-off-by: Harshit Shah <hshah@axiado.com>
---
 arch/arm64/Kconfig.platforms | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index a541bb029aa4e1bee095ab3f44e3a52294905616..e998e1aff0fec4aca5e3bf2d0410f2578e25cb1d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -40,6 +40,12 @@ config ARCH_APPLE
 	  This enables support for Apple's in-house ARM SoC family, such
 	  as the Apple M1.
 
+config ARCH_AXIADO
+	bool "Axiado SoC Family"
+	select GPIOLIB
+	help
+	  This enables support for Axiado SoC family like AX3000
+
 menuconfig ARCH_BCM
 	bool "Broadcom SoC Support"
 

-- 
2.25.1

Re: [PATCH v3 4/7] arm64: add Axiado SoC family

[Krzysztof Kozlowski]

On 23/06/2025 19:28, Harshit Shah wrote:
> This patch introduce ARCH_AXIADO to add the support of the Axiado


Please do not use "This commit/patch/change", but imperative mood. See
longer explanation here:
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95

> SoC for arm64 architecture.
> 
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---
>  arch/arm64/Kconfig.platforms | 6 ++++++

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 4/7] arm64: add Axiado SoC family

[Harshit Shah]

On 6/23/2025 11:35 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 23/06/2025 19:28, Harshit Shah wrote:
>> This patch introduce ARCH_AXIADO to add the support of the Axiado
>
> Please do not use "This commit/patch/change", but imperative mood. See
> longer explanation here:
> https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95
Agreed. I will update this.
>
>> SoC for arm64 architecture.
>>
>> Signed-off-by: Harshit Shah <hshah@axiado.com>
>> ---
>>   arch/arm64/Kconfig.platforms | 6 ++++++
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>

Noted with thanks. I will take care from next patchset.

Regards,

Harshit.

[PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Harshit Shah]

Add initial device tree support for the AX3000 SoC and its evaluation
platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
Secure Vault, AI Engine and Firewall.

This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
controllers on the AX3000 evaluation board.

Signed-off-by: Harshit Shah <hshah@axiado.com>
---
 arch/arm64/boot/dts/Makefile              |   1 +
 arch/arm64/boot/dts/axiado/Makefile       |   2 +
 arch/arm64/boot/dts/axiado/ax3000-evk.dts |  79 +++++
 arch/arm64/boot/dts/axiado/ax3000.dtsi    | 488 ++++++++++++++++++++++++++++++
 4 files changed, 570 insertions(+)

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += amlogic
 subdir-y += apm
 subdir-y += apple
 subdir-y += arm
+subdir-y += axiado
 subdir-y += bitmain
 subdir-y += blaize
 subdir-y += broadcom
diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..6676ad07db6129f8b333b0feffee705d272517c2
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb
diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
new file mode 100644
index 0000000000000000000000000000000000000000..cc3bcf681c32430d251f20f6d52905423c182f3b
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ax3000.dtsi"
+
+/ {
+	model = "Axiado AX3000 EVK";
+	compatible = "axiado,ax3000-evk", "axiado,ax3000";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial3:115200";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		/* Cortex-A53 will use following memory map */
+		reg = <0x00000000 0x3D000000 0x00000000 0x23000000>,
+		      <0x00000004 0x00000000 0x00000000 0x80000000>;
+	};
+};
+
+/* GPIO bank 0 - 7 */
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&gpio6 {
+	status = "okay";
+};
+
+&gpio7 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..ea85ae8ca5dea5ab3288a2770b18d7aeb66cad03
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x3c0013a0 0x00000008;	/* cpu-release-addr */
+/ {
+	model = "Axiado AX3000";
+	interrupt-parent = <&gic500>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x3c0013a0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x3c0013a0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x2>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x3c0013a0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x3>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x3c0013a0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+		l2: l2-cache0 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-unified;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+	};
+
+	clocks {
+		clk_xin: clock-200000000 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			clock-output-names = "clk_xin";
+		};
+		refclk: clock-125000000 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <125000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		interrupt-parent = <&gic500>;
+
+		gic500: interrupt-controller@80300000 {
+			compatible = "arm,gic-v3";
+			reg = <0x00 0x80300000 0x00 0x10000>,
+				  <0x00 0x80380000 0x00 0x80000>;
+			ranges;
+			#interrupt-cells = <3>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		/* GPIO Controller banks 0 - 7 */
+		gpio0: gpio-controller@80500000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80500000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio1: gpio-controller@80580000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80580000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio2: gpio-controller@80600000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80600000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio3: gpio-controller@80680000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80680000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio4: gpio-controller@80700000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80700000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio5: gpio-controller@80780000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80780000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio6: gpio-controller@80800000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80800000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio7: gpio-controller@80880000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80880000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
+		/* I3C Controller 0 - 16 */
+		i3c0: i3c@80500400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80500400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c1: i3c@80500800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80500800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c2: i3c@80580400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80580400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c3: i3c@80580800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80580800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c4: i3c@80600400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80600400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c5: i3c@80600800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80600800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c6: i3c@80680400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80680400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c7: i3c@80680800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80680800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c8: i3c@80700400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80700400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c9: i3c@80700800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80700800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c10: i3c@80780400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80780400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c11: i3c@80780800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80780800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c12: i3c@80800400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80800400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c13: i3c@80800800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80800800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c14: i3c@80880400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80880400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c15: i3c@80880800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80880800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c16: i3c@80620400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80620400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		uart0: serial@80520000 {
+			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+			reg = <0x00 0x80520000 0x00 0x100>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&refclk &refclk>;
+			status = "disabled";
+		};
+		uart1: serial@805a0000 {
+			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+			reg = <0x00 0x805A0000 0x00 0x100>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&refclk &refclk>;
+			status = "disabled";
+		};
+		uart2: serial@80620000 {
+			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+			reg = <0x00 0x80620000 0x00 0x100>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&refclk &refclk>;
+			status = "disabled";
+		};
+		uart3: serial@80520800 {
+			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+			reg = <0x00 0x80520800 0x00 0x100>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&refclk &refclk>;
+			status = "disabled";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic500>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};

-- 
2.25.1

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Krzysztof Kozlowski]

On 23/06/2025 19:28, Harshit Shah wrote:
> Add initial device tree support for the AX3000 SoC and its evaluation
> platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
> Secure Vault, AI Engine and Firewall.
> 
> This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
> controllers on the AX3000 evaluation board.
> 
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---
>  arch/arm64/boot/dts/Makefile              |   1 +
>  arch/arm64/boot/dts/axiado/Makefile       |   2 +
>  arch/arm64/boot/dts/axiado/ax3000-evk.dts |  79 +++++
>  arch/arm64/boot/dts/axiado/ax3000.dtsi    | 488 ++++++++++++++++++++++++++++++
>  4 files changed, 570 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ subdir-y += amlogic
>  subdir-y += apm
>  subdir-y += apple
>  subdir-y += arm
> +subdir-y += axiado
>  subdir-y += bitmain
>  subdir-y += blaize
>  subdir-y += broadcom
> diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..6676ad07db6129f8b333b0feffee705d272517c2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb
> diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..cc3bcf681c32430d251f20f6d52905423c182f3b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ax3000.dtsi"
> +
> +/ {
> +	model = "Axiado AX3000 EVK";
> +	compatible = "axiado,ax3000-evk", "axiado,ax3000";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial3 = &uart3;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial3:115200";
> +	};
> +
> +	memory@0 {
> +		device_type = "memory";
> +		/* Cortex-A53 will use following memory map */
> +		reg = <0x00000000 0x3D000000 0x00000000 0x23000000>,

Lowercase hex, see DTS coding style.

> +		      <0x00000004 0x00000000 0x00000000 0x80000000>;
> +	};
> +};
> +
> +/* GPIO bank 0 - 7 */
> +&gpio0 {
> +	status = "okay";
> +};
> +
> +&gpio1 {
> +	status = "okay";
> +};
> +
> +&gpio2 {
> +	status = "okay";
> +};
> +
> +&gpio3 {
> +	status = "okay";
> +};
> +
> +&gpio4 {
> +	status = "okay";
> +};
> +
> +&gpio5 {
> +	status = "okay";
> +};
> +
> +&gpio6 {
> +	status = "okay";
> +};
> +
> +&gpio7 {
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	status = "okay";
> +};
> +
> +&uart3 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..ea85ae8ca5dea5ab3288a2770b18d7aeb66cad03
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
> @@ -0,0 +1,488 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/memreserve/ 0x3c0013a0 0x00000008;	/* cpu-release-addr */
> +/ {
> +	model = "Axiado AX3000";
> +	interrupt-parent = <&gic500>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0 0x0>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x3c0013a0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};

Missing blank line between each new node. See DTS coding style.

> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0 0x1>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x3c0013a0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0 0x2>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x3c0013a0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0 0x3>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x3c0013a0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +		l2: l2-cache0 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-unified;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +	};
> +
> +	clocks {
> +		clk_xin: clock-200000000 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <200000000>;
> +			clock-output-names = "clk_xin";
> +		};
> +		refclk: clock-125000000 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <125000000>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		interrupt-parent = <&gic500>;
> +
> +		gic500: interrupt-controller@80300000 {
> +			compatible = "arm,gic-v3";
> +			reg = <0x00 0x80300000 0x00 0x10000>,
> +				  <0x00 0x80380000 0x00 0x80000>;

Does not look aligned.

> +			ranges;
> +			#interrupt-cells = <3>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-controller;
> +			#redistributor-regions = <1>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		/* GPIO Controller banks 0 - 7 */
> +		gpio0: gpio-controller@80500000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80500000 0x00  0x400>;

Only one space, not double space.

> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};

Please follow DTS coding style.

> +		gpio1: gpio-controller@80580000 {
> +			compatible = "cdns,gpio-r1p02";

This should not be accepted without specific compatible, but that's some
old binding so maybe matters less. Anyway, if you ever need quirk or
custom properties they I will reject them based on what you claim here.


> +			reg = <0x00 0x80580000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio2: gpio-controller@80600000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80600000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio3: gpio-controller@80680000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80680000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio4: gpio-controller@80700000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80700000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio5: gpio-controller@80780000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80780000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio6: gpio-controller@80800000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80800000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio7: gpio-controller@80880000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80880000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		/* I3C Controller 0 - 16 */
> +		i3c0: i3c@80500400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80500400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c1: i3c@80500800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80500800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c2: i3c@80580400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80580400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c3: i3c@80580800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80580800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c4: i3c@80600400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80600400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c5: i3c@80600800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80600800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c6: i3c@80680400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80680400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c7: i3c@80680800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80680800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c8: i3c@80700400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80700400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c9: i3c@80700800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80700800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c10: i3c@80780400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80780400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c11: i3c@80780800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80780800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c12: i3c@80800400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80800400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c13: i3c@80800800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80800800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c14: i3c@80880400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80880400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c15: i3c@80880800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80880800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c16: i3c@80620400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80620400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		uart0: serial@80520000 {

Looks like not ordered by unit address. What is the ordering rule you
are going to adopt for entire arch?

> +			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";

NAK, you do not have xlnx here. Look at your SoC: name of vendor is
axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
randomly pick any compatibles and stuff them around.

Please carefully read writing bindings from DT directory.


> +			reg = <0x00 0x80520000 0x00 0x100>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "uart_clk", "pclk";
> +			clocks = <&refclk &refclk>;
> +			status = "disabled";
> +		};
Best regards,
Krzysztof

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Harshit Shah]

On 6/23/2025 11:45 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 23/06/2025 19:28, Harshit Shah wrote:
>> +     memory@0 {
>> +             device_type = "memory";
>> +             /* Cortex-A53 will use following memory map */
>> +             reg = <0x00000000 0x3D000000 0x00000000 0x23000000>,
> Lowercase hex, see DTS coding style.

I missed it. I will update it to lower case.


>
>> +     cpus {
>> +             #address-cells = <2>;
>> +             #size-cells = <0>;
>> +
>> +             cpu0: cpu@0 {
>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a53";
>> +                     reg = <0x0 0x0>;
>> +                     enable-method = "spin-table";
>> +                     cpu-release-addr = <0x0 0x3c0013a0>;
>> +                     d-cache-size = <0x8000>;
>> +                     d-cache-line-size = <64>;
>> +                     d-cache-sets = <128>;
>> +                     i-cache-size = <0x8000>;
>> +                     i-cache-line-size = <64>;
>> +                     i-cache-sets = <256>;
>> +                     next-level-cache = <&l2>;
>> +             };
> Missing blank line between each new node. See DTS coding style.

Noted, I will update between each nodes.


>
>> +             cpu1: cpu@1 {
>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a53";
>> +                     reg = <0x0 0x1>;
>> +                     enable-method = "spin-table";
>> +                     cpu-release-addr = <0x0 0x3c0013a0>;
>> +                     d-cache-size = <0x8000>;
>> +                     d-cache-line-size = <64>;
>> +                     d-cache-sets = <128>;
>> +                     i-cache-size = <0x8000>;
>> +                     i-cache-line-size = <64>;
>> +                     i-cache-sets = <256>;
>> +                     next-level-cache = <&l2>;
>> +             };
>> +             cpu2: cpu@2 {
>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a53";
>> +                     reg = <0x0 0x2>;
>> +                     enable-method = "spin-table";
>> +                     cpu-release-addr = <0x0 0x3c0013a0>;
>> +                     d-cache-size = <0x8000>;
>> +                     d-cache-line-size = <64>;
>> +                     d-cache-sets = <128>;
>> +                     i-cache-size = <0x8000>;
>> +                     i-cache-line-size = <64>;
>> +                     i-cache-sets = <256>;
>> +                     next-level-cache = <&l2>;
>> +             };
>> +             cpu3: cpu@3 {
>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a53";
>> +                     reg = <0x0 0x3>;
>> +                     enable-method = "spin-table";
>> +                     cpu-release-addr = <0x0 0x3c0013a0>;
>> +                     d-cache-size = <0x8000>;
>> +                     d-cache-line-size = <64>;
>> +                     d-cache-sets = <128>;
>> +                     i-cache-size = <0x8000>;
>> +                     i-cache-line-size = <64>;
>> +                     i-cache-sets = <256>;
>> +                     next-level-cache = <&l2>;
>> +             };
>> +             l2: l2-cache0 {
>> +                     compatible = "cache";
>> +                     cache-size = <0x100000>;
>> +                     cache-unified;
>> +                     cache-line-size = <64>;
>> +                     cache-sets = <1024>;
>> +                     cache-level = <2>;
>> +             };
>> +     };
>> +
>> +     clocks {
>> +             clk_xin: clock-200000000 {
>> +                     compatible = "fixed-clock";
>> +                     #clock-cells = <0>;
>> +                     clock-frequency = <200000000>;
>> +                     clock-output-names = "clk_xin";
>> +             };
>> +             refclk: clock-125000000 {
>> +                     compatible = "fixed-clock";
>> +                     #clock-cells = <0>;
>> +                     clock-frequency = <125000000>;
>> +             };
>> +     };
>> +
>> +     soc {
>> +             compatible = "simple-bus";
>> +             ranges;
>> +             #address-cells = <2>;
>> +             #size-cells = <2>;
>> +             interrupt-parent = <&gic500>;
>> +
>> +             gic500: interrupt-controller@80300000 {
>> +                     compatible = "arm,gic-v3";
>> +                     reg = <0x00 0x80300000 0x00 0x10000>,
>> +                               <0x00 0x80380000 0x00 0x80000>;
> Does not look aligned.

Agreed. I will update the alignment.


>
>> +                     ranges;
>> +                     #interrupt-cells = <3>;
>> +                     #address-cells = <2>;
>> +                     #size-cells = <2>;
>> +                     interrupt-controller;
>> +                     #redistributor-regions = <1>;
>> +                     interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +             };
>> +
>> +             /* GPIO Controller banks 0 - 7 */
>> +             gpio0: gpio-controller@80500000 {
>> +                     compatible = "cdns,gpio-r1p02";
>> +                     reg = <0x00 0x80500000 0x00  0x400>;
> Only one space, not double space.

Agreed. There is double space in every GPIO nodes, I will update the same.


Regards,

Harshit.

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Harshit Shah]

Thank you for the reviews. I have some questions/feedback to clarify 
before I fix some of them.

On 6/23/2025 11:45 PM, Krzysztof Kozlowski wrote:
>
> On 23/06/2025 19:28, Harshit Shah wrote:
>> +                     clocks = <&refclk>;
>> +                     interrupt-parent = <&gic500>;
>> +                     interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     status = "disabled";
>> +             };
> Please follow DTS coding style.

Sorry, I didn't got this comment. Is this for the spaces between the 
nodes or something else?

The current GPIO node is as follows:

gpio0: gpio-controller@80500000 {
                         compatible = "cdns,gpio-r1p02";
                         reg = <0x00 0x80500000 0x00 0x400>;
                         clocks = <&refclk>;
                         interrupt-parent = <&gic500>;
                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         status = "disabled";
                 };

I checked the document: 
https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/dts-coding-style.rst#L112.

>
>> +             gpio1: gpio-controller@80580000 {
>> +                     compatible = "cdns,gpio-r1p02";
> This should not be accepted without specific compatible, but that's some
> old binding so maybe matters less. Anyway, if you ever need quirk or
> custom properties they I will reject them based on what you claim here.

Yes, we are not changing anything on this driver. Is it okay?


>
>
>> +             i3c16: i3c@80620400 {
>> +                     compatible = "cdns,i3c-master";
>> +                     reg = <0x00 0x80620400 0x00 0x400>;
>> +                     clocks = <&refclk &clk_xin>;
>> +                     clock-names = "pclk", "sysclk";
>> +                     interrupt-parent = <&gic500>;
>> +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>> +                     i2c-scl-hz = <100000>;
>> +                     i3c-scl-hz = <400000>;
>> +                     #address-cells = <3>;
>> +                     #size-cells = <0>;
>> +                     status = "disabled";
>> +             };
>> +             uart0: serial@80520000 {
> Looks like not ordered by unit address. What is the ordering rule you
> are going to adopt for entire arch?

Apologies for the confusion. I should have updated in last patch-set 
comments.

We are following alphabetical ordering rule. In those we are grouping 
some nodes together based on the numbers.

cpus

clocks

soc {

    gic500 { }

    gpio0-7 { }

    i3c0-16 { }

    uart0-3 { }

}

timer


Is this okay?

>
>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
> randomly pick any compatibles and stuff them around.
>
> Please carefully read writing bindings from DT directory.


We are using the "cdns,uart-r1p12" for the UART. However, that alone 
can't be added alone in the compatible as per the DT bindings doc.

So that's the reason we have used the other node. However, which is not 
proper, understood your point. Thank you for the same.


This driver' on of the compatible is "cdns,uart-r1p12". Ref: 
https://elixir.bootlin.com/linux/v6.15/source/drivers/tty/serial/xilinx_uartps.c#L1598. 


Is it okay if we edit this file 
(https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/serial/cdns,uart.yaml#L12) 


to have the supported "OneOf" as "cdns,uart-r1p12" ?


Regards,

Harshit.

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Krzysztof Kozlowski]

On 25/06/2025 04:16, Harshit Shah wrote:
> Thank you for the reviews. I have some questions/feedback to clarify 
> before I fix some of them.
> 
> On 6/23/2025 11:45 PM, Krzysztof Kozlowski wrote:
>>
>> On 23/06/2025 19:28, Harshit Shah wrote:
>>> +                     clocks = <&refclk>;
>>> +                     interrupt-parent = <&gic500>;
>>> +                     interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>>> +                     gpio-controller;
>>> +                     #gpio-cells = <2>;
>>> +                     interrupt-controller;
>>> +                     #interrupt-cells = <2>;
>>> +                     status = "disabled";
>>> +             };
>> Please follow DTS coding style.
> 
> Sorry, I didn't got this comment. Is this for the spaces between the 
> nodes or something else?
> 
> The current GPIO node is as follows:

There is always, always line break between nodes.

> 
> gpio0: gpio-controller@80500000 {
>                          compatible = "cdns,gpio-r1p02";
>                          reg = <0x00 0x80500000 0x00 0x400>;
>                          clocks = <&refclk>;
>                          interrupt-parent = <&gic500>;
>                          interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>                          gpio-controller;
>                          #gpio-cells = <2>;
>                          interrupt-controller;
>                          #interrupt-cells = <2>;
>                          status = "disabled";
>                  };
> 
> I checked the document: 
> https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/dts-coding-style.rst#L112.
> 
>>
>>> +             gpio1: gpio-controller@80580000 {
>>> +                     compatible = "cdns,gpio-r1p02";
>> This should not be accepted without specific compatible, but that's some
>> old binding so maybe matters less. Anyway, if you ever need quirk or
>> custom properties they I will reject them based on what you claim here.
> 
> Yes, we are not changing anything on this driver. Is it okay?

I meant for future. I would expect to follow writing bindings now, so
have front specific compatible, but if you do not then whatever issues
you have in the future with this driver, they should be rejected, right?

> 
> 
>>
>>
>>> +             i3c16: i3c@80620400 {
>>> +                     compatible = "cdns,i3c-master";
>>> +                     reg = <0x00 0x80620400 0x00 0x400>;
>>> +                     clocks = <&refclk &clk_xin>;
>>> +                     clock-names = "pclk", "sysclk";
>>> +                     interrupt-parent = <&gic500>;
>>> +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>>> +                     i2c-scl-hz = <100000>;
>>> +                     i3c-scl-hz = <400000>;
>>> +                     #address-cells = <3>;
>>> +                     #size-cells = <0>;
>>> +                     status = "disabled";
>>> +             };
>>> +             uart0: serial@80520000 {
>> Looks like not ordered by unit address. What is the ordering rule you
>> are going to adopt for entire arch?
> 
> Apologies for the confusion. I should have updated in last patch-set 
> comments.
> 
> We are following alphabetical ordering rule. In those we are grouping 
> some nodes together based on the numbers.
> 
> cpus
> 
> clocks
> 
> soc {
> 
>     gic500 { }
> 
>     gpio0-7 { }
> 
>     i3c0-16 { }
> 
>     uart0-3 { }
> 
> }
> 
> timer
> 
> 
> Is this okay?

alphabetical ordering is not mentioned in dts coding style. Maybe it
should, but I think the only user of second style with grouping nodes -
Renesas - still uses ordering by unit address in general.

The trouble with your approach is that if you ever need to change the
name, you will need to re-order and move entire node.

Anyway, not a problem for me.

> 
>>
>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>> randomly pick any compatibles and stuff them around.
>>
>> Please carefully read writing bindings from DT directory.
> 
> 
> We are using the "cdns,uart-r1p12" for the UART. However, that alone 
> can't be added alone in the compatible as per the DT bindings doc.

Exactly. See writing bindings... or any guides/talks.


Best regards,
Krzysztof

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Harshit Shah]

On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
>>
>>
>>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>>> randomly pick any compatibles and stuff them around.
>>>
>>> Please carefully read writing bindings from DT directory.
>>
>> We are using the "cdns,uart-r1p12" for the UART. However, that alone
>> can't be added alone in the compatible as per the DT bindings doc.
> Exactly. See writing bindings... or any guides/talks.

We will add the "compatible = "axiado,ax-uart", "cdns,uart-r1p12". We 
will append in the dt-bindings doc and driver.

Is this name look good?

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Krzysztof Kozlowski]

On 26/06/2025 03:31, Harshit Shah wrote:
> On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
>>>
>>>
>>>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>>>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>>>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>>>> randomly pick any compatibles and stuff them around.
>>>>
>>>> Please carefully read writing bindings from DT directory.
>>>
>>> We are using the "cdns,uart-r1p12" for the UART. However, that alone
>>> can't be added alone in the compatible as per the DT bindings doc.
>> Exactly. See writing bindings... or any guides/talks.
> 
> We will add the "compatible = "axiado,ax-uart", "cdns,uart-r1p12". We 
> will append in the dt-bindings doc and driver.
> 
> Is this name look good?

No, all compatibles for SoC must be SoC specific. Take any recent
Qualcomm SM8650 or SM8750 as example.

I asked to read writing bindings. Did you read it? It covers exactly
this case.

Best regards,
Krzysztof

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Harshit Shah]

On 6/26/2025 1:50 AM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 26/06/2025 03:31, Harshit Shah wrote:
>> On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
>>>>
>>>>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>>>>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>>>>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>>>>> randomly pick any compatibles and stuff them around.
>>>>>
>>>>> Please carefully read writing bindings from DT directory.
>>>> We are using the "cdns,uart-r1p12" for the UART. However, that alone
>>>> can't be added alone in the compatible as per the DT bindings doc.
>>> Exactly. See writing bindings... or any guides/talks.
>> We will add the "compatible = "axiado,ax-uart", "cdns,uart-r1p12". We
>> will append in the dt-bindings doc and driver.
>>
>> Is this name look good?
> No, all compatibles for SoC must be SoC specific. Take any recent
> Qualcomm SM8650 or SM8750 as example.
>
> I asked to read writing bindings. Did you read it? It covers exactly
> this case.
>
Thank you for the references.

Yes, I I missed the point in the writing bindings doc. It says the 
following:

" For sub-blocks/components of bigger device (e.g. SoC blocks) use 
rather device-based compatible (e.g. SoC-based compatible), instead of 
custom versioning of that component. For example use 
"vendor,soc1234-i2c" instead of "vendor,i2c-v2"." (Ref: 
https://elixir.bootlin.com/linux/v6.15.3/source/Documentation/devicetree/bindings/writing-bindings.rst#L79) 
# We need to add the full SoC name instead of versioning. e.g. 
compatible should contain full SoC name ax3000. Another example, we have 
seen is the designware I2C IP is used by MSCC, ocelot chipset. It is 
showing as below in the following: 
(https://elixir.bootlin.com/linux/v6.16-rc3/source/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml)

i2c@100400 { compatible = "mscc,ocelot-i2c 
<https://elixir.bootlin.com/linux/v6.16-rc3/B/ident/mscc%2Cocelot-i2c>", 
"snps,designware-i2c 
<https://elixir.bootlin.com/linux/v6.16-rc3/B/ident/snps%2Cdesignware-i2c>"; 
reg = <0x100400 0x100>, <0x198 0x8>; pinctrl-0 = <&i2c_pins>; 
pinctrl-names = "default"; interrupts = <8>; clocks = <&ahb_clk>; }; # 
We will add this compatible in the existing driver 
(drivers/tty/serial/xilinx_uartps.c) & bindings 
(Documentation/devicetree/bindings/serial/cdns,uart.yaml) since the IP 
is common. As per the above examples, I see two types of bindings. 
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12" OR compatible = 
"axiado,ax3000-uart"Can you please help for this option? Apologies for 
the long thread again. Regards, Harshit.

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Harshit Shah]

On 6/26/2025 1:50 AM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 26/06/2025 03:31, Harshit Shah wrote:
>> On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
>>>>
>>>>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>>>>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>>>>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>>>>> randomly pick any compatibles and stuff them around.
>>>>>
>>>>> Please carefully read writing bindings from DT directory.
>>>> We are using the "cdns,uart-r1p12" for the UART. However, that alone
>>>> can't be added alone in the compatible as per the DT bindings doc.
>>> Exactly. See writing bindings... or any guides/talks.
>> We will add the "compatible = "axiado,ax-uart", "cdns,uart-r1p12". We
>> will append in the dt-bindings doc and driver.
>>
>> Is this name look good?
> No, all compatibles for SoC must be SoC specific. Take any recent
> Qualcomm SM8650 or SM8750 as example.
>
> I asked to read writing bindings. Did you read it? It covers exactly
> this case.
>
> Best regards,
> Krzysztof


Extremely sorry for the last reply. It got messed up in formatting, 
re-sending the same.


Thank you for the references.

Yes, I missed the point in the writing bindings doc. It says the following:


"For sub-blocks/components of bigger device (e.g. SoC blocks) use rather 
device-based compatible (e.g. SoC-based compatible),

  instead of custom versioning of that component. For example use 
"vendor,soc1234-i2c" instead of "vendor,i2c-v2"."


(Ref: 
https://elixir.bootlin.com/linux/v6.15.3/source/Documentation/devicetree/bindings/writing-bindings.rst#L79) 


# We need to add the full SoC name instead of versioning. e.g. 
compatible should contain full SoC name ax3000.


Another example, we have seen is the designware I2C IP is used by MSCC, 
ocelot chipset.

It is showing as below in the following: 
(https://elixir.bootlin.com/linux/v6.16-rc3/source/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml) 


     i2c@100400 {

       compatible = "mscc,ocelot-i2c", "snps,designware-i2c";

       reg = <0x100400 0x100>, <0x198 0x8>;

       pinctrl-0 = <&i2c_pins>;

       pinctrl-names = "default";

       interrupts = <8>;

       clocks = <&ahb_clk>;

     };


# We will add this compatible in the existing driver 
(drivers/tty/serial/xilinx_uartps.c) &

bindings (Documentation/devicetree/bindings/serial/cdns,uart.yaml) since 
the IP is common.


As per the above examples,  I see two types of bindings.

1. compatible = "axiado,ax3000-uart", "cdns,uart-r1p12"

OR

2. compatible = "axiado,ax3000-uart"

Can you please help for this options? Apologies for the long thread again.


Regards,

Harshit.

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Krzysztof Kozlowski]

On 27/06/2025 02:47, Harshit Shah wrote:
>>> Is this name look good?
>> No, all compatibles for SoC must be SoC specific. Take any recent
>> Qualcomm SM8650 or SM8750 as example.
>>
>> I asked to read writing bindings. Did you read it? It covers exactly
>> this case.
>>
>> Best regards,
>> Krzysztof
> 
> 
> Extremely sorry for the last reply. It got messed up in formatting, 
> re-sending the same.
> 
> 
> Thank you for the references.
> 
> Yes, I missed the point in the writing bindings doc. It says the following:
> 
> 
> "For sub-blocks/components of bigger device (e.g. SoC blocks) use rather 
> device-based compatible (e.g. SoC-based compatible),
> 
>   instead of custom versioning of that component. For example use 
> "vendor,soc1234-i2c" instead of "vendor,i2c-v2"."
> 
> 
> (Ref: 
> https://elixir.bootlin.com/linux/v6.15.3/source/Documentation/devicetree/bindings/writing-bindings.rst#L79) 
> 
> 
> # We need to add the full SoC name instead of versioning. e.g. 
> compatible should contain full SoC name ax3000.

Yes.

> 
> 
> Another example, we have seen is the designware I2C IP is used by MSCC, 
> ocelot chipset.
> 
> It is showing as below in the following: 
> (https://elixir.bootlin.com/linux/v6.16-rc3/source/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml) 
> 
> 
>      i2c@100400 {
> 
>        compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
> 
>        reg = <0x100400 0x100>, <0x198 0x8>;
> 
>        pinctrl-0 = <&i2c_pins>;
> 
>        pinctrl-names = "default";
> 
>        interrupts = <8>;
> 
>        clocks = <&ahb_clk>;
> 
>      };
> 
> 
> # We will add this compatible in the existing driver 
> (drivers/tty/serial/xilinx_uartps.c) &
> 
> bindings (Documentation/devicetree/bindings/serial/cdns,uart.yaml) since 
> the IP is common.
> 
> 
> As per the above examples,  I see two types of bindings.
> 
> 1. compatible = "axiado,ax3000-uart", "cdns,uart-r1p12"


This one. Thank you.


Best regards,
Krzysztof

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Harshit Shah]

On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 25/06/2025 04:16, Harshit Shah wrote:
>> gpio0: gpio-controller@80500000 {
>>                           compatible = "cdns,gpio-r1p02";
>>                           reg = <0x00 0x80500000 0x00 0x400>;
>>                           clocks = <&refclk>;
>>                           interrupt-parent = <&gic500>;
>>                           interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>>                           gpio-controller;
>>                           #gpio-cells = <2>;
>>                           interrupt-controller;
>>                           #interrupt-cells = <2>;
>>                           status = "disabled";
>>                   };
>>
>> I checked the document:
>> https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/dts-coding-style.rst#L112.
>>
>>>> +             gpio1: gpio-controller@80580000 {
>>>> +                     compatible = "cdns,gpio-r1p02";
>>> This should not be accepted without specific compatible, but that's some
>>> old binding so maybe matters less. Anyway, if you ever need quirk or
>>> custom properties they I will reject them based on what you claim here.
>> Yes, we are not changing anything on this driver. Is it okay?
> I meant for future. I would expect to follow writing bindings now, so
> have front specific compatible, but if you do not then whatever issues
> you have in the future with this driver, they should be rejected, right?

Based on the another discussion for the UART node, we understood this 
better.

It would be better if we change this GPIO nodes to with the below 
compatible.

compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02".

>
>>
>>>
>>>> +             i3c16: i3c@80620400 {
>>>> +                     compatible = "cdns,i3c-master";
>>>> +                     reg = <0x00 0x80620400 0x00 0x400>;
>>>> +                     clocks = <&refclk &clk_xin>;
>>>> +                     clock-names = "pclk", "sysclk";
>>>> +                     interrupt-parent = <&gic500>;
>>>> +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                     i2c-scl-hz = <100000>;
>>>> +                     i3c-scl-hz = <400000>;
>>>> +                     #address-cells = <3>;
>>>> +                     #size-cells = <0>;
>>>> +                     status = "disabled";
>>>> +             };
>>>> +             uart0: serial@80520000 {
>>> Looks like not ordered by unit address. What is the ordering rule you
>>> are going to adopt for entire arch?
>> Apologies for the confusion. I should have updated in last patch-set
>> comments.
>>
>> We are following alphabetical ordering rule. In those we are grouping
>> some nodes together based on the numbers.
>>
>> cpus
>>
>> clocks
>>
>> soc {
>>
>>      gic500 { }
>>
>>      gpio0-7 { }
>>
>>      i3c0-16 { }
>>
>>      uart0-3 { }
>>
>> }
>>
>> timer
>>
>>
>> Is this okay?
> alphabetical ordering is not mentioned in dts coding style. Maybe it
> should, but I think the only user of second style with grouping nodes -
> Renesas - still uses ordering by unit address in general.
>
> The trouble with your approach is that if you ever need to change the
> name, you will need to re-order and move entire node.
>
> Anyway, not a problem for me.

Okay, Thank you.


Regards,

Harshit.

Re: [PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Harshit Shah]

On 6/23/2025 10:28 AM, Harshit Shah wrote:
> +
> +		/* I3C Controller 0 - 16 */
> +		i3c0: i3c@80500400 {
> +			compatible = "cdns,i3c-master";

compatible = "axiado,ax3000-i3c", "cdns,i3c-master";

Is it better to change above as well?


Regards,

Harshit.

[PATCH v3 6/7] arm64: defconfig: enable the Axiado family

[Harshit Shah]

Enable the Axiado SoC family in the arm64 defconfig.

Signed-off-by: Harshit Shah <hshah@axiado.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 897fc686e6a91b79770639d3eb15beb3ee48ef77..96268ade08aff844ad833c18397932a059db5499 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_APPLE=y
+CONFIG_ARCH_AXIADO=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM2835=y
 CONFIG_ARCH_BCM_IPROC=y

-- 
2.25.1

Re: [PATCH v3 6/7] arm64: defconfig: enable the Axiado family

[Krzysztof Kozlowski]

On 23/06/2025 19:28, Harshit Shah wrote:
> Enable the Axiado SoC family in the arm64 defconfig.
> 
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---
>  arch/arm64/configs/defconfig | 1 +


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 6/7] arm64: defconfig: enable the Axiado family

[Harshit Shah]

On 6/23/2025 11:45 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 23/06/2025 19:28, Harshit Shah wrote:
>> Enable the Axiado SoC family in the arm64 defconfig.
>>
>> Signed-off-by: Harshit Shah <hshah@axiado.com>
>> ---
>>   arch/arm64/configs/defconfig | 1 +
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Noted with thanks. I will take care from next patchset.

Regards,

Harshit.

[PATCH v3 7/7] MAINTAINERS: Add entry for Axiado

[Harshit Shah]

Add entry for Axiado maintainer and related files

Signed-off-by: Harshit Shah <hshah@axiado.com>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0c1d245bf7b84f8a78b811e0c9c5a3edc09edc22..7a04bee308cda1d8079ef61d1c0c68bafa89fa12 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2414,6 +2414,14 @@ F:	arch/arm/boot/dts/aspeed/
 F:	arch/arm/mach-aspeed/
 N:	aspeed
 
+ARM/AXIADO ARCHITECTURE
+M:	Harshit Shah <hshah@axiado.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	Documentation/devicetree/bindings/arm/axiado.yaml
+F:	arch/arm64/boot/dts/axiado/
+N:	axiado
+
 ARM/AXM LSI SOC
 M:	Krzysztof Kozlowski <krzk@kernel.org>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

-- 
2.25.1

Re: [PATCH v3 7/7] MAINTAINERS: Add entry for Axiado

[Krzysztof Kozlowski]

On 23/06/2025 19:28, Harshit Shah wrote:
> Add entry for Axiado maintainer and related files
> 
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---
>  MAINTAINERS | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 7/7] MAINTAINERS: Add entry for Axiado

[Harshit Shah]

On 6/23/2025 11:45 PM, Krzysztof Kozlowski wrote:
> On 23/06/2025 19:28, Harshit Shah wrote:
>> Add entry for Axiado maintainer and related files
>>
>> Signed-off-by: Harshit Shah <hshah@axiado.com>
>> ---
>>   MAINTAINERS | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Thank you Krzysztof. I was not aware of this before, apologies for the 
same. I will add this line of this from next patchset as per your 
suggestion.

Regards,

Harshit.

Re: [PATCH v3 7/7] MAINTAINERS: Add entry for Axiado

[Krzysztof Kozlowski]

On 25/06/2025 01:33, Harshit Shah wrote:
> On 6/23/2025 11:45 PM, Krzysztof Kozlowski wrote:
>> On 23/06/2025 19:28, Harshit Shah wrote:
>>> Add entry for Axiado maintainer and related files
>>>
>>> Signed-off-by: Harshit Shah <hshah@axiado.com>
>>> ---
>>>   MAINTAINERS | 8 ++++++++
>>>   1 file changed, 8 insertions(+)
>>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> Thank you Krzysztof. I was not aware of this before, apologies for the 
> same. I will add this line of this from next patchset as per your 
> suggestion.

I don't understand why you are replying to my reviews and what you
wanted to say.

Please read submitting patches, which I linked in one of responses.

Best regards,
Krzysztof