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Mon, 16 Jan 2023 10:30:25 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 16 Jan 2023 10:30:25 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 16 Jan 2023 10:30:25 -0600 Received: from [10.250.234.92] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30GGUJFM063429; Mon, 16 Jan 2023 10:30:20 -0600 Message-ID: <4d7ac24a-0a35-323c-045c-cc5b3d3c715a@ti.com> Date: Mon, 16 Jan 2023 22:00:18 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Content-Language: en-US To: Roger Quadros , Siddharth Vadapalli CC: , , , , , , , , , , , , , , References: <20230111114429.1297557-1-s-vadapalli@ti.com> <20230111114429.1297557-6-s-vadapalli@ti.com> <6ae650c9-d68d-d2fc-8319-b7784cd2a749@kernel.org> <2007adb5-0980-eee3-8d2f-e30183cf408e@kernel.org> From: Vignesh Raghavendra Subject: Re: [PATCH net-next 5/5] arm64: dts: ti: k3-am625-sk: Add cpsw3g cpts PPS support In-Reply-To: <2007adb5-0980-eee3-8d2f-e30183cf408e@kernel.org> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230116_083035_730683_7FDB0FEB X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 16/01/23 9:35 pm, Roger Quadros wrote: >>>> diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts >>>> index 4f179b146cab..962a922cc94b 100644 >>>> --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts >>>> +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts >>>> @@ -366,6 +366,10 @@ &cpsw3g { >>>> pinctrl-names = "default"; >>>> pinctrl-0 = <&main_rgmii1_pins_default >>>> &main_rgmii2_pins_default>; >>>> + >>>> + cpts@3d000 { >>>> + ti,pps = <2 1>; >>>> + }; >>>> }; >>>> >>>> &cpsw_port1 { >>>> @@ -464,3 +468,19 @@ partition@3fc0000 { >>>> }; >>>> }; >>>> }; >>>> + >>>> +#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) >>> Should this go in ./include/dt-bindings/pinctrl/k3.h ? >>> That way every board DT file doesn't have to define it. >>> >>> The name should be made more platform specific. >>> e.g. K3_TS_OFFSET if it is the same for all K3 platforms. >>> If not then please add Platform name instead of K3. >> The offsets are board specific. If it is acceptable, I will add board specific >> macro for the TS_OFFSET definition in the ./include/dt-bindings/pinctrl/k3.h >> file. Please let me know. > If it is board specific then it should remain in the board file. The values you pass to macro maybe board specific. But the macro definition itself same for a given SoC right? Also, is its same across K3 family ? Please use SoC specific prefix like AM62X_TS_OFFSET() or K3_TS_OFFSET() accordingly. Regards Vignesh _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel