Re: [PATCH v3 5/7] arm64: dts: ti: k3-j722s: Add lane mux for Serdes1

From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Roger Quadros <rogerq@kernel.org>
Cc: Siddharth Vadapalli <s-vadapalli@ti.com>, <nm@ti.com>,
	<vigneshr@ti.com>, <afd@ti.com>, <kristo@kernel.org>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <u-kumar1@ti.com>,
	<danishanwar@ti.com>, <srk@ti.com>
Subject: Re: [PATCH v3 5/7] arm64: dts: ti: k3-j722s: Add lane mux for Serdes1
Date: Tue, 28 May 2024 18:12:35 +0530	[thread overview]
Message-ID: <4df26738-c86f-4180-889c-afa45ac4777f@ti.com> (raw)
In-Reply-To: <1e6242a1-2dc5-4f88-9cbb-eb14a27cccc4@kernel.org>

On Tue, May 28, 2024 at 03:23:32PM +0300, Roger Quadros wrote:
> 
> 
> On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> > The Serdes1 instance of Serdes on J722S SoC can be muxed between PCIe0
> 
> Please use SERDES insted of Serdes or serdes as it is an abbreviation.

Ok.

> 
> > and SGMII1. Update the "serdes_ln_ctrl" node adding support for the lane
> > mux of Serdes1. Additionally, set the default muxing for Serdes1 Lane0 to
> > PCIe0.
> > 
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> > Current patch is v1. No changelog.
> > 

[...]

> > @@ -96,8 +96,9 @@ usb1: usb@31200000{
> >  &main_conf {
> >  	serdes_ln_ctrl: mux-controller@4080 {
> >  		compatible = "reg-mux";
> > -		reg = <0x4080 0x4>;
> > +		reg = <0x4080 0x14>;
> >  		#mux-control-cells = <1>;
> > -		mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
> > +		mux-reg-masks = <0x0 0x3>, /* SERDES0 lane0 select */
> > +				<0x10 0x3>; /* SERDES1 lane0 select */
> 
> Why not introduce this right in the patch where you add serdes_ln_ctrl mux node?

I was preserving patch authorship from the v2 series. I will combine
this in the v4 with a Co-developed-by tag.

Regards,
Siddharth.

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