From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A5C5C64EC4 for ; Thu, 9 Mar 2023 13:14:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eYiun4mSIfYNuLxiLoBvKLAjPz5Mz6jtwYNkST7420o=; b=h3uwPt7JXmUhMT 1xZcotV40A5zrL8KzOJ1SYo1AaTPb+gO0XZXseAjVEYlU0MD4/RZV0U/4cg/LBCepqjlBi/l/TWFG W6CUbXFEjsBZQY7klJRp50trzoXvyrzP2VihoWfjBeCNseaprRcR1FRJ/CWaeTG+qIgU+UJNzy+yn 0xpyNQot1EK6gogPhTfDP5QUx5vvuhhvlicK4x2fY9/2VcyQBbMiYEPA4Ax8lN4hXFzZWArDz7DxX +sRBgHDlNdV9u/jfvqErWZmKvmVrxiMKAp28Djb+JBfFvjloQJnUWOrXvyaNeJTKyh94yhY4SFuc3 mkNB5etFkw68Q+IdD/PA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1paG5G-00A20A-VF; Thu, 09 Mar 2023 13:13:27 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1paG5D-00A1yu-QE for linux-arm-kernel@lists.infradead.org; Thu, 09 Mar 2023 13:13:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C9148C14; Thu, 9 Mar 2023 05:14:01 -0800 (PST) Received: from [10.57.91.145] (unknown [10.57.91.145]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C52B3F67D; Thu, 9 Mar 2023 05:13:16 -0800 (PST) Message-ID: <4e426dc4-6852-336f-7321-5b4df69fd430@arm.com> Date: Thu, 9 Mar 2023 13:13:11 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE fields when s2_cfg is NULL Content-Language: en-GB To: Nicolin Chen , jgg@nvidia.com, will@kernel.org Cc: eric.auger@redhat.com, kevin.tian@intel.com, baolu.lu@linux.intel.com, joro@8bytes.org, shameerali.kolothum.thodi@huawei.com, jean-philippe@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org References: <995e48fe6eb9e31c71dbe8bb80d445aa34a51819.1678348754.git.nicolinc@nvidia.com> From: Robin Murphy In-Reply-To: <995e48fe6eb9e31c71dbe8bb80d445aa34a51819.1678348754.git.nicolinc@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230309_051323_944063_6EB6BB14 X-CRM114-Status: GOOD ( 18.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2023-03-09 10:53, Nicolin Chen wrote: > From: Eric Auger > > Despite the spec does not seem to mention this, on some implementations, > when the STE configuration switches from an S1+S2 cfg to an S1 only one, > a C_BAD_STE error would happen if dst[3] (S2TTB) is not reset. Can you provide more details, since it's not clear whether this is a hardware erratum workaround or a bodge around the driver itself doing something wrong like not doing a proper break-before-make transition of the STE. The architecture explicitly states that all the STE.S2* fields except S2VMID and potentially S2S are ignored when Stage 2 is bypassed. Thanks, Robin. > Explicitly reset those two higher 64b fields, to prevent that. > > Note that this is not a bug at this moment, since a 2-stage translation > setup is not yet enabled, until the following patches add its support. > > Reported-by: Shameer Kolothum > Signed-off-by: Eric Auger > Signed-off-by: Nicolin Chen > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index c5616145e2a3..29e36448d23b 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1361,6 +1361,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); > > val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); > + } else { > + dst[2] = 0; > + dst[3] = 0; > } > > if (master->ats_enabled) _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel