Re: [PATCH v2 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 04/11/2022 09:10, Marek Vasut wrote:
> The i.MX SoCs have various power domain configurations routed into
> the PCIe IP. MX6SX is the only one which contains 2 domains and also
> uses power-domain-names. MX6QDL do not use any domains. All the rest
> uses one domain and does not use power-domain-names anymore.
> 
> Document all those configurations in the DT binding document.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: devicetree@vger.kernel.org
> ---
> V2: - Keep the power-domains description in the main section
> ---
>  .../bindings/pci/fsl,imx6q-pcie.yaml          | 55 ++++++++++++++-----
>  1 file changed, 42 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index 1cfea8ca72576..2087dab95d679 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -68,19 +68,6 @@ properties:
>      description: A phandle to an fsl,imx7d-pcie-phy node. Additional
>        required properties for imx7d-pcie and imx8mq-pcie.
>  
> -  power-domains:
> -    items:
> -      - description: The phandle pointing to the DISPLAY domain for
> -          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
> -          imx8mq-pcie.
> -      - description: The phandle pointing to the PCIE_PHY power domains
> -          for imx6sx-pcie.
> -
> -  power-domain-names:
> -    items:
> -      - const: pcie
> -      - const: pcie_phy
> -
>    resets:
>      maxItems: 3
>      description: Phandles to PCIe-related reset lines exposed by SRC
> @@ -132,6 +119,19 @@ properties:
>    phy-names:
>      const: pcie-phy
>  
> +  power-domains:
> +    minItems: 1
> +    items:
> +      - description: The phandle pointing to the DISPLAY domain for
> +          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
> +          imx8mq-pcie.
> +      - description: The phandle pointing to the PCIE_PHY power domains
> +          for imx6sx-pcie.
> +  power-domain-names:
> +    items:
> +      - const: pcie
> +      - const: pcie_phy

I don't understand why these are being moved. Commit msg also does not
explain this. While moving you make some changes so it's difficult to
review.

> +
>    reset-gpio:
>      description: Should specify the GPIO for controlling the PCI bus device
>        reset signal. It's not polarity aware and defaults to active-low reset
> @@ -241,6 +241,35 @@ allOf:
>                  - const: pcie_bus
>                  - const: pcie_phy
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: fsl,imx6sx-pcie
> +    then:
> +      properties:
> +        power-domains:
> +          minItems: 2
> +          maxItems: 2
> +        power-domain-names:
> +          minItems: 2
> +          maxItems: 2
> +    else:
> +      if:

Don't nest, it's difficult to track what is where.

> +        not:
> +          properties:
> +            compatible:
> +              contains:
> +                enum:
> +                  - fsl,imx6q-pcie
> +                  - fsl,imx6qp-pcie
> +      then:
> +        properties:
> +          power-domains:
> +            minItems: 1
> +            maxItems: 1
> +          power-domain-names: false
> +
>  examples:
>    - |
>      #include <dt-bindings/clock/imx6qdl-clock.h>

Best regards,
Krzysztof


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