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Thu, 30 Jan 2025 09:58:09 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 675A540044; Thu, 30 Jan 2025 09:56:49 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id F12E72D5869; Thu, 30 Jan 2025 09:55:47 +0100 (CET) Received: from [10.48.87.62] (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Thu, 30 Jan 2025 09:55:47 +0100 Message-ID: <4ea55395-e4e2-425e-9711-3c99f30a9fa9@foss.st.com> Date: Thu, 30 Jan 2025 09:55:46 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/9] spi: stm32: Add OSPI driver To: Mark Brown CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Philipp Zabel , Maxime Coquelin , Greg Kroah-Hartman , Arnd Bergmann , Catalin Marinas , Will Deacon , , , , , , References: <20250128081731.2284457-1-patrice.chotard@foss.st.com> <20250128081731.2284457-3-patrice.chotard@foss.st.com> Content-Language: en-US From: Patrice CHOTARD In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.87.62] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-30_05,2025-01-29_01,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250130_005819_907824_AC77E608 X-CRM114-Status: GOOD ( 16.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/28/25 13:37, Mark Brown wrote: > On Tue, Jan 28, 2025 at 09:17:24AM +0100, patrice.chotard@foss.st.com wrote: > >> +static int stm32_ospi_tx_poll(struct stm32_ospi *ospi, u8 *buf, u32 len, bool read) >> +{ > >> + if (read) >> + tx_fifo = stm32_ospi_read_fifo; >> + else >> + tx_fifo = stm32_ospi_write_fifo; > >> + tx_fifo(buf++, regs_base + OSPI_DR); > > It feels like the _tx_poll and tx_fifo naming is a landmine waiting to > surprise people in the future. The code sharing makes sense but the > naming is just looking to cause surprises, especially with it just being > a bool selecting read or write. Agree, i will replace "tx_fifo" to a more neutral name as "fifo" for example > >> +static int stm32_ospi_tx(struct stm32_ospi *ospi, const struct spi_mem_op *op) >> +{ > >> + return stm32_ospi_tx_poll(ospi, buf, op->data.nbytes, >> + op->data.dir == SPI_MEM_DATA_IN); > > Though the one caller is also using _tx only naming, it's a bit more > tied in with the op sending though. I will replace stm32_ospi_tx_poll() by stm32_ospi_poll() > >> + ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | >> + SPI_TX_DUAL | SPI_TX_QUAD | >> + SPI_TX_OCTAL | SPI_RX_OCTAL; >> + ctrl->setup = stm32_ospi_setup; >> + ctrl->bus_num = -1; >> + ctrl->mem_ops = &stm32_ospi_mem_ops; >> + ctrl->use_gpio_descriptors = true; >> + ctrl->transfer_one_message = stm32_ospi_transfer_one_message; >> + ctrl->num_chipselect = STM32_OSPI_MAX_NORCHIP; >> + ctrl->dev.of_node = dev->of_node; > > It looks like the controller only does half duplex as well so it should > set SPI_CONTROLLER_HALF_DUPLEX. Right, i will add it. Thanks Patrice