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d="scan'208";a="88967171" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2026 04:47:21 -0700 X-CSE-ConnectionGUID: G6cPanw3St+oo08ir6C0kQ== X-CSE-MsgGUID: Z+tNzAXeQFy/qftCJFxY9w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="311254377" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.24]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2026 04:47:12 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Tue, 15 Sep 2026 14:47:07 +0300 (EEST) To: Long Zhao cc: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial , LKML Subject: Re: [PATCH v7 13/15] serial: 8250_dw: add Ambarella CV75 quirks In-Reply-To: <20260915-cv75-v5-v7-13-3297d3fbc9c0@ambarella.com> Message-ID: <4eca948b-ebf7-ee86-78e8-af886f19ed0c@linux.intel.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> <20260915-cv75-v5-v7-13-3297d3fbc9c0@ambarella.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323328-710529132-1789472827=:1365" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260915_124724_487848_3BB7AC10 X-CRM114-Status: GOOD ( 20.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-710529132-1789472827=:1365 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE On Tue, 15 Sep 2026, Long Zhao via B4 Relay wrote: > From: Long Zhao >=20 > The Ambarella CV75 UART is Ambarella IP, not a Synopsys DesignWare > licensed block. At the register level it is close enough to DW APB UART > that a full custom UART driver is unnecessary: reuse 8250_dw with a > small platform quirk. >=20 > Quirks: > - keep IER ETOI (bit 5) set for RX timeout behaviour > - skip set_rate; baud clock is managed outside the UART block >=20 > Reviewed-by: Linus Walleij > Signed-off-by: Long Zhao > --- > drivers/tty/serial/8250/8250_dw.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) >=20 > diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/= 8250_dw.c > index 5fba913f3301..19431c476c55 100644 > --- a/drivers/tty/serial/8250/8250_dw.c > +++ b/drivers/tty/serial/8250/8250_dw.c > @@ -43,6 +43,9 @@ > #define RZN1_UART_xDMACR_8_WORD_BURST=09(2 << 1) > #define RZN1_UART_xDMACR_BLK_SZ(x)=09((x) << 3) > =20 > +/* Ambarella IER: receive timeout interrupt enable */ > +#define AMBARELLA_UART_IER_ETOI=09=09BIT(5) > + > /* Quirks */ > #define DW_UART_QUIRK_OCTEON=09=09BIT(0) > #define DW_UART_QUIRK_ARMADA_38X=09BIT(1) > @@ -60,6 +63,7 @@ > =20 > struct dw8250_platform_data { > =09u8 usr_reg; > +=09u8 ier_mask; > =09u32 cpr_value; > =09unsigned int quirks; > }; > @@ -572,6 +576,25 @@ static void dw8250_prepare_rx_dma(struct uart_8250_p= ort *p) > =09dw8250_writel_ext(up, RZN1_UART_RDMACR, val); > } > =20 > +static int dw8250_ier_mask_startup(struct uart_port *p) > +{ > +=09struct dw8250_data *d =3D to_dw8250_data(p->private_data); > +=09struct uart_8250_port *up =3D up_to_u8250p(p); > +=09int ret; > + > +=09ret =3D serial8250_do_startup(p); > +=09if (ret) > +=09=09return ret; > + > +=09/* > +=09 * Ambarella keeps variant IER bits (e.g. ETOI) set for correct RX > +=09 * timeout behaviour. > +=09 */ > +=09up->ier |=3D d->pdata->ier_mask; > + > +=09return 0; > +} > + > static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) > { > =09unsigned int quirks =3D data->pdata->quirks; > @@ -606,6 +629,8 @@ static void dw8250_quirks(struct uart_port *p, struct= dw8250_data *data) > =09=09p->serial_in =3D dw8250_serial_in32; > =09=09data->uart_16550_compatible =3D true; > =09} > +=09if (data->pdata->ier_mask) > +=09=09p->startup =3D dw8250_ier_mask_startup; > } > =20 > static void dw8250_reset_control_assert(void *data) > @@ -879,6 +904,12 @@ static const struct dw8250_platform_data dw8250_intc= 10ee =3D { > =09.quirks =3D DW_UART_QUIRK_IER_KICK, > }; > =20 > +static const struct dw8250_platform_data dw8250_ambarella_cv75_data =3D = { > +=09.usr_reg =3D DW_UART_USR, > +=09.ier_mask =3D AMBARELLA_UART_IER_ETOI, > +=09.quirks =3D DW_UART_QUIRK_SKIP_SET_RATE, > +}; > + > static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = =3D { > =09.usr_reg =3D DW_UART_USR, > =09.cpr_value =3D FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | > @@ -889,6 +920,7 @@ static const struct dw8250_platform_data dw8250_ultra= risc_dp1000_data =3D { > }; > =20 > static const struct of_device_id dw8250_of_match[] =3D { > +=09{ .compatible =3D "ambarella,cv75-uart", .data =3D &dw8250_ambarella_= cv75_data }, > =09{ .compatible =3D "snps,dw-apb-uart", .data =3D &dw8250_dw_apb }, > =09{ .compatible =3D "cavium,octeon-3860-uart", .data =3D &dw8250_octeon= _3860_data }, > =09{ .compatible =3D "marvell,armada-38x-uart", .data =3D &dw8250_armada= _38x_data }, Reviewed-by: Ilpo J=C3=A4rvinen --=20 i. --8323328-710529132-1789472827=:1365--