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X-CSE-ConnectionGUID: 3j892OOuQlOYOLfdP/5oNA== X-CSE-MsgGUID: wCi4gz88QPKpFod2uMHDmA== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="53028422" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="53028422" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 21:42:59 -0800 X-CSE-ConnectionGUID: g55xazAASY6gp1sqPcfseQ== X-CSE-MsgGUID: 9IDYRVS6RdmXV8k/XcCKXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="189924294" Received: from allen-sbox.sh.intel.com (HELO [10.239.159.30]) ([10.239.159.30]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 21:42:54 -0800 Message-ID: <4eeda61a-c71d-4ad1-8ac7-a14942f7a864@linux.intel.com> Date: Tue, 18 Nov 2025 13:38:40 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/5] pci: Suspend iommu function prior to resetting a device To: Nicolin Chen , "Tian, Kevin" Cc: "joro@8bytes.org" , "afael@kernel.org" , "bhelgaas@google.com" , "alex@shazbot.org" , "jgg@nvidia.com" , "will@kernel.org" , "robin.murphy@arm.com" , "lenb@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-pci@vger.kernel.org" , "kvm@vger.kernel.org" , "patches@lists.linux.dev" , "Jaroszynski, Piotr" , "Sethi, Vikram" , "helgaas@kernel.org" , "etzhao1900@gmail.com" References: Content-Language: en-US From: Baolu Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251117_214302_283887_4945B612 X-CRM114-Status: GOOD ( 14.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/18/25 09:42, Nicolin Chen wrote: > On Tue, Nov 18, 2025 at 12:29:43AM +0000, Tian, Kevin wrote: >>> From: Nicolin Chen >>> Sent: Tuesday, November 18, 2025 3:27 AM >>> >>> On Mon, Nov 17, 2025 at 04:52:05AM +0000, Tian, Kevin wrote: >>>>> From: Nicolin Chen >>>>> Sent: Saturday, November 15, 2025 2:01 AM >>>>> >>>>> On Fri, Nov 14, 2025 at 09:45:31AM +0000, Tian, Kevin wrote: >>>>>>> From: Nicolin Chen >>>>>>> Sent: Tuesday, November 11, 2025 1:13 PM >>>>>>> >>>>>>> +/* >>>>>>> + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software >>> disables >>>>> ATS >>>>>>> before >>>>>>> + * initiating a reset. Notify the iommu driver that enabled ATS. >>>>>>> + */ >>>>>>> +int pci_reset_iommu_prepare(struct pci_dev *dev) >>>>>>> +{ >>>>>>> + if (pci_ats_supported(dev)) >>>>>>> + return iommu_dev_reset_prepare(&dev->dev); >>>>>>> + return 0; >>>>>>> +} >>>>>> the comment says "driver that enabled ATS", but the code checks >>>>>> whether ATS is supported. >>>>>> >>>>>> which one is desired? >>>>> The comments says "the iommu driver that enabled ATS". It doesn't >>>>> conflict with what the PCI core checks here? >>>> actually this is sent to all IOMMU drivers. there is no check on whether >>>> a specific driver has enabled ATS in this path. >>> But the comment doesn't say "check".. >>> >>> How about "Notify the iommu driver that enables/disables ATS"? >>> >>> The point is that pci_enable_ats() is called in iommu drivers. >>> >> but in current way even an iommu driver which doesn't call >> pci_enable_ats() will also be notified then I didn't see the >> point of adding an attribute to "the iommu driver". > Hmm, that's a fair point. > > Having looked closely, I see only AMD and ARM call that to enable > ATs. How others (e.g. Intel) enable it? The VT-d driver enables ATS in the iommu probe_finalize() path (for scalable mode). static void intel_iommu_probe_finalize(struct device *dev) { [...] if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) { iommu_enable_pci_ats(info); /* Assign a DEVTLB cache tag to the default domain. */ if (info->ats_enabled && info->domain) { u16 did = domain_id_iommu(info->domain, iommu); if (cache_tag_assign(info->domain, did, dev, IOMMU_NO_PASID, CACHE_TAG_DEVTLB)) iommu_disable_pci_ats(info); } } [...] } iommu_enable_pci_ats() will eventually call pci_enable_ats() after some necessary checks. Thanks, baolu